JP2003273395A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device manufactured using semiconductor capable of forming a film on silicon or silicon substrate and emitting or modulating light at a room temperature efficiently. <P>SOLUTION: The semiconductor device is provided with an n-type silicon substrate 1, an n-type silicon layer 2, a silicon/germanium superlattice layer 5 where Be doped silicon germanium layers 3 and i-type silicon layers 4 are laminated, a p-type silicon layer 6, a p-side electrode 7, and an n-side electrode 8. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, it relates to a semiconductor device having high luminous efficiency or excellent light modulation characteristics by introducing an impurity serving as an isoelectrotrap into a silicon-based superlattice structure.

[0002]

2. Description of the Related Art Since silicon is an indirect transition semiconductor, it has a low luminous efficiency and is usually used for semiconductor lasers and LEDs (li).
It is not possible to fabricate a light emitting device such as a glow emitting diode). If a light-emitting element can be fabricated from silicon or a semiconductor that can be formed on a silicon substrate, new optoelectronic integrated circuit technology will be spread by fusing with silicon LSI technology, and its impact is immeasurable. Therefore, researches on light-emitting elements such as silicon germanium which can be formed on silicon or a silicon substrate have been widely researched, but none for practical use has been obtained yet.

FIG. 9 shows, for example, PL Bradfield et. Al., A.
1 schematically shows a sectional structure of a conventional silicon light emitting device shown in ppl.Phys.Lett.vol.55, no.2, p.100 (1989).

As shown in FIG. 9, an S, O-doped silicon layer 16 doped with sulfur and oxygen and a p-type silicon layer 6 are formed on an n-type silicon substrate 1 through an n-type silicon layer 2. Further, a p-side electrode 7 and an n-side electrode 8 are formed above and below these, respectively. In the S, O-doped silicon layer 16, sulfur and oxygen are arranged at the lattice positions of silicon, and they form a complex to form an electrically neutral isoelectronic trap.

[0005]

The conventional silicon light emitting device is configured as described above, and forward voltage (p-side electrode 7 is positive, n-side electrode 8 is positive) is applied to the p-side electrode 7 and the n-side electrode 8. negative)
Is applied, holes are injected from the p-side electrode 7 and electrons are injected into the S, O-doped silicon layer 16 from the n-side electrode 8, respectively. Here, the isoelectronic trap has a property of easily catching an electron, and the electron is localized near the trap. The spatial localization of electrons in this way means that they are spread in wavenumber space,
Near the Γ point, holes and direct transition excitons recombine and emit light. Such a phenomenon is also observed in gallium phosphide, which is also an indirect transition semiconductor, and LEDs have been put to practical use.

However, in the case of silicon, since the binding energy of excitons is small, such exciton recombination is observed only at low temperature, and light emission is not performed at room temperature. It is also difficult to change the amount of light absorption using an isoelectronic trap at room temperature.

Therefore, the present invention can be made of silicon or a semiconductor capable of forming a film on a silicon substrate,
An object of the present invention is to provide a semiconductor device which can efficiently emit light or modulate light at room temperature.

[0008]

A semiconductor device according to the present invention, a first semiconductor layer of a first conductivity type, and an isoelectronic trap including a silicon layer and a silicon germanium layer formed on the first semiconductor layer are formed. A superlattice layer containing impurities, a second conductivity type second semiconductor layer formed on the superlattice layer, a first electrode on the first semiconductor layer side, and a second electrode on the second semiconductor layer side. Equipped with. Here, the “semiconductor layer” may be a single layer or a plurality of layers, and the “semiconductor layer” is defined to include a semiconductor substrate.

It is preferable that one of the silicon layer and the silicon germanium layer is lattice-matched and one is strained with respect to the other, and that one of the silicon layer and the silicon germanium layer is doped with an impurity forming an isoelectronic trap.

The semiconductor device may be a light emitting device which emits light by applying a voltage between the first and second electrodes,
It may be an optical modulator that modulates the amount of light absorption by applying a voltage between the first and second electrodes.

The thickness of the layer containing impurities forming the isoelectronic trap is set to 2 nm to 10 nm.
The following is preferable.

It is preferable to use at least one material selected from sulfur, beryllium, selenium, zinc, carbon and tin as the impurities forming the isoelectronic trap.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to FIGS.

(First Embodiment) FIG. 1 schematically shows a sectional structure of a silicon light emitting element (semiconductor device) according to a first embodiment of the present invention.

As shown in FIG. 1, on an n-type silicon substrate (semiconductor substrate) 1, an n-type silicon layer (semiconductor layer) 2 is electrically intrinsic (n-type or p-type is intentionally doped). A silicon / silicon germanium superlattice layer 5 and a p-type silicon layer 6 which are not formed), and a p-side electrode 7 and an n-side electrode 8 are formed respectively above and below them.

The silicon / silicon germanium superlattice layer 5 has a laminated structure of semiconductor layers, and in the example of FIG.
Doped silicon germanium layer 3 and i-type silicon layer 4
It has a laminated structure with. The silicon germanium layer 3 is
Since the lattice constant is larger than that of silicon, compressive strain is applied, and beryllium (Be) that is an impurity forming an isoelectronic trap is doped.

The thickness of the silicon germanium layer (semiconductor layer) 3 containing beryllium, which is an impurity forming the isoelectronic trap, is preferably 2 nm or more and 10 nm or less. As a result, the region in which holes or electrons are confined is narrowed, so that the binding energy of excitons increases greatly, and the effect of excitons is sufficiently exhibited at room temperature. The beryllium doping amount is, for example, 1
It is about × 10 ¹⁷ to 1 × 10 ¹⁹ cm ⁻³ . Further, beryllium does not need to be uniformly doped in the silicon germanium layer 3, and even if the center portion of the layer has a high concentration distribution, the effect of the present invention is not impaired.
Further, even if beryllium is diffused into the silicon layer 4 by thermal diffusion or the like, the effect of the present invention can be obtained as long as beryllium in the silicon germanium layer 3 has a higher concentration.

The energy band diagram of the silicon / silicon germanium superlattice layer 5 is shown in FIG. 2, and holes are strongly confined in the silicon germanium layer.

The structure as described above can be produced by forming a semiconductor layer using a molecular beam epitaxial growth apparatus, a chemical vapor deposition apparatus under reduced pressure or ultra-high vacuum, and an ordinary electrode forming method.

In the silicon light emitting device having the above-described structure, when a forward voltage is applied to the p-side electrode 7 and the n-side electrode 8 as in the conventional example, holes are emitted from the p-side electrode 7 and n-side electrode 8 is generated. Electrons are injected into the superlattice region, respectively. The electrons injected into the silicon germanium layer 3 are bound to the isoelectronic trap as in the conventional example, and are further bound to holes by Coulomb force to form bound excitons.

At this time, in the present invention, holes are strongly confined in the silicon germanium layer 3, so that the bond with the electron is strengthened and the binding energy of excitons is increased. Therefore, excitons are stably present even at room temperature, and light emission is obtained by exciton recombination.

(Second Embodiment) Next, a second embodiment of the present invention will be described with reference to FIGS. FIG. 3 schematically shows a cross-sectional structure of the silicon light emitting element according to the second embodiment.

As shown in FIG. 3, on the n-type silicon substrate 1, an n-type buffer layer 9 for reducing dislocations in the upper layer film, a lattice-relaxed n-type silicon germanium layer 10, and an electrically intrinsic silicon germanium / Silicon superlattice layer 17, lattice-relaxed p-type silicon germanium layer 13
Are formed, and the p-side electrodes 7 and n are formed above and below, respectively.
The side electrode 8 is formed.

The silicon germanium / silicon superlattice layer 17 has a laminated structure of an i-type silicon germanium layer 11 and a Be-doped silicon layer 12. Since the silicon germanium / silicon superlattice layer 17 matches the lattice constant of silicon germanium, tensile strain is applied to the silicon layer. Further, the silicon layer is doped with beryllium, which is an impurity forming an isoelectronic trap.

In this case, the energy band diagram of the silicon germanium / silicon superlattice layer 17 is as shown in FIG. 4, and unlike the case of FIG. 2, electrons are strongly confined in the silicon layer. Note that the structure of this embodiment mode can also be manufactured by a method similar to that of Embodiment Mode 1.

In the silicon light emitting device having the above-described structure, when a forward voltage is applied to the p-side electrode 7 and the n-side electrode 8 as in the first embodiment, holes are emitted from the p-side electrode 7.
Electrons are injected into the superlattice region from the n-side electrode 8. The electrons injected into the silicon layer having the isoelectronic trap are bound to the isoelectronic trap as in the conventional example, and are further bound to holes by Coulomb force to form bound excitons.

At this time, in the present invention, since electrons are strongly confined in the silicon layer,
The bond to the isoelectronic trap becomes stronger. Therefore, the binding energy of excitons becomes large, the excitons exist stably even at room temperature, and light emission by exciton recombination can be obtained.

(Third Embodiment) Next, a third embodiment of the present invention will be described. Although the silicon light emitting element has been described in the above embodiments, an optical modulator can be configured using a similar structure.

FIG. 5 schematically shows a sectional structure of the optical modulator formed on the silicon substrate 1.

As shown in FIG. 5, an n-type silicon layer 2 and an electrically intrinsic (n
A silicon / silicon germanium superlattice layer 5 and a p-type silicon layer 6 which are not intentionally doped into a p-type or a p-type), and a p-side electrode 7 and an n-side electrode 8 are formed respectively above and below them. Has been done.

Since the silicon germanium layer has a lattice constant larger than that of silicon, a compressive strain is applied thereto, and beryllium which is an impurity forming an isoelectronic trap is further doped. An antireflection film 14 is formed on both end faces (side faces) of the above structure. As the antireflection film 14, a dielectric multilayer film such as TiO ₂ / SiO ₂ can be used.

In the silicon optical modulator configured as described above, the light absorption characteristics when no voltage is applied to the p-side electrode 7 and the n-side electrode 8 are as shown in FIG. However, since excitons are stably present, it exhibits a characteristic with a sharp absorption peak. When a reverse voltage (reverse bias) is applied to the p-side electrode 7 and the n-side electrode 8, the absorption peak shifts to the long wavelength side due to the deformation of the energy band structure of the superlattice layer 5.

At this time, if the wavelength of the input light is set as shown in FIG. 6, the amount of absorption is small when no voltage is applied, and the amount of absorption increases when a reverse voltage is applied. The intensity of light can be modulated.

(Fourth Embodiment) Next, a fourth embodiment of the present invention will be described with reference to FIG. FIG. 7 is a sectional view of the semiconductor device according to the fourth embodiment.

As shown in FIG. 7, in the fourth embodiment,
An antireflection film 14 is formed on both side surfaces of the device having the structure shown in FIG. As the antireflection film 14, the same film as that of the third embodiment can be used. The other configuration is the same as that shown in FIG. 3, and therefore its explanation is omitted.

Also in the case of the fourth embodiment, the light absorption characteristic of the silicon optical modulator shifts depending on the presence / absence of reverse bias application as in the case shown in FIG. Therefore, similarly to the third embodiment, the optical modulator on the silicon substrate 1 shown in FIG. 7 can also modulate the transmitted light intensity by applying a voltage.

(Fifth Embodiment) Next, a fifth embodiment of the present invention will be described. FIG. 8 is a perspective view showing a semiconductor device according to the fifth embodiment.

In each of the above-described embodiments, the cross-sectional structure of each device has been described. However, a ridge waveguide structure as shown in FIG. 8 is used to confine light in the lateral direction (left-right direction in FIG. 8). Therefore, it is possible to improve light emission and light modulation characteristics.

In the semiconductor device according to the fifth embodiment, as shown in FIG. 8, a silicon / silicon germanium superlattice layer 5 and a p-type silicon layer 6 are formed on an n-type silicon layer 2, and they are formed above and below them. A p-side electrode 7 and an n-side electrode 8 are formed, respectively.

The p-type silicon layer 6 has a convex portion at the center, and the convex portion extends in the longitudinal direction (longitudinal direction) of the device. The insulating film 15 is formed on the p-type silicon layer 6 so as to have an opening on this convex portion. A p-side electrode 7 is formed on the insulating film 15 so as to cover the convex portion of the p-type silicon layer 6. With such a structure, lateral light can be confined by the device of this embodiment.

(Embodiment 6) In the above embodiments,
Although the case where beryllium is used as an impurity forming the isoelectronic trap has been described, at least one material selected from sulfur, beryllium, selenium, zinc, carbon, tin, or an equivalent impurity having a function similar to these is used. Even if it is used, the same effect can be obtained.

Although the embodiments of the present invention have been described above, the features of the respective embodiments may be combined as appropriate. Further, it should be considered that the embodiments disclosed this time are exemplifications in all points and not restrictive. The scope of the invention is indicated by the claims,
All modifications that come within the meaning and range of equivalency of the claims are to be embraced.

[0043]

According to the present invention, by providing a superlattice layer containing an impurity forming an isoelectronic trap, which includes a silicon layer and a silicon germanium layer, electrons or holes are contained in the silicon layer or the silicon germanium layer. Can be confined. For example, by introducing the above impurities into the silicon germanium layer,
Holes can be confined in the silicon germanium layer, the binding energy of excitons bound to the isoelectronic trap is increased, and light can be efficiently emitted at room temperature. Further, by introducing the above impurities into the silicon layer, electrons can be confined in the silicon layer, the binding energy of excitons bound to the isoelectronic trap is increased, and light can be efficiently emitted at room temperature.

It should be noted that the silicon layer and the silicon germanium layer are lattice-matched and one is distorted with respect to the other, and one of the silicon layer and the silicon germanium layer is doped with an impurity that forms an isoelectronic trap. The effect of is remarkable, and it is possible to efficiently emit light at room temperature.

The semiconductor device of the present invention has the first structure as described above.
It is useful as a light emitting device that emits light by applying a voltage between the first and second electrodes, but is also useful as an optical modulator that modulates the amount of light absorption by applying a voltage between the first and second electrodes. . For example, when the impurities are introduced into the silicon germanium layer to confine holes in the silicon germanium layer, the binding energy of excitons bound to the isoelectronic trap increases, so that the light generated when a voltage is applied is increased. The absorption amount change can be increased. Also, when the impurities are introduced into the silicon layer and electrons are confined in the silicon layer, the binding energy of excitons bound to the isoelectronic trap increases, so the amount of light absorbed when a voltage is applied. The change can be large.

The thickness of the layer containing impurities forming the isoelectronic trap is set to 2 nm or more and 10 nm.
In the following cases, the region in which holes or electrons are confined is narrowed, so that the binding energy of excitons increases greatly, and the effect of excitons is sufficiently exhibited at room temperature.

When at least one material selected from sulfur, beryllium, selenium, zinc, carbon and tin is used as the impurity forming the isoelectronic trap, the isoelectronic trap can be efficiently formed.

[Brief description of drawings]

FIG. 1 is a sectional view of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is an energy band diagram of the silicon / silicon germanium superlattice layer of FIG.

FIG. 3 is a sectional view of a semiconductor device according to a second embodiment of the present invention.

FIG. 4 is an energy band diagram of the silicon germanium / silicon superlattice layer of FIG.

FIG. 5 is a sectional view of a semiconductor device according to a third embodiment of the present invention.

FIG. 6 is a diagram showing light absorption characteristics of the semiconductor device of the present invention.

FIG. 7 is a sectional view of a semiconductor device according to a fourth embodiment of the present invention.

FIG. 8 is a perspective view of a semiconductor device according to a fifth embodiment of the present invention.

FIG. 9 is a cross-sectional view of a conventional semiconductor device.

[Explanation of symbols]

1 n-type silicon substrate, 2 n-type silicon layer, 3 Be
Doped silicon germanium layer, 4 i-type silicon layer,
5 silicon / silicon germanium superlattice layer, 6 p
Type silicon layer, 7 p-side electrode, 8 n-side electrode, 9 n-type buffer layer, 10 n-type silicon germanium layer, 11
i-type silicon germanium layer, 12Be-doped silicon layer, 13 p-type silicon germanium layer, 14 antireflection film, 15 insulating film, 16 S, O-doped silicon layer, 17 silicon germanium / silicon superlattice layer.

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Shigemitsu Maruno             2-3 2-3 Marunouchi, Chiyoda-ku, Tokyo             Inside Ryo Electric Co., Ltd. (72) Inventor Akinori Tokuda             2-3 2-3 Marunouchi, Chiyoda-ku, Tokyo             Inside Ryo Electric Co., Ltd. F-term (reference) 2H079 AA02 AA13 BA01 CA05 DA16                       EA03                 5F041 CA05 CA33 CA50 CA53 CA56                       CA57 CA66                 5F073 AA74 CA24 CB04 CB18 DA06

Claims (6)

[Claims] 1. A first semiconductor layer of a first conductivity type, a superlattice layer formed on the first semiconductor layer, containing a silicon layer and a silicon germanium layer, and containing impurities forming an isoelectronic trap. A semiconductor device comprising a second conductive type second semiconductor layer formed on the superlattice layer, a first electrode on the side of the first semiconductor layer, and a second electrode on the side of the second semiconductor layer. . 2. The silicon layer and the silicon germanium layer are lattice-matched and one is strained with respect to the other, and one of the silicon layer and the silicon germanium layer is doped with an impurity forming the isoelectronic trap, The semiconductor device according to claim 1. 3. The semiconductor device according to claim 1, wherein the semiconductor device emits light when a voltage is applied between the first and second electrodes. 4. The semiconductor device according to claim 1, wherein the semiconductor device modulates the amount of light absorption by applying a voltage between the first and second electrodes. 5. The thickness of the layer containing impurities forming the isoelectronic trap is 2 nm or more and 10 n or less.
The semiconductor device according to any one of claims 1 to 4, which has a thickness of m or less. 6. The impurities forming the isoelectronic trap include sulfur, beryllium, selenium,
The semiconductor device according to claim 1, wherein at least one material selected from zinc, carbon, and tin is used.