JP2003273284A - Semiconductor packaging substrate and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor packaging substrate in which, by a method for providing an external connection terminal by etching and next embedding a resin as a base material, the bottom of the obtained connection terminal is formed greater than the top thereof, thereby solving restriction items on a circuit side, and the top of the connection terminal is formed greater than the bottom thereof, thereby forming higher density wiring. <P>SOLUTION: In a semiconductor packaging substrate having a plurality of pillar-like external connection terminals on the surface thereof, the bottom of the external connection terminal is formed smaller than the top of the external connection terminal. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package substrate and a method for manufacturing the same.

[0002]

2. Description of the Related Art With the recent high-density mounting of electronic parts,
There is a growing demand for improvement in the wiring density of wiring boards. Further, similar demands are increasing for semiconductor packages mounted on wiring boards. Generally, in the case of a semiconductor package, there are a type in which input / output terminals are arranged in a row in the periphery of the package, and a type in which not only the periphery but also the inside are arranged in multiple rows. The former is typically a QFP (Quad Flat Package). When the number of terminals is increased, it is necessary to reduce the terminal pitch, but in the area of 0.5 mm pitch or less, a high level technique is required for connection with the wiring board. The latter array type is suitable for increasing the number of pins because the terminals can be arranged at a relatively large pitch. Conventionally, an array type is generally a PGA (Pin Grid Array) having connection pins, but the connection with a wiring board is an insertion type and is not suitable for surface mounting. Therefore, surface mountable BG
A package called A (Ball Grid Array) has been developed.

On the other hand, with the miniaturization of electronic equipment, there is an increasing demand for further miniaturization of the package size. To cope with this miniaturization, a so-called chip size package (CS
P; Chip Size Package) is proposed. this is,
This is a package having a connection portion with an external wiring board, that is, an external connection terminal, in the mounting region, not in the peripheral portion of the semiconductor chip. As a specific example, a polyimide film with bumps is adhered to the surface of a semiconductor chip, electrical contact is made with the chip and gold lead wires, and then epoxy resin is potted and sealed (NIKKEI MATERIALS & TECHNOLOG
Y 94.4, No.140, p18-19) or a metal bump is formed on the temporary substrate at a position corresponding to the connection part with the semiconductor chip and the external wiring board, and the semiconductor chip is face down bonded on the temporary substrate. Transfer molded (Smal
lest Flip-Chip-Like Package CSP; The Second VLSI P
ackaging Workshop of Japan, p46-50, 1994). In all of these semiconductor packages, a circuit formed on the package substrate and a connection terminal are connected between the circuit formed on the package substrate and the connection terminal for connection between the connection terminal and the semiconductor chip. Through holes and via holes are used for connection. Through hole,
The via hole is generally a method in which a hole is formed beforehand with a drill or a laser at the connection terminal of the base material, and the external connection terminal is provided by filling solder or conductive paste, but this method reduces the diameter of the hole. Is limited. Therefore, a method has been studied in which an external connection terminal is provided by etching in advance and a resin to be a base material is embedded later.

[0004]

However, in this etching method, the bottom diameter is usually larger than the top diameter of the obtained connection terminal, and the larger the bottom diameter, the greater the restrictions on the circuit side. . To solve this problem, the present invention provides a substrate for a semiconductor package that enables higher density wiring by making the top diameter of the connection terminal larger than the bottom diameter.

[0005]

SUMMARY OF THE INVENTION The present invention is a semiconductor package substrate having a plurality of columnar external connection terminals on its surface, wherein the bottom diameter of the external connection terminals is smaller than the top diameter of the external connection terminals. The present invention relates to a semiconductor package substrate.

The present invention also provides a step of providing a first resist at a location where an external connection terminal of a first metal layer of a multilayer body composed of two or more layers having a first metal layer as an upper layer is to be formed, A step of half-etching the first metal layer, a step of peeling the first resist, and a second step on the upper surface and the side surface of the protruding portion of the first metal layer generated by the half etching.
And a step of over-etching the first metal layer not provided with the second resist, the method for manufacturing a semiconductor package substrate.

The present invention also provides a step of providing a resist at a location where an external connection terminal of the first metal layer of the multilayer body composed of two or more layers having the first metal layer as an upper layer is formed, The step of half-etching the metal layer of No. 1
And a step of over-etching the first metal layer on which the resist is not provided, and a step of providing a resist on the upper surface and the side surface of the protruding portion of the metal layer.

In the present invention, the multilayer body composed of two or more layers is a multilayer body of three or more layers, the lower layer of the first metal layer is an etching barrier layer, and the first metal layer is over-etched up to the etching barrier layer. The present invention also relates to a method for manufacturing the above semiconductor package substrate.

According to the present invention, the external connection terminal of the first metal layer of the multi-layer body having three or more layers having the two metal layers of the first metal layer and the second metal layer as the upper layer is formed. A step of providing a resist at an appropriate position, a step of providing the metal resist by etching the first metal layer, and a step of overetching the second metal layer of the metal resist not provided with the resist by selective etching The present invention relates to a method for manufacturing a semiconductor package substrate.

In the present invention, the multilayer body composed of three or more layers is a multilayer body of four or more layers, the lower layer of the second metal layer is an etching barrier layer, and the second metal layer is over-etched up to the etching barrier layer. The present invention also relates to a method for manufacturing the above semiconductor package substrate.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION The metal layer of the multilayer body used in the present invention to be an external connection terminal by etching is not particularly limited as long as it is a material having a conductive property that can be selectively etched with a material under the metal layer. Not done. For example, copper, nickel,
Examples thereof include gold, tin, lead, silver, titanium, alloys thereof and 42 alloy. The material of the bottom layer of the multilayer body is a material that is not etched when etching the above metal layer,
The material is not particularly limited as long as it can hold the member formed by etching. For example, for metal materials, copper, nickel, gold, tin, lead, silver, titanium, alloys and 42 alloys thereof, for organic materials, polyimide, epoxy resin, liquid crystal polymer, for inorganic materials, aluminum oxide,
Examples include silicon oxide, aluminum nitride, silicon nitride, and the like, and composites thereof. Alternatively, a substrate having an internal circuit may be used.

FIG. 1 is an explanatory view showing an embodiment of the method for manufacturing a semiconductor package substrate of the present invention. First, as a multilayer body of two or more layers having a first metal layer as an upper layer, for example, Cu (carrier layer: first metal layer 2) / Ni (barrier layer: second metal layer 3) / Cu (circuit) Layer: The resist layer 1 is formed by attaching a dry film to the first metal layer 2 of the three-layer metal foil consisting of the third metal layer 4) (a).
The resist layer other than the portion where the connection terminal is provided is removed by exposure and development, and the first resist 5 is provided on the portion of the first metal layer 2 where the external connection terminal is to be formed (b). Etching is performed so that the etching amount is about 10 to 20 μm (half etching;
(C)). The first resist 5 remaining at the places where the connection terminals are provided is peeled off (d). A resist layer such as a dry film is laminated on the entire surface of the first metal layer, and the resist layer 6 is brought into close contact with the upper surface and the side surface of the protruding portion formed by half etching (e). The second resist 7 is provided by removing the resist layer other than the place where the connection terminal is provided by exposure and development (f). The first metal layer 2 not provided with the second resist 7 is over-etched using alkali or the like. The etching stops at the second metal layer 3 (Ni layer) provided as the barrier layer, but since the side surface of the columnar portion where the connection terminal is provided is cut off and the root portion is cut off, the outside of the top diameter of the external connection terminal The bottom diameter of the connection terminal is smaller. (G). The second resist 7 is peeled off (h).

FIG. 2 is an explanatory view showing another embodiment of the method for manufacturing a semiconductor package substrate according to the present invention.
The steps (a), (b) and (c) are the same as above.
After the half etching in the step (c), the first resist 5 is heated and pressed to form a resist 7'on the upper surface and the side surface of the protruding portion of the first metal layer 2 generated by the half etching (f '). The first metal layer 2 not provided with the resist 7'is over-etched by using an alkali or the like.
The etching stops at the second metal layer 3 (Ni layer), but since the side surface of the columnar portion where the connection terminal is to be provided is carved and the root portion is shaved, the bottom diameter of the external connection terminal is smaller than the top diameter of the external connection terminal. It becomes smaller. (G '). The resist 7'is peeled off (h ').

FIG. 3 is an explanatory view showing another embodiment of the method for manufacturing a semiconductor package substrate of the present invention. First, as a multilayer body including three or more layers having two metal layers as an upper layer, for example, Ni (resist metal layer: first metal layer 12) / Cu (second metal layer 13) / Ni (barrier layer) : The resist layer 1 by attaching a dry film to the Ni layer (resist metal layer) 12 of the four-layer metal foil composed of the third metal layer 14) / Cu (the fourth metal layer 15 serving as the circuit layer)
1 is formed (a '). The resist layer 11 other than the portion where the connection terminal is provided is removed by exposure and development, and the first resist 16 is provided on the portion of the first metal layer 12 where the external connection terminal is to be formed (b '). First metal layer 1
2 is selectively etched (selective etching;
(C ')). The first resist 16 remaining at the places where the connection terminals are provided is peeled off to remove the first metal layer 12 from the metal resist 1.
7 (f ″). The second metal layer 13 not provided with the metal resist 17 is over-etched by selective etching using an alkaline etching solution or the like. The etching is performed with the third metal layer 14 (Ni layer). However, the bottom diameter of the external connection terminal is smaller than the top diameter of the external connection terminal (h ″) because the side surface of the columnar portion where the connection terminal is provided is scooped off and the root portion is ground. The board obtained as described above has a bottom diameter of the external connection terminal of 40 to 590.
μm, the top diameter is preferably 80 to 600 μm, and the bottom diameter is preferably 99 to 50% of the top diameter. The height of the external connection terminal is 25 to 150 μm.
Is preferred.

[0015]

EXAMPLES The present invention will now be described in detail based on examples, but the present invention is not limited thereto. Example 1 First, Cu (circuit layer) 8 μm / Ni (barrier layer) 0.2
3-layer foil (2 μm / Cu (carrier layer) 70 μm)
A dry film (Photec H-350, manufactured by Hitachi Chemical Co., Ltd.) was attached to a carrier layer of 50 mm × 250 mm (a). The dry film was removed by exposure and development using a negative mask, except for the portions where the connection terminals were provided, so that the locations where the connection terminals were provided were circular with a pitch of 0.5 mm and a diameter of 0.25 mm. The exposure machine used was EXM-1029 manufactured by Oak Manufacturing Co., Ltd., and the exposure amount was 90 mJ.
The developing machine used was a developing tank made by Yako Co., Ltd., which was composed of a developing tank of 1 m and three washing tanks. Developer is 1% sodium carbonate
An aqueous solution was used. Transport speed of development is 1.4m / mi
n. , Spray pressure 17.7 × 10 ⁴ Pa (1.8 kgf
/ Cm ² ) (b). Etching thickness is 10
The copper layer of the carrier layer was etched to have a thickness of about 20 μm. (Half etching; (c)) As an etching solution, an Aprocess bath solution manufactured by Meltex was used. Transport speed 1m / mi using alkaline etching equipment
n. , Spray pressure 17.7 × 10 ⁴ Pa (1.8 kgf
/ Cm ² ). The dry film remaining at the place where the connection terminal is provided was peeled off (d). The peeling operation was carried out by immersing it in a 2.5% aqueous solution of sodium hydroxide for 40 seconds in a batch tank of 50 L, washing it twice with water, and then drying. The dry film was laminated on the entire surface of the carrier layer, and the dry film was also brought into close contact with the side surfaces of the protrusions formed by half etching (e). The laminator is Hitachi AIC H
Using LM-A53, roll temperature 110 ° C, pressure 4.9.
× 10 ⁵ Pa (5 kgf / cm ² ), speed 1.8 m / mi
n. I went there. Using the above-mentioned exposure machine and developing machine, the dry film was removed by exposure / development except for the area where the connection terminals were provided (f). The copper layer of the carrier layer was etched with alkali until it reached the nickel layer of the barrier layer. (G). As the etching liquid, A-Process construction bath liquid made by Meltex is used, and as the etching device, a developing tank 1 m and a water washing 3 tank device made by San Techno Systems Co., Ltd. are used.
Transport speed 0.5 m / min. , Spray pressure 17.7
Performed under the condition of × 10 ⁴ Pa (1.8 kgf / cm ² ) and 1
It was etched for 20 seconds. The dry film was peeled off (h). Sodium hydroxide 2.
It was dipped in a 5% aqueous solution for 40 seconds. After that, wash with water twice,
Dried. The diameter of the top layer and the diameter of the bottom layer of the connection terminal of the completed board with connection terminals were 245 μm and 23, respectively.
It was 0 μm.

Example 2 First, Cu (circuit layer) 8 μm / Ni (barrier layer) 0.2
3-layer foil (2 μm / Cu (carrier layer) 70 μm)
A dry film (Photec H-350, manufactured by Hitachi Chemical Co., Ltd.) was attached to a carrier layer of 50 mm × 250 mm (a). The dry film was removed by exposure and development using a negative mask, except for the portions where the connection terminals were provided, so that the locations where the connection terminals were provided were circular with a pitch of 0.5 mm and a diameter of 0.25 mm. The exposure machine used was EXM-1029 manufactured by Oak Manufacturing Co., Ltd., and the exposure amount was set to 70 mJ, which is lower than usual, to improve the adhesion when the dry film is re-adhered by pressing. The developing machine used was a developing tank made by Yako Co., Ltd., which consists of a developing tank of 1 m and a washing tank of 3 tanks. A 1% aqueous solution of sodium carbonate was used as the developing solution. The transport speed of development is 2.0m / mi, which is close to the development speed.
n. , Spray pressure 17.7 × 10 ⁴ Pa (1.8 kgf
/ Cm ² ) and developed (b). The copper layer of the carrier layer was etched so that the etching thickness was about 10 to 20 μm. (Half etching; (c)) As an etching solution, an Aprocess bath solution manufactured by Meltex was used. Transport speed 1m / min. , Spray pressure 17.7 × 10 ⁴ Pa
It was performed under the condition of (1.8 kgf / cm ² ). With the dry film remaining, it was air-dried so as not to apply heat.
The dry film was worked by pressing with a vacuum press while heating it through a cushion so that the dry film was in close contact with the side surface of the etched copper layer (press pressure 9.8 × 10 ⁵ P
a (10 kgf / cm ² ), heating temperature 80 ° C., vacuum degree 3
0 mmHg, release film 0.04 mm thickness, cushion paper 1.0 mm thickness, heating and pressing time 10 minutes) (f ').
The copper layer of the carrier layer was etched with alkali until it reached the nickel layer of the barrier layer. (G '). Meltex A-process construction bath liquid was used as the etching liquid, and a developing tank 1 m manufactured by San Techno Systems Co., Ltd. was used as the etching device.
Transport speed of 0.5m / mi using a device with 3 washing tanks
n. , Spray pressure 17.7 × 10 ⁴ Pa (1.8 kgf
/ Cm ² ) and the etching was performed for 120 seconds. The dry film was peeled off (h '). It was immersed in a 2.5% aqueous solution of sodium hydroxide for 40 seconds using the above-mentioned stripping device. Then, it was washed twice with water and dried. The diameter of the top layer of the connection terminals of the finished board with connection terminals is 245 μm.
And the diameter of the bottom layer was 230 μm.

Example 3 First, Cu (circuit layer) 8 μm / Ni (barrier layer) 0.2
3-layer foil (2 μm / Cu (carrier layer) 70 μm)
A 50 mm × 250 mm) carrier layer was electrolytically plated with Ni to a thickness of 10 to 20 μm to obtain a four-layer foil. A dry film (Photec H-350, manufactured by Hitachi Chemical Co., Ltd.) was attached to the Ni layer (a). The dry film was removed by exposure and development using a negative mask, except for the portions where the connecting terminals were provided, so that the portions where the connecting terminals were provided were circular with a pitch of 0.5 mm and a diameter of 0.25 mm (b '). The Ni layer formed by plating until the copper of the carrier layer was exposed was selectively etched with a Ni etching liquid (Meltex N950 manufactured by Meltex) (c '). The dry film was peeled off, and the copper layer of the carrier layer was selectively etched until the nickel layer of the barrier layer was reached. (F ″,
h ″). The diameter of the top layer and the diameter of the bottom layer of the connection terminal of the completed substrate with connection terminals are 245 μm and 230, respectively.
was μm.

[0018]

According to the present invention, it is possible to reduce the pad diameter of the wiring layer, and it is possible to provide wiring of higher density.

[Brief description of drawings]

FIG. 1 is a process drawing showing an embodiment of the present invention.

FIG. 2 is a process drawing showing another embodiment of the present invention.

FIG. 3 is a process drawing showing another embodiment of the present invention.

[Explanation of symbols]

1 Resist layer 2 First metal layer 3 Second metal layer 4 Third metal layer 5 First resist 6 Resist layer 7 Second resist 7'resist 11 Resist layer 12 First metal layer 13 Second metal layer 14 Third metal layer 15 Fourth metal layer 16 First resist 17 Metal resist

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Mitsuo Kikuchi             No. 1380, Nishihara, Ashizaki, Hitachinaka City, Ibaraki Prefecture             Ground 1 Inside Hitachi Chemical Co., Ltd. Yamazaki Plant (72) Inventor Kazuhisa Suzuki             No. 1380, Nishihara, Ashizaki, Hitachinaka City, Ibaraki Prefecture             Ground 1 Inside Hitachi Chemical Co., Ltd. Yamazaki Plant

Claims (6)

[Claims] 1. A semiconductor package substrate having a plurality of columnar external connection terminals on a surface thereof, wherein a bottom diameter of the external connection terminals is smaller than a top diameter of the external connection terminals. . 2. A step of providing a first resist at a location where an external connection terminal of a first metal layer of a multilayer body composed of two or more layers having a first metal layer as an upper layer is formed, Half-etching the metal layer, peeling the first resist, providing a second resist on the upper and side surfaces of the protrusion of the first metal layer generated by the half-etching, and providing the second resist. A method of manufacturing a semiconductor package substrate, comprising the step of over-etching the first metal layer which is not formed. 3. A step of providing a resist at a position where an external connection terminal of the first metal layer of a multilayer body composed of two or more layers having a first metal layer as an upper layer is formed, the first metal layer. The step of half-etching the resist, the step of heating and pressing the resist to provide the resist on the upper surface and the side surface of the protruding portion of the first metal layer generated by the half-etching, and the first metal layer not provided with the resist being over-etched. A method for manufacturing a semiconductor package substrate, comprising the steps of: 4. The multi-layered body comprising two or more layers is a multi-layered body having three or more layers, the lower layer of the first metal layer is used as an etching barrier layer, and the first metal layer is over-etched up to the etching barrier layer. Alternatively, the method for manufacturing a semiconductor package substrate according to the above item 3. 5. The external connection terminal of the first metal layer of a multi-layer body having three or more layers having the first metal layer and the two metal layers of the second metal layer on the upper layer is to be formed. A step of providing a resist, a step of etching the first metal layer to provide a metal resist, and a step of overetching the second metal layer of the metal resist on which no resist is provided by selective etching. Of manufacturing a semiconductor package substrate. 6. The multi-layered body composed of three or more layers is a multi-layered body of four or more layers, the lower layer of the second metal layer is an etching barrier layer, and the second metal layer is over-etched up to the etching barrier layer. A method for manufacturing a semiconductor package substrate as described above.