JP2003273253A - Randomly programmable non-volatile semiconductor memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a randomly programmable non-volatile semiconductor memory wherein its power saving is made possible largely, and its access time is shortened, and further, its function is improved. <P>SOLUTION: The randomly programmable non-volatile semiconductor memory comprises a first conduction type semiconductor base 32, a second conduction type deep ion well 34, a first conduction type shallow ion well 36, one or more NAND memory-cell blocks B1, B2, and a bit line BL1. The first conduction type shallow ion well is so isolated from others by insulation layers as to be formed in the second conduction type deep ion well. The NAND memory-cell blocks are formed in the first conduction type shallow ion well. The bit line is so formed above the semiconductor base as to be connected electrically with plugs 40 extending to the first conduction type shallow ion well. In a programming mode, a first predetermined voltage is applied to the first conduction type shallow ion well, and in an erasing mode, a second predetermined voltage is applied thereto. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a kind of non-volatile semiconductor memory, and more particularly to a NAND type non-volatile semiconductor memory capable of random programming.

[0002]

2. Description of the Related Art Among storage media called so-called flash memory, an electrically erasable programmable read only memory (hereinafter referred to as EEPROM) is a non-volatile memory having advantages such as high density. It is widely used because it can be written.

The manufacturing process of a flash memory is mainly NO.
It can be divided into R type and NAND type. The former is a code flash whose main purpose is program conversion, and the latter is a data flash whose main purpose is data storage. Code flash can convert and read programs at high speed, and is therefore applied to, for example, mobile phones. Since the data flash has high density, it is applied to, for example, a digital camera or a memory card of a home electric appliance having a data storage function. Also, flash EEPROMs come in several different formats. One of them is EEPPOM using an opposite channel.

FIG. 1 shows a conventional NAND type EEPROM.
The cross-sectional structure of is disclosed. According to the figure, NAND type E
EPROM 10 is a semiconductor base 1 having a memory area.
2, a semiconductor well 14 provided in the semiconductor base 12 located in the memory region, and a plurality of NANDs formed on the semiconductor well 14 provided in the semiconductor base 12.
The memory cell block B includes a memory cell block B and a bit line BL1 provided on the semiconductor base 12. The memory cell block B includes a plurality of memory cells M that can be written in duplicate. The memory cell M includes the bit line BL1.
And are electrically connected in series with each other. Further, the memory cell M below the bit line BL1 shares the doping region formed thereunder as a source and a drain to form a NAND type memory cell. For example, the memory cell M114 has the doping region 16 as a source and the doping region 18 as a drain. However, the doping region 18 simultaneously serves as the source of the memory cell M115. The memory cell M further has a stack structure gate.
Equipped with For example, in the memory cell M14, the upper layer is the control gate 20 and the lower layer is the floating gate 22 for storing charges, and the insulating layer 24 is formed between the control gate 20 and the floating gate 22 to separate them.

One end of the memory cells M connected in series has a plug 2
It is electrically connected to the bit line BL1 by 6 and is electrically connected to the source line SL by providing a selecting transistor ST at the other end. Further, the control gate of the memory cell M is the bit line BL1.
Is electrically connected to a word line (not shown) orthogonal to. With this structure, all the serially connected memory cells activated by the same bit line are defined as a NAND cell block.

The above-described NAND-type EEPROM 10 according to the conventional technique can activate a memory cell only when a high voltage (for example, 20 V) is applied to a selected word line in a programming execution mode. In addition, the word lines that are not selected have a certain high voltage (for example, 12V) to form a channel.
Need. Therefore, conventional NAND type EPROM
Not only is 10 very draining of electricity, but the speed must be significantly reduced since all the word lines must be applied with voltage. Further, due to the presence of the high voltage, there is a possibility that breakdown or the like may occur at the joint surface, and the reliability thereof is not high at all.

[0007]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a non-volatile semiconductor memory capable of random programming, which enables significant power saving, shortens access time, and enhances functions.

[0008]

Therefore, the present inventor has conducted intensive studies in view of the structure of a conventional NAND type EEPROM and its drawbacks, and as a result, a first conductive type semiconductor base having a memory region and the memory. A second conductivity type ion deep well formed in the semiconductor base in the region;
A first conductivity type ion shallow well (Sh that is formed in the ion deep well and is isolated by an insulating layer)
allow well), at least one or more NAND cell blocks provided on the semiconductor base in the shallow ion well, and a plug provided above the semiconductor base and extending to the ion shallow well. The present invention has been completed based on such knowledge, focusing on the fact that the problem can be solved by a structure including a bit line that supplies a predetermined voltage to a well.

That is, when the programming mode is executed, the first predetermined voltage is applied to the Shallion well,
In the erase mode, a second predetermined voltage is applied to the Charo ion well. Since the shallow ion well is formed in the deep ion well and a plug extending to the shallow ion well is inserted to form a common electrode, it is necessary to apply a voltage to all word lines as in the conventional technique. There is no. That is, in the structure of the present invention, when programming is performed on the non-volatile semiconductor memory, it is only necessary to apply a voltage of an appropriate level to the selected word line. It is possible to obtain a non-volatile semiconductor memory having an improved function, which enables the significant power saving and the shortening of access time, which are the subjects of the present invention.

A non-volatile semiconductor memory capable of random programming according to claim 1 has at least a semiconductor base of a first conductivity type, a deep ion well of a second conductivity type, and a shallow ion well of a first conductivity type. A non-volatile semiconductor memory comprising one or more NAND memory cell blocks and a bit line and capable of performing random programming, wherein the first conductive type semiconductor base comprises a memory region and the second conductive type. Type deep ion wells are formed in the semiconductor base in the memory region, and the first conductive type shallow ion wells are formed in the second conductive type deep ion wells by being isolated by an insulating layer. The cell block is located on the semiconductor base in the first conductivity type Charo-ion well. Made is, the bit line is formed on the semiconductor base information, and electrically connected to the plug which extends up to the shallow ion well of first conductivity type,
A first predetermined voltage is applied to the first conductivity type shallow ion well in the programming mode, and a second predetermined voltage is applied to the first conductivity type shallow ion well in the erase mode.

In the nonvolatile programmable nonvolatile semiconductor memory according to a second aspect, the well depth of the Shallion ion well according to the first aspect is shallower than the thickness of the insulating layer.

A random programmable nonvolatile semiconductor memory according to a third aspect is the nonvolatile semiconductor memory according to the second aspect, wherein the first conductivity type is p.
The second conductivity type is n-type.

According to another aspect of the nonvolatile programmable nonvolatile semiconductor memory of the present invention, in the NAND memory cell block of the third aspect, a plurality of memory cells capable of overlapping writing are connected in series, and the series-connected memories are connected. Providing a selecting transistor at one end of the cell,
The other end is electrically connected to the plug.

In the nonvolatile programmable nonvolatile semiconductor memory according to claim 5, the selecting transistor according to claim 4 is electrically connected to the source line.

According to a sixth aspect of the non-volatile semiconductor memory capable of random programming, the memory cell according to the fifth aspect includes a stack structure gate.

In the non-volatile semiconductor memory capable of random access described in claim 7, the memory cell in claim 6 is a SONOS memory cell.

A nonvolatile semiconductor memory capable of random access according to claim 8 is a semiconductor base, a shallow ion well, a deep ion well, and a plurality of NANs.
An electrically erasable programmable read only memory (EEPROM) comprising a D memory cell block and at least one bit line, wherein the semiconductor base comprises a memory region and the shallow ion well comprises the memory region. A deep ion well is provided in the memory region below the shallow ion well, and the plurality of NAND memory cell blocks are formed on the semiconductor base in the shallow ion well. The bit line is electrically connected to a plug provided above the semiconductor base and extending to the shallow ion well, and is electrically connected to the shallow ion well through the plug.

According to a ninth aspect of the present invention, there is provided the electrically erasable programmable read-only memory, wherein the depth of the shallow ion well in the eighth aspect is smaller than the thickness of the insulating layer.

The electrically erasable programmable read-only memory according to claim 10 is the electrically erasable programmable read-only memory according to claim 9, and when the programming mode is executed, the bit line to the shallow A first predetermined voltage is applied to the ion well, and a second predetermined voltage is applied from the bit line to the shallow ion well in the erase mode.

In the electrically erasable programmable read-only memory according to the eleventh aspect, the programming mode according to the tenth aspect is performed by utilizing the Fowler-Nordheim tunnel phenomenon.

According to a twelfth aspect of the present invention, in the electrically erasable programmable read-only memory, the first predetermined voltage in the eleventh aspect is 5V, and the second predetermined voltage is
It is -10V.

According to a thirteenth aspect of the present invention, there is provided an electrically erasable read-only memory in which the NAND memory cell block according to the twelfth aspect includes a plurality of redundant writable memory cells and a selecting transistor. The cells are connected to each other in series, and the selecting transistor is provided at one end.

In the electrically erasable programmable read only memory according to claim 14, the selecting transistor according to claim 13 is electrically connected to the source line.

According to a fifteenth aspect of the present invention, in the electrically erasable programmable read only memory, the memory cell according to the fourteenth aspect comprises a stack structure gate.

In the electrically erasable programmable read-only memory according to claim 16, the memory cell according to claim 15 is a SONOS memory cell.

[0026]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention relates to a NAND type non-volatile semiconductor memory capable of random programming, including a first conductive type semiconductor base, a second conductive type deep ion well, and a first conductive type shallow. It includes an ion well, at least one NAND memory cell block, and a bit line.

Specific examples will be given in order to describe the structure and characteristics of the nonvolatile semiconductor memory in detail, and will be described below with reference to the drawings.

[0028]

1 is a circuit diagram of a NAND type nonvolatile semiconductor memory 30 according to the present invention. According to the figure, N
The AND memory cell block E includes a plurality of memory cells M that can be written in duplicate, and a plurality of memory cells M
Are connected to each other in a serial manner along the direction of the bit line BL1. Further, one end of the plurality of memory cells M connected in series is electrically connected to the bit line BL1 and the other end is connected to the source line SL by providing a selecting transistor ST.

FIG. 3 discloses the layout of the NAND type nonvolatile semiconductor memory 30 according to the present invention, and FIG. 4 shows the NAND type nonvolatile semiconductor memory 3 in FIG.
A cross-sectional view along the zero bit line BL1 is disclosed. According to the drawing, the NAND type semiconductor memory 30 includes a first conductive type semiconductor base 32 having a memory region and a second conductive type semiconductor base 32 formed in the memory region.
A conductive type deep ion well 34, a first conductive type shallow ion well 36 formed in the deep ion well by being isolated from the deep ion well by an insulating layer 38, and formed on the semiconductor base 32 in the shallow ion well 36. In the programming mode, the first predetermined voltage is applied to the shallow ion well 36 to erase the NAND memory cell block B and the plug 40 provided above the semiconductor base 32 and extending to the shallow ion well 36. A second predetermined voltage is applied to the Charo ion well 36 in the mode.

In the preferred embodiment of the present invention, the semiconductor base 32 is a p-type semiconductor base and the deep ion well 34 is an n-type conductivity type. Further, the Charo ion well 36 is a pe type conductivity type. Of course, in the present invention, the semiconductor base 32 may be an n-type conductivity type. In this case, the deep ion well 34 is of p-type conductivity type and the shallow ion well 36 is of n-type conductivity type.

Further, the depth of the shallow ion well 36 is shallower than the thickness of the insulating layer 38. In the embodiment according to the present invention, the thickness of the insulating layer 38 is about 3000 to Å4000Å.
And At the same time, the doping dose of the deep ion well is about 1E12 to 1E113 atoms / m ² , and the doping dose of the shallow ion well is about 1E13.
˜1E14 atoms / m ² .

The NAND memory cell block B comprises a plurality of memory cells M which can be written in a redundant manner, and the plurality of memory cells M are connected in series along the direction of the bit line BL. Adjacent memory cells M below the same bit line BL share a doping region thereunder to form a NAND type memory cell as a source and a drain. For example, the memory cell M14 uses the doping region 42 as a source and the doping region 44 as a drain. However, the doping region 44 is simultaneously formed in the memory cell M11.
It is also the source of 5.

In the preferred embodiment of the present invention, memory cell M comprises a stacked gate. For example, a control gate 46 is formed on the upper layer of the memory cell M114 with polysilicon, and a lower layer is a floating gate 48 for storing electric charges, and an insulating film 50 is an ONO insulating film 50 for isolating the control gate 46 and the floating gate 48 from each other. (Oxide-nitride-oxid
e) It may be a film. However, the gate structure in the present invention may be a SONOS structure gate. That is, the control gate 46 is formed by directly setting the ONO layer on the shallow ion well 36 by sedimentation and further forming the polysilicon layer by sedimentation. The control gates of the plurality of memory cells M provided below the bit line BL are
Each is electrically connected to the corresponding word line WL. Therefore, all serial memory cells activated by one bit line are defined as a NAND memory cell block.

One ends of the plurality of memory cells connected in series are electrically connected to the bit line BL via the plug 40.
A contact hole is formed by etching in order to extend the plug 40 to the shallow ion well 36. That is, the surface of the shallow ion well 36 is etched, and further vertically vertically etched from the doping region serving as the drain of the memory cell M to the inside of the shallow ion well 36.

As shown in FIG. 5, the source line SL is formed in the form of the buried doping region SL1 disclosed in the non-volatile semiconductor memory 30, and the plug 52 and the doping region 54 are formed using metal leads. Connecting.

FIG. 6 discloses operating conditions of a non-volatile semiconductor memory having a stack structure gate. A description will be given based on the disclosure of FIG. 6 and taking the nonvolatile semiconductor memory 30 as an example. When executing the programming mode for the nonvolatile semiconductor memory 30, 5V is applied to the bit line BL.
Voltage is applied. The bit line BL is electrically connected to the Shaloion well 36 through a plug 40 extending to the Shaloion well 36. Therefore, the bit line BL can supply a voltage of 5V to the shallow ion well 36. For this reason, Charoion Well 3
6 is a common electrode. Therefore, when programming is performed by selecting one memory cell M, it suffices to apply a voltage of an appropriate height to the selected word line WL, and it is not necessary to apply it to all word lines WL, and the Fowler-Nordheim tunnel current Use the phenomenon to move electrons,
Can write. In the embodiment of the present invention, the voltage applied to the selected word line WL is about −
At 10V, the source line is floating, and the gates of the selecting transistors ST are all 0V.

When the erase mode of the non-volatile semiconductor memory 30 is executed, a voltage of -10V is applied to the source line SL. In erase mode, all memory cells M
Since all the word lines WL are erased collectively, a voltage of 10V is applied to all the word lines WL. In this case, similarly, the bit line BL becomes floating, all the selecting transistors ST are 0 V, and similarly, erasing is performed by using the Fowler-Nordheim tunnel current phenomenon. That is, the nonvolatile semiconductor memory 30
Operates by utilizing the Fowler-Nordheim tunnel current phenomenon in both directions.

When the read mode of the non-volatile semiconductor memory 30 is performed, the voltage of the bit line is set to 0V, a current of 5V is applied to the gate of the selected selecting transistor ST, and the unselected selecting transistor STx is applied. The gate maintains 0V. At the same time, a voltage of 5V is applied to the unselected word lines WLx, the selected word lines WL are set to 0V, and reading is performed. Moreover, a voltage of 1 to 5 V is applied to the source line SL.

The non-volatile semiconductor memory according to the present invention may be composed of SONOS memory cells other than the above-mentioned stack structure gate. The operating conditions of a non-volatile storage medium comprising SONOS memory cells are disclosed in FIG. According to the drawing, in programming and erasing modes, S
The voltage required for a non-volatile semiconductor memory including ONOS memory cells is lower than that for a stacked structure gate. That is, the nonvolatile semiconductor memory including the SONOS memory cells is not only simple in manufacturing process,
At the same time, it also saves electricity.

The above is a preferred embodiment of the present invention and does not limit the scope of the present invention. Therefore, any changes or modifications that can be made by those skilled in the art that are made within the spirit of the present invention and have an equivalent effect on the present invention are all included in the scope of the claims of the present invention. To do.

[0041]

The nonvolatile semiconductor memory according to the present invention is
A shallow ion well is formed in the deep ion well, and a plug connected to the bit line is inserted in the shallow ion well to form a common electrode. Such a structure can ameliorate the drawback of applying a voltage to all bit lines in the conventional technique. Further, the structure of the non-volatile semiconductor memory according to the present invention can remedy the drawbacks of the prior art that require a high voltage drive voltage. In other words, the structure according to the present invention only needs to apply an appropriate voltage voltage to the selected word line when executing the programming mode for the non-volatile semiconductor memory. Therefore,
It not only saves a great deal of power, but also shortens access time and enhances memory functions.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing the structure of a conventional NAND type EEPROM.

FIG. 2 is an explanatory diagram of an electric circuit having an effect equivalent to that of the NAND type nonvolatile semiconductor memory according to the present invention.

FIG. 3 is an explanatory diagram showing a layout of a NAND type nonvolatile semiconductor memory according to the present invention.

FIG. 4 is a sectional view taken along a bit line of the NAND type nonvolatile semiconductor memory disclosed in FIG. 3;

FIG. 5 is a cross-sectional view showing a structure of a second embodiment of a NAND type nonvolatile semiconductor memory according to the present invention.

FIG. 6 is an operating condition table of a nonvolatile semiconductor memory having a stack structure gate according to the present invention.

FIG. 7 is an operating condition table of a nonvolatile semiconductor memory including SONOS memory cells according to the present invention.

[Explanation of symbols]

32 semiconductor base 42, 44, 54 doping regions 46 control gate 48 floating gates 38 Insulation layer 40, 52 plug 30 NAND type non-volatile semiconductor memory 34 Deep Ion Well 36 Charionon Well 50 insulating film B memory cell block BL, BL1 Bit line M, M14, M114, M115 memory cells SL source line ST selecting transistor

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[Procedure amendment]

[Submission date] July 18, 2002 (2002.7.1)
8)

[Procedure Amendment 1]

[Document name to be corrected] Drawing

[Name of item to be corrected] Fig. 4

[Correction method] Change

[Correction content]

[Figure 4]

[Procedure Amendment 2]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 5

[Correction method] Change

[Correction content]

[Figure 5]

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Claims (16)

[Claims] 1. A semiconductor base of the first conductivity type and a second base.
Conductive type deep ion well, first conductive type shallow ion well, and at least one or more NAND
Comprising a memory cell block and a bit line,
A non-volatile semiconductor memory capable of performing random programming, wherein the first conductive type semiconductor base comprises a memory region, and the second conductive type deep ion well is formed in the semiconductor base in the memory region. The first conductive type shallow ion well is separated by an insulating layer and formed in a second conductive type deep ion well, and the NAND memory cell block is formed on a semiconductor base in the first conductive type shallow ion well. The bit line is formed above the semiconductor base, and is electrically connected to a plug extending to the shallow ion well of the first conductivity type, and the first conductivity type is used when performing a programming mode. A first predetermined voltage is applied to the Charo ion well of the Nonvolatile semiconductor memory capable of random programming and applying a second predetermined voltage to the shallow ion wells. 2. The random programmable nonvolatile semiconductor memory according to claim 1, wherein a depth of the shallow ion well is shallower than a thickness of the insulating layer. 3. In the non-volatile semiconductor memory, the first conductivity type is p-type and the second conductivity type is n-type.
The non-volatile semiconductor memory capable of random programming according to claim 1, wherein the nonvolatile semiconductor memory is of a type. 4. The NAND memory cell block has a plurality of writable memory cells connected in series,
In addition, a non-volatile semiconductor memory capable of random programming, wherein a selecting transistor is provided at one end of the series-connected memory cells and the other end is electrically connected to a plug. 5. The selecting transistor is electrically connected to a source line.
A non-volatile semiconductor memory capable of random programming according to [1]. 6. The random programmable nonvolatile semiconductor memory according to claim 4, wherein the memory cell includes a stack structure gate. 7. The randomly accessible nonvolatile semiconductor memory according to claim 4, wherein the memory cell is a SONOS memory cell. 8. An electrically erasable programmable read only memory (EEPROM) comprising a semiconductor base, a shallow ion well, a deep ion well, a plurality of NAND memory cell blocks, and at least one or more bit lines. Wherein the semiconductor base comprises a memory region, the shallow ion well is formed in the memory region with an insulating layer, and the deep ion well is provided below the shallow ion well in the memory region. The plurality of NAND memory cell blocks are formed on the semiconductor base in the shallow ion well, and the bit line is electrically connected to a plug provided above the semiconductor base and extending to the shallow ion well, Characterized in that it is electrically connected to the Shallion ion well through the plug. Electrically erasable programmable read-only memory that. 9. An electrically erasable programmable read-only memory, wherein the well depth of the shallow ion well is smaller than the thickness of the insulating layer. 10. The electrically erasable programmable read-only memory applies a first predetermined voltage from the bit line to the shallow ion well in a programming mode, and applies a first predetermined voltage from the bit line to the shallow ion well in an erase mode. 9. The electrically erasable programmable read-only memory according to claim 8, wherein a predetermined voltage of 2 is applied. 11. The electrically erasable programmable read only memory according to claim 8, wherein the programming mode is performed by utilizing a Fowler-Nordheim tunnel current phenomenon. 12. The first predetermined voltage is 5V,
11. The electrically erasable programmable read only memory according to claim 10, wherein the second predetermined voltage is -10V. 13. The NAND memory cell block includes a plurality of redundant writable memory cells and a selecting transistor, the plurality of memory cells are connected to each other in series, and the selecting transistor is provided at one end. The electrically erasable read-only memory according to claim 8, wherein the electrically erasable read-only memory is provided. 14. The electrically erasable programmable read-only memory of claim 13, wherein the selecting transistor is electrically connected to a source line. 15. The electrically erasable programmable read-only memory of claim 13, wherein the memory cell includes a stack structure gate. 16. The electrically erasable programmable read only memory according to claim 13, wherein the memory cell is a SONOS memory cell.