JP2003273118A - Hetero-junction bipolar transistor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce a driving voltage of an HBT, the parasitic resistance of each layer, and electrode contact resistance in processing a device by using GaAs for a substrate. <P>SOLUTION: A hetero-junction bipolar transistor has a laminated structure comprising an InGaAs sub-collector layer 2, an InGaAs collector layer 3, an InGaAs base layer 4, an InGaP emitter layer 5, an InGaAs emitter contact layer 6, and InGaAs non-alloy contact layers 7, 8 arranged in this order from the substrate side. GaAs is used for the substrate and a buffer layer 1, e.g. in the form of an InGaAs gradient composition layer, is provided between the GaAs substrate and the sub-collector layer 2 to alleviates lattice mismatching between them. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention provides a sub-collector layer, a collector layer, a base layer, an emitter layer, an emitter contact layer and a non-alloy layer on a semi-insulating compound semiconductor substrate with a III-V group compound semiconductor crystal. The present invention relates to a heterojunction bipolar transistor (HBT), and more particularly to a low voltage drive HBT using a GaAs substrate as a substrate.

[0002]

2. Description of the Related Art A heterojunction bipolar transistor (HBT) using a heterojunction as an emitter-base junction is
Since the bandgap of the emitter layer is wider than the bandgap of the base layer, the emitter injection efficiency can be increased, and thus the device is used as an ultrahigh-speed, high-power device.

An HBT which is composed of a III-V group compound semiconductor and uses a wide band gap semiconductor for the emitter is
AlGaAs / G using AlGaAs as an emitter
The aAs-based HBT is common. Further, by using InGaP having a larger band cap for the emitter, InGaP / GaAs-based H having characteristics such as reduction of oxygen impurities and leak current from the base to the emitter.
BT is also being developed. In addition, InP / InGaAs HBTs have also been developed. This is I
This is because the high mobility of electrons in the nGaAs layer makes it suitable for high-speed operation.

[0004]

In any of the HBTs, it has been attempted so far to improve the reliability of the device by focusing on the emitter layer and the base layer and improving the crystallinity and the interface between them. It has been tried.

However, under the following consideration,
It is considered that a better heterojunction bipolar transistor can be obtained by forming epitaxial layers having different lattice constants on the substrate.

First, considering the base material, I
Since nGaAs has a narrower band cap than GaAs, if the base layer is made of InGaAs, the turn-on voltage required to operate the HBT can be reduced, and it is promising for the development of a low-power HBT. Is.

Further, if InGaAs is used for the sub-collector, it is possible to reduce the contact with the collector electrode when manufacturing the device, which is advantageous for the device process.

Considering the substrate material for growing the InGaAs subcollector layer, In _0.53 GA _0.47 As having an In composition ratio of 0.53 is lattice-matched with InP. Therefore, In _0.53 GA _0.47 on the InP substrate
If As is grown, an HBT structure can be created without causing an increase in surface roughness due to lattice mismatch.

However, the InP substrate is expensive and easily damaged.

Therefore, an object of the present invention is to solve the above-mentioned problems and to provide a general Ga as a substrate for III-V group compound semiconductors.
(EN) A heterojunction bipolar transistor that uses an As substrate and realizes reduction of driving voltage for HBT operation, parasitic resistance of each layer, and electrode contact resistance during device process.

The present invention is a low voltage drive HBT using a general GaAs substrate as a substrate of a III-V group compound semiconductor.
As an In / emitter junction on the GaAs substrate
In composed of a GaP / InGaAs heterojunction
Provided is a technique for producing a GaP / InGaAs-based HBT, and in particular, a technique for reducing surface roughness due to lattice mismatch in a lattice mismatch system of GaAs and InGaAs. The HBT of the present invention has an InGaAs base layer, so that the turn-on voltage can be reduced, that is, a low-power drive HBT. Further, the HBT of the present invention has a high electron mobility in the InGaAs layer, and thus is suitable for high-speed operation. Further, by having the InGaAs subcollector layer, the contact resistance with the electrode during device fabrication can be reduced. it can.

[0012]

In order to achieve the above object, the present invention is configured as follows.

The heterojunction bipolar transistor according to the first aspect of the present invention comprises a subcollector layer,
In a heterojunction bipolar transistor made of a compound semiconductor having a laminated structure in which a collector layer, a base layer, an emitter layer, an emitter contact layer, and a non-alloy contact layer are formed, a lattice between the substrate and the subcollector layer is provided. A feature is that a buffer layer is provided to alleviate the mismatch.

Here, as a form of forming the buffer layer on the substrate, a form of a composition gradient layer (FIG. 2) is used.
(See (c)).

According to a second aspect of the present invention, in the heterojunction bipolar transistor according to the first aspect, a composition graded layer is used as the buffer layer. This corresponds to the form shown in FIG.

According to a third aspect of the present invention, in the heterojunction bipolar transistor according to the first or second aspect, the substrate is made of GaAs, and the buffer layer, the subcollector layer, the collector layer, the base layer, and the emitter. The contact layer is made of InGaAs, and the emitter layer is made of an InGaP layer.

In a heterojunction bipolar transistor according to a fourth aspect of the present invention, InGaAs is used as a buffer layer on a GaAs substrate to gradually increase the In composition ratio from 0 to a predetermined value (for example, 0.15) to form a GaAs crystal. I above
An InGaAs graded layer (composition gradient layer) grown to a thickness equal to or greater than the critical thickness capable of maintaining a pseudo-matching state of the nGaAs crystal is formed, and InGaA is formed on the buffer layer.
s subcollector layer, InGaAs collector layer, InGa
It is characterized in that an As base layer, an InGaP emitter layer, an InGaAs emitter contact layer, and an InGaAs non-alloy contact layer are sequentially formed.

The invention of claim 5 is the heterojunction bipolar transistor according to any one of claims 3 to 5, wherein the In composition ratio of the InGaAs layer is 0.2 or less.

According to a sixth aspect of the present invention, in the heterojunction bipolar transistor according to any one of the first to sixth aspects, the buffer layer, the subcollector layer, the collector layer, the base layer, the emitter layer, the emitter. The contact layer and the non-alloy contact layer are formed by a metal organic chemical vapor deposition method.

<Points of the Invention> In the present invention, in order to realize an HBT driven at a low voltage, an HBT using InGaAs having a narrow band cap as compared with GaAs is prepared. Further, in order to reduce the emitter resistance and the contact resistance of the collector electrode during the device process, the emitter contact, collector, and subcollector are made of InGaAs.

Since a general GaAs substrate and InGaAs have a lattice mismatch system, the above-mentioned low voltage driven HBT is
Lattice-mismatched heteroepitaxy technology is used for fabrication on aAs substrates. In the lattice-mismatched heteroepitaxy, the growth occurs so that the substrate and the lattice constant in the growth plane match each other, so that the growth occurs in a strained state in the growth plane. For this reason, the growth layer includes many dislocations, and the growth surface is deformed from smooth to island-like, which results in three-dimensional growth in which strain is alleviated. The inclusion of high-density dislocations in each epitaxial layer of the HBT structure and the low smoothness of the interface between the layers are factors that hinder the achievement of high-performance HBT characteristics.

Therefore, the occurrence of the above-mentioned transition or 3
Designing the buffer layer so that dimensional growth is suppressed is a key point of lattice mismatch heteroepitaxy.

The present invention provides a metamorphic layer as the buffer layer.

[0024]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to examples.

<Embodiment> FIG. 1 is a schematic diagram of GaA according to the present invention.
InGaP / InGaAs system H constructed by using s substrate
FIG. 1 is a cross-sectional view showing a schematic configuration of BT, and Table 1 shows this FIG.
3 shows the structure of each layer on the GaAs substrate of the HBT shown in FIG.

[0026]

[Table 1]

That is, in the case of the HBT of the present embodiment, FIG.
1 is un-InGaA formed on the GaAs substrate
s buffer layer, 2 is an n-InGaAs subcollector layer,
3 is an n-InGaAs collector layer, 4 is p-InGaA
s base layer, 5 n-In _{0. 58} Ga _0.42 P emitter layer,
Reference numeral 6 is an n-InGaAs emitter contact layer, and 7 and 8 are n-InGaAs non-alloy contact layers. In the table, n− in the name of the epitaxial layer represents that the epitaxial layer is n-type, similarly p− represents p-type, and un− represents undoped.

As shown in Table 1, the In _x Ga _1-x As layers of the sub-collector layer 2, the collector layer 3, the base layer 4 and the emitter contact layer 6 are made of In considering the lattice mismatch with the GaAs substrate. In _0.15 G with a composition ratio x of 0.15
a _0.85 As. The In _x Ga _1-x As layer of the buffer layer 1 has an In composition ratio x of 0 to 0.1 over 50 nm.
An In _{(0 → 0.15)} GaAs composition graded layer gradually changing to 5 was used.

Further, the InGaP emitter layer 5 is made of In _x G
The a _1-x P layer is formed by setting various flow rate ratios of trimethylindium (TMI) that is a raw material of In and trimethylgallium (TMG) that is a raw material of Ga during growth.
Growth was attempted on n _0.15 Ga _0.85 As, and the flow rate ratio that was lattice-matched with the underlying In _0.15 Ga _0.85 As was determined by X-ray diffraction reflection measurement. In _x Ga _1-x P grown under these conditions
Is In _0.58 Ga _0.42 P having an In composition ratio x of 0.58
Is.

Table 2 is a comparative example, and general InGa
GaAs when configured as a P / GaAs HBT
3 shows a configuration of each layer on a substrate. General InG
In the case of aP / GaAs HBT, 1 is GaAs in FIG.
Buffer layer, 2 is GaAs subcollector layer, 3 is GaA
s collector layer, 4 is a GaAs base layer, 5 is InGaP
Emitter layer, 6 is a GaAs emitter contact layer, 7,
Reference numeral 8 indicates an InGaAs non-alloy contact layer.

[0031]

[Table 2]

The difference from the present invention is that in the comparative example (Table 2), GaAs is used for the subcollector layer 2, the collector layer 3, the base layer 4, and the emitter contact layer 6, respectively. On the other hand, in the present invention (Table 1), In _0.15 Ga _0.85 As is used for the sub-collector layer 2, the collector layer 3, the base layer 4, and the emitter contact layer 6, respectively.

FIG. 3 is a current-voltage characteristic called a Gummel plot showing the basic characteristics of the HBT. And are compared and shown. InGaP / InGa of the present invention
As-based HBT is a general InGaP / GaAs-based HBT
It can be seen that current amplification is obtained from a lower voltage than that of.

FIG. 4 shows the In composition ratio dependency of the ideal factor of the HBT characteristic called n value. n value is shown in Figure 3.
Is the slope of the Gummel plot of and takes a value of 1 or more.
In the case of an ideal crystal, n value = 1 is defined. According to FIG. 4, the n value significantly increases when the In composition ratio is 0.2 or more. From this result, InGaP / Ga of the present invention
The In composition ratio of As-based HBT was 0.2 or less.

The HBT of this embodiment described above uses a general GaAs substrate as the substrate of the III-V group compound semiconductor, so that it is less expensive than the InP substrate and less susceptible to damage.

Although a lattice mismatch system of GaAs and InGaAs, a buffer layer 1 of In is formed on a GaAs substrate.
GaAs has an In composition ratio of 0 to a predetermined value (here, 0.1).
5) until the InGa on the GaAs crystal is gradually increased.
Since the InGaAs graded layer (composition gradient layer) grown to a thickness equal to or greater than the critical film thickness capable of maintaining the pseudo-matching state of the As crystal is formed, surface roughness due to lattice mismatch can be reduced. That is, according to this embodiment, InGaP / InGaAs using a GaAs substrate is used.
A system HBT can be realized.

In the HBT of this embodiment, the base material is Ga
Since the base layer is made of InGaAs having a band cap narrower than that of As, the turn-on voltage of the HBT becomes small. Therefore, it is possible to obtain an HBT driven by low power.

The HBT of this embodiment is InGaAs.
Since the mobility of electrons in the layer is high, it is suitable for high-speed operation. Moreover, since the subcollector layer is made of InGaAs, the contact resistance with the electrode at the time of making the device can be reduced, which is advantageous for the device process Is.

Further, according to this embodiment, the sub-collector layer, the collector layer, the base layer and the emitter contact layer are
By using InGaAs layers each having an In composition ratio of 0.2 or less, for example, In _0.15 Ga _0.85 As, it is possible to realize reduction of driving voltage for HBT operation, parasitic resistance of each layer, and electrode contact resistance during device processing.

In the above embodiment, In _0.15 is formed on the GaAs substrate.
In order to grow Ga _0.85 As, In is grown on the GaAs substrate.
_{(0 → 0.15)} GaAs composition gradient layer was formed,
The buffer layer formed on the substrate may have some forms other than the composition gradient layer described in the above embodiment.

FIGS. 2A, 2B and 2C are examples of the buffer layer formed on the GaAs substrate for growing In _0.15 Ga _0.85 As on the GaAs substrate, and these structures are shown in FIG. It corresponds to the structure from the substrate to the subcollector layer 2.

FIG. 2A shows In _0.15 Ga on a GaAs substrate.
_{The 0.85} As sub-collector layer 2 is directly grown.
Therefore, when the term “buffer layer” is simply used, this FIG.
As described above, a mode in which the buffer layer is virtually formed by thickening the subcollector layer is also included.

FIG. 2B shows a buffer layer 1 on a GaAs substrate.
As In_0.2Ga_0.8After forming As, In_0.15Ga
_0.85The As subcollector layer 2 is grown. In
_xGa_1-xThe chemical bond of As is weaker as the In composition ratio x is larger.
I.e. soft. Therefore, on the GaAs substrate
Therefore, the In composition ratio x is set to 0.2_0.2Ga_0.8As Ba
If a buffer layer is formed, In_0.15Ga_0.85
When the As sub-collector layer is grown, In_0.15Ga
_0.85Since the As subcollector layer is harder, In _0.15Ga
_0.85In the lower layer in accordance with the As subcollector layer_0.2Ga
_0.8As the As buffer layer is strongly strained, In_0.15Ga
_0.85Lattice mismatch between As subcollector layer and GaAs substrate
Can be absorbed.

FIG. 2C shows a form of HBT (Table 1) in which the In _0.15 Ga _0.85 As subcollector layer 2 is grown after the above-mentioned compositionally graded layer is formed as the buffer layer 1. The morphological buffer layer of FIG. 2C can obtain better characteristics than those of FIGS. 2A and 2B.

The InGaP / InGaAs HBT of the present invention can be used as a substrate, either a JUST substrate or a substrate with an off angle.

[0046]

As described above, according to the present invention, the following excellent effects can be obtained.

According to the HBT of the present invention, GaAs and In
It is a lattice mismatch system of GaAs, but on a GaAs substrate,
Since the buffer layer for relaxing the lattice mismatch with the sub-collector layer is provided in the form of, for example, a compositionally graded layer, the surface roughness due to the lattice mismatch is reduced, and In
It is possible to realize an InGaP / InGaAs-based HBT using a GaAs substrate that is less expensive and less likely to be damaged than a P substrate.

Further, the HBT of the present invention has the InGaAs base layer, so that the turn-on voltage can be reduced, and an HBT driven at low power can be obtained.

Further, the HBT of the present invention has a high electron mobility in the InGaAs layer and therefore is suitable for high speed operation.

Further, since the HBT of the present invention has the InGaAs sub-collector layer, it is possible to reduce the contact resistance with the electrode when the device is manufactured.

As described above, according to the present invention, by using InGaAs for the subcollector layer, the collector layer, the base layer, and the emitter contact layer, the driving voltage of the HBT operation, the parasitic resistance of each layer, and the electrode contact resistance during the device process. Can be realized.

[Brief description of drawings]

FIG. 1 is a diagram showing a structure of an InGaP / InGaAs-based HBT of the present invention.

FIG. 2 is a diagram showing a configuration example of a buffer layer of the HBT of the present invention.

FIG. 3 shows current-voltage characteristics called a Gummel plot showing the basic characteristics of HBT, showing HBT of the present invention and H of a comparative example.
It is the figure shown about BT.

FIG. 4 is a diagram showing the In composition ratio dependence of the n value of the HBT of the present invention.

[Explanation of symbols]

1 buffer layer 2 Sub collector layer 3 Collector layer 4 base layer 5 Emitter layer 6 Emitter contact layer 7,8 Non-alloy contact layer

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Takayuki Tsuji             1-6-1, Otemachi, Chiyoda-ku, Tokyo             Standing Wire Co., Ltd. F-term (reference) 5F003 BC01 BF06 BP31

Claims (6)

[Claims] 1. A subcollector layer, a collector layer, a base layer, an emitter layer, an emitter contact layer, in order from the substrate side.
In a heterojunction bipolar transistor made of a compound semiconductor having a laminated structure in which a non-alloy contact layer is formed, a buffer layer for relaxing lattice mismatch between the substrate and the subcollector layer is provided between the substrate and the subcollector layer. A heterojunction bipolar transistor characterized by the above. 2. The heterojunction bipolar transistor according to claim 1, wherein a gradient composition layer is used as the buffer layer. 3. The substrate is made of GaAs, and the buffer layer, the subcollector layer, the collector layer, the base layer, and the emitter contact layer are made of InG.
The heterojunction bipolar transistor according to claim 1, wherein the heterojunction bipolar transistor is made of aAs and the emitter layer is an InGaP layer. 4. A buffer layer formed on a GaAs substrate as I
The In composition ratio of nGaAs was gradually increased from 0 to a predetermined value, and In grown to a thickness equal to or more than the critical thickness at which the InGaAs crystal on the GaAs crystal can maintain a pseudo-matching state.
A GaAs graded layer is formed, and on this buffer layer, an InGaAs subcollector layer, I
nGaAs collector layer, InGaAs base layer, InG
aP emitter layer, InGaAs emitter contact layer,
A heterojunction bipolar transistor characterized in that an InGaAs non-alloy contact layer is sequentially formed. 5. The In composition ratio of the InGaAs layer is 0.2.
The following is the heterojunction bipolar transistor according to any one of claims 3 to 5. 6. The buffer layer, the subcollector layer, the collector layer, the base layer, the emitter layer, the emitter contact layer, and the non-alloy contact layer are formed by a metal organic chemical vapor deposition method. The heterojunction bipolar transistor according to claim 1.