JP2003271271A - Interface circuit and semiconductor device using the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an interface circuit or the like which can perform IEEE1394 communication without use of an analog circuit. <P>SOLUTION: The interface circuit is provided with a circuit which outputs a high level Connect<SB>-</SB>detect signal, an inverter 6 which inverts a TpBias<SB>-</SB>disable signal and transmits it, a buffer B1 which transmits Strb<SB>-</SB>Tx signal, a buffer B2 which transmits a Strb<SB>-</SB>Enable signal, a buffer B3 which transmits a Data<SB>-</SB>Rx signal, buffers B4, B5 which transmit Speed<SB>-</SB>Rx(1:0) signals, a buffer B6 which transmits a Data<SB>-</SB>Tx signal, a buffer B7 which transmits a Data<SB>-</SB>Enable signal, a buffer B8 which transmits a Strb<SB>-</SB>Rx signal, a buffer B9 which transmits a Bias<SB>-</SB>Detect signal, buffers B10 and B11 which transmit Speed<SB>-</SB>Tx(1:0) signals, a first decoder circuit 7 which outputs an Arb<SB>-</SB>A<SB>-</SB>Rx(1:0) signal, and a second decoder circuit 8 which outputs an Arb<SB>-</SB>B<SB>-</SB>Rx(1:0) signal. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interface circuit for communicating with an external device based on a digital signal received from a digital signal processing circuit.
Furthermore, the present invention relates to a semiconductor device using such an interface circuit.

[0002]

2. Description of the Related Art In recent years, in data transfer between a personal computer and a peripheral device (for example, digital video camera, docking station, etc.), IEEE1
394 standard (IEEE 1394-1995 and IEEE
(Including 1394a-2000)) (hereinafter,
"IEEE 1394 communication") is used.
FIG. 31 is a diagram illustrating an example of a conventional device that uses IEEE 1394 communication. As shown in FIG. 31, the personal computer 170 and the digital video camera 171 are
They are connected by a cable (hereinafter, simply referred to as “cable”) 180 based on the IEEE 1394 standard.

FIG. 32 shows a personal computer 170.
3 is a diagram showing a part of the configuration of a digital video camera 171. FIG. As shown in FIG. 32, the personal computer 170 and the digital video camera 171 are
It includes an IEEE 1394 communication controller 172 for performing E1394 communication and termination resistance circuits 173 and 174, respectively. In addition, the cable 180 includes two wiring pairs 1
81 and 182 are included. The wire pair 181 is connected to the TPA output and TPA * output of the IEEE 1394 communication controller 172 in the personal computer 170, and in the digital video camera 171, the TPB of the IEEE 1394 communication controller 172 is connected.
It is connected to the output and the TPB * output. On the other hand, the wire pair 182 is I
It is connected to the TPB output and TPB * output of the IEEE 1394 communication controller 172, and is connected to the TPA output and TPA * output of the IEEE 1394 communication controller 172 in the digital video camera 171.

The terminating resistor circuit 173 in the personal computer 170 is an I terminal in the personal computer 170.
TpBias of EEE1394 communication controller 172
It is connected between the output / wiring pair 181 and the power supply potential (here, the ground potential V _SS ). In addition, the termination resistance circuit 174 in the personal computer 170 is connected to the wiring pair 18
2 and the power supply potential (here, the ground potential V _SS ). On the other hand, the terminating resistor circuit 173 in the digital video camera 171 is
TpB of the IEEE 1394 communication controller 172 in
It is connected between the ias output / wiring pair 182 and the power supply potential (here, the ground potential V _SS ). The terminating resistance circuit 174 in the digital video camera 171 is connected between the wiring pair 181 and the power supply potential (here, the ground potential V _SS ).

FIG. 33 is a diagram showing an internal configuration of the IEEE 1394 communication controller 172. As shown in FIG. 33, the IEEE 1394 communication controller 172 includes a logic circuit unit 190 mainly performing digital signal processing and a port interface circuit unit 1 mainly performing analog signal processing.
91 and 91 are included. The configuration of the IEEE 1394 communication controller 172 conforms to the IEEE 1394 standard, and is standard or general. The logic circuit unit 190 and the port interface circuit unit 191 are IEEE
Connect_detect signal specified in E1394 standard,
TpBias_disable signal, Strb_Tx signal, Strb_Enable signal,
Data_Rx signal, Arb_A_Rx (1: 0) signal, Speed_Rx (1: 0) signal, Data_Tx signal, Data_Enable signal, Strb_Rx signal, Arb
It sends and receives the _B_Rx (1: 0) signal, Bias_Detect signal, and Speed_Tx (1: 0) signal. In addition, the port interface circuit unit 19
1 is Tp_Bias signal, TPA signal, TPA * signal, TPB signal, TPB
* Output signal. These signals are IEEE 1394
It is a digital signal according to the standard. IEEE 1394
According to the standard, these digital signals are converted into small amplitude differential signals (analog signals) for communication.

FIG. 34 shows the port interface circuit unit 1.
It is a figure which shows the internal structure of 91. As shown in FIG. 34,
The port interface circuit unit 191 includes a constant current source 20.
1, 219, 220, operational amplifiers 202 to 209, 21
2 to 216 and resistors 210, 211, 217 and 21.
Contains 8. This port interface circuit section 19
The configuration of 1 is in accordance with the IEEE 1394 standard, and is standard or general.

FIG. 35 is a diagram showing an internal configuration of the termination resistance circuit 173. As shown in FIG. 35, the termination resistor circuit 1
73 includes resistors 183, 184 and a capacitor 185. Further, FIG. 36 is a diagram showing an internal configuration of the termination resistance circuit 174. As shown in FIG. 36, the termination resistor circuit 174 includes resistors 186 to 188 and a capacitor 1.
Contains 89.

According to the IEEE1394 standard, communication is performed by transmitting and receiving a small amplitude differential signal (analog signal). Therefore, IEEE1394
The port interface circuit 191 in the communication controller 172 had to include a large number of analog circuits as shown in FIG. In addition, the personal computer 170 and the digital video camera 171 are IEEE
In addition to the 1394 communication controller 172, it was necessary to include the termination resistance circuits 173 and 174, respectively.

For example, as shown in FIG. 37, the cable 180 is not necessary when performing IEEE 1394 communication between the personal computer 170 and the docking station 175. However, IEEE
The 1394 communication controller 172, as described above,
It was necessary to have a large number of analog circuits. Further, the personal computer 170 and the docking station 175 were required to include the termination resistance circuits 173 and 174, respectively. In addition, the two placed on the same substrate
IE between one IEEE 1394 communication controller 172
Even when performing EE1394 communication, the cable 18
0 is not necessary. However, the IEEE 1394 communication controller 172 needs to include a large number of analog circuits as described above. Furthermore, it is necessary to arrange the termination resistance circuits 173 and 174 on the substrate.

[0010]

Therefore, in view of the above points, the present invention provides an interface circuit which receives a digital signal of the IEEE 1394 standard and communicates with an external device based on the received digital signal. The purpose is to do. A further object of the present invention is to provide a semiconductor device including such an interface circuit.

[0011]

In order to solve the above problems, an interface circuit according to the present invention, based on a digital signal received from a digital signal processing circuit,
An interface circuit for performing communication with an external device, which receives a plurality of digital signals according to the IEEE 1394 standard from a digital signal processing circuit or outputs the digital signal to the digital signal processing circuit to transmit and receive digital signals to and from the external device. It is characterized by performing.

Here, a first circuit for outputting a high-level Connect_detect signal to the digital signal processing circuit, an inverter for receiving and inverting the TpBias_disable signal from the digital signal processing circuit, and a digital signal processing circuit. First buffer that receives the Strb_Tx signal from the digital signal processing circuit to the external device, a second buffer that receives the Strb_Enable signal from the digital signal processing circuit to the external device, and a Data buffer from the digital signal processing circuit
The third buffer that receives the _Tx signal and sends it to the external device, the fourth buffer that receives the Data_Enable signal from the digital signal processing circuit and sends it to the external device, and the Speed_Tx (1: 0) signal from the digital signal processing circuit The fifth and sixth buffers that receive and transmit to the external device, the seventh buffer that receives the Data_Tx signal from the external device and outputs it as the Data_Rx signal to the digital signal processing circuit, and the Speed_Tx (1: 0) from the external device. Eighth and ninth buffers that receive a signal and output it to the digital signal processing circuit as a Speed_Rx (1: 0) signal, and a Strb_Tx signal that is received from an external device and output to the digital signal processing circuit as a Strb_Rx signal 10 buffers and TpBias_disable from external device
The 11th buffer that receives the inverted signal and outputs it to the digital signal processing circuit as the Bias_Detect signal and the Data_Tx signal and the Data_Enable signal from the external device, and receives the Arb_A_Rx (1: 0) signal based on the received signal. The second circuit for generating and outputting to the digital signal processing circuit and the Strb_Tx signal and the Strb_Enable signal from the external device, and generating the Arb_B_Rx (1: 0) signal based on the received signal, and the digital signal processing circuit And a third circuit for outputting to.

A first circuit for outputting a high-level Connect_detect signal to the digital signal processing circuit, a first buffer for receiving the Strb_Tx signal from the digital signal processing circuit and transmitting the Strb_Tx signal to an external device, and a digital signal processing circuit Da from the second buffer that receives the Strb_Enable signal and sends it to the external device, and the digital signal processing circuit.
A third buffer that receives the ta_Tx signal and sends it to the external device, a fourth buffer that receives the Data_Enable signal from the digital signal processing circuit and sends it to the external device, and a Data_Tx signal that is received from the external device and digitally outputs it as the Data_Rx signal. A fifth buffer that outputs to the signal processing circuit, a sixth buffer that receives the Strb_Tx signal from the external device and outputs the Strb_Rx signal to the digital signal processing circuit, and a Data_Tx signal and the Data_Enable signal from the external device,
Generate the Arb_A_Rx (1: 0) signal based on these signals,
The second circuit that outputs to the digital signal processing circuit and the Strb_Tx signal and the Strb_Enable signal from the external device, generates Arb_B_Rx (1: 0) signal based on these signals, and outputs to the digital signal processing circuit From the circuit of 3 and digital signal processing circuit, TpBias_disable signal and Speed_Tx
The 4th circuit that receives the (1: 0) signal, converts it to a serial signal, and sends it to the external device, and TpBias_dis from the external device.
Receives the able signal and the signal obtained by converting the Speed_Tx (1: 0) signal to a serial signal, and Arb_B_Rx based on the received signal.
A fifth circuit for generating a (1: 0) signal and outputting it to the digital signal processing circuit may be provided.

Further, the Strb_Tx signal having an N-bit width (N is an integer of 2 or more) is received from the first circuit for outputting the high-level Connect_detect signal to the digital signal processing circuit and the external signal by the external signal. A first buffer group including N buffers for transmitting to the external device, a second buffer group including N buffers for receiving a Data_Tx signal having an N-bit width from the digital signal processing circuit, and transmitting the external data to an external device; A third buffer group including N buffers that receives an N-bit wide Data_Tx signal from the device and outputs it as an N-bit wide Data_Rx signal to the digital signal processing circuit, and an N-bit wide Strb_Tx signal from the external device. From the digital signal processing circuit and a fourth buffer group including N buffers for receiving and outputting N-bit width Strb_Rx signal to the digital signal processing circuit. s_disab
Strb_Tx signal, Strb_Enable signal from the second circuit that receives le signal and Speed_Tx (1: 0) signal, converts it to a serial signal, and sends it to external equipment,
Also, a third circuit that receives a signal that becomes high level when transmitting an arbitration signal and becomes low level when transmitting data synchronized with a clock signal, converts the signal into a serial signal, and transmits the serial signal to an external device; The signal processing circuit receives the Data_Tx signal, Data_Enable signal, and high level when transmitting the arbitration signal, and receives the signal that becomes low level when transmitting the data synchronized with the clock signal, converts it to a serial signal, and converts it to an external device. Data_Tx signal, Data_Enable from the 4th circuit to send to
The signal, which becomes high level when transmitting the arbitration signal, becomes low level when transmitting the data synchronized with the clock signal, receives the signal that is converted into the serial signal, and receives the Strb_Tx signal from the digital signal processing circuit. And S
Receives the trb_Enable signal and based on the received signal
Arb_A_Rx (1: 0) signal is generated and output to the digital signal processing circuit. When the Strb_Tx signal, Strb_Enable signal, and arbitration signal are transmitted from an external device, the signal becomes high level and becomes a clock signal. Receives a signal that is a low-level signal converted to a serial signal when transmitting synchronized data, and from the digital signal processing circuit,
A sixth circuit that receives the Data_Tx signal and the Data_Enable signal, generates the Arb_B_Rx (1: 0) signal based on the received signal, and outputs the signal to the digital signal processing circuit may be included.

A semiconductor device according to the present invention includes the interface circuit according to the present invention.

Here, a digital signal processing circuit may be further provided.

According to the above configuration, it is possible to receive an IEEE 1394 standard digital signal without using an analog circuit such as an operational amplifier, and to communicate with an external device based on the received digital signal.

[0018]

DETAILED DESCRIPTION OF THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. In addition, the same reference numerals are given to the same components, and the description thereof will be omitted. Figure 1
FIG. 1 shows a system using a communication controller as the first embodiment of the present invention. As shown in FIG. 1, the system includes a personal computer 1 and a docking station 2. Docking station 2
Are mounted on the bottom surface of the personal computer 1.

FIG. 2 is a view showing the docking station 2. As shown in FIG. 2, 14 electrodes 11 to 24 are arranged on the upper surface of the docking station 2. FIG. 3 is a diagram showing the bottom surface of the personal computer 1. As shown in FIG. 3, the personal computer 1
Fourteen electrodes 31 to 44 are arranged on the bottom surface of the. Then, as shown in FIG. 1, when the docking station 2 is mounted on the bottom surface of the personal computer 1, the electrodes 11 to 24 contact the electrodes 31 to 44, respectively.

FIG. 4 is a diagram showing a part of the configuration of the personal computer 1 and the docking station 2.
As shown in FIG. 4, the personal computer 1 and the docking station 2 each include an IEEE 1394 communication controller 3 that performs IEEE 1394 communication. IEEE 1394 communication controller 3 of personal computer 1 and IEEE of docking station 2
The E1394 communication controller 3 transmits / receives signals via the electrodes 11-24 and 31-44. Figure 5 shows the IEEE
It is a figure which shows the structure of the E1394 communication controller 3.
As shown in FIG. 5, the IEEE 1394 communication controller 3 includes a logic circuit unit 4 and an interface circuit unit 5. The logic circuit section 4 performs digital signal processing and outputs a digital signal specified by IEEE 1394 to the interface circuit section 5. The interface circuit section 5 receives a digital signal specified by IEEE 1394 from the logic circuit section 4, communicates with an external device based on the received digital signal, and generates an IEEE 1394 standard digital signal as a communication result. Output to section 4.

Logic circuit section 4 and interface circuit section 5
Is a Connect_detect signal, a TpBias_disable signal, which is a digital signal defined in the IEEE 1394 standard,
Strb_Tx signal, Strb_Enable signal, Data_Rx signal, Arb_A_R
x (1: 0) signal, Speed_Rx (1: 0) signal, Data_Tx signal, Data_E
nable signal, Strb_Rx signal, Arb_B_Rx (1: 0) signal, Bias_De
Send and receive tect signal and Speed_Tx (1: 0) signal.

FIG. 6 shows an IE of the personal computer 1.
The interface circuit section 5 of the IEEE 1394 communication controller 3 and the IEEE 1394 of the docking station 2
3 is a diagram showing an internal configuration of an interface circuit section 5 of the communication controller 3. FIG. The interface circuit unit 5 includes buffers B1 to B11, an inverter 6, a first decoder circuit 7, and a second decoder circuit 8.

As shown in FIG. 6, the interface circuit section 5 of the IEEE 1394 communication controller 3 of the personal computer 1 has a first power supply potential (here, _VDD ).
Is output to the logic circuit unit 4 of the IEEE 1394 communication controller 3 of the personal computer 1 as a Connect_detect signal. Similarly, I of docking station 2
The interface circuit unit 5 of the IEEE 1394 communication controller 3 outputs V _DD as a Connect_detect signal to the logic circuit unit 4 of the IEEE 1394 communication controller 3 of the docking station 2.

IEEE 13 of the personal computer 1
The inverter 6 of the interface circuit section 5 of the 94 communication controller 3 is connected to the IEEE 1 of the personal computer 1.
394 Tp output from the logic circuit unit 4 of the communication controller 3
Inverts the Bias_disable signal and outputs it. This output signal is input to the buffer B9 of the interface circuit unit 5 of the IEEE 1394 communication controller 3 of the docking station 2 via the electrodes 31 and 11. The buffer B9 of the interface circuit unit 5 of the IEEE 1394 communication controller 3 of the docking station 2 outputs this signal as a Bias_Detect signal to the logic circuit unit 4 of the IEEE 1394 communication controller 3 of the docking station 2.

IEEE 13 of the personal computer 1
The buffer B1 of the interface circuit section 5 of the 94 communication controller 3 is the IEEE1 of the personal computer 1.
394 St output by the logic circuit unit 4 of the communication controller 3
The rb_Tx signal is transmitted to the buffer B8 of the interface circuit section 5 of the IEEE 1394 communication controller 3 of the docking station 2 via the electrodes 32 and 12. The buffer B8 of the interface circuit section 5 of the IEEE 1394 communication controller 3 of the docking station 2 is
This signal is output to the logic circuit unit 4 of the IEEE 1394 communication controller 3 of the docking station 2 as a Strb_Rx signal.

IEEE 13 of the personal computer 1
The buffer B2 of the interface circuit section 5 of the 94 communication controller 3 is the IEEE1 of the personal computer 1.
394 St output by the logic circuit unit 4 of the communication controller 3
The rb_Enable signal is transmitted to the interface circuit unit 5 of the IEEE 1394 communication controller 3 of the docking station 2 via the electrodes 33 and 13. This signal is
The Strb_Tx signal output from the buffer B1 of the interface circuit unit 5 of the IEEE 1394 communication controller 3 of the personal computer 1 is input to the second decoder 8 of the interface circuit unit 5 of the IEEE 1394 communication controller 3 of the docking station 2.

FIG. 7 is a diagram showing the internal structure of the second decoder 8. As shown in FIG. 7, the second decoder 8 is
It includes a 2-input NAND gate circuit 45 and a 2-input NAND gate circuit 46 that inverts one input signal and performs a NAND operation with the other input signal. IEEE 1394 communication controller 3 of docking station 2
Of the second decoder 8 of the interface circuit unit 5 of
The D gate circuit 45 is an IE of the personal computer 1.
NAND of Strb_Tx signal output by the IEEE 1394 communication controller 3 and Strb_Enable signal output by the IEEE 1394 communication controller 3 of the personal computer 1
The calculation is performed and the signal as the calculation result is output. N of the second decoder 8 of the interface circuit section 5 of the IEEE 1394 communication controller 3 of the docking station 2
The AND gate circuit 46 outputs Strb_T output from the IEEE 1394 communication controller 3 of the personal computer 1.
The signal obtained by inverting the x signal and the I of the personal computer 1
Strb_Ena output by the EEE1394 communication controller 3
The NAND operation of the ble signal is performed and the signal as the operation result is output. Docking station 2 IEEE13
94 N of the interface circuit section 5 of the communication controller 3
The output signals of the AND gates 45 and 46 are Arb_B_Rx (1: 0).
As a signal, the docking station 2 IEEE13
94 is output to the logic circuit unit 4 of the communication controller 3.

Referring again to FIG. 6, the buffer B6 of the interface circuit section 5 of the IEEE 1394 communication controller 3 of the docking station 2 outputs the Data_Tx signal output from the logic circuit section 4 of the IEEE 1394 communication controller 3 of the docking station 2 to the electrodes 14 and 34
Via the personal computer 1 IEEE139
4 to the buffer B3 of the interface circuit unit 5 of the communication controller 3. IE of personal computer 1
The buffer B3 of the interface circuit unit 5 of the IEEE 1394 communication controller 3 outputs this signal as a Data_Rx signal to the logic circuit unit 4 of the IEEE 1394 communication controller 3 of the personal computer 1.

IEEE 13 of the docking station 2
The buffer B7 of the interface circuit unit 5 of the 94 communication controller 3 is the IEEE1 of the docking station 2.
394 Da output by the logic circuit unit 4 of the communication controller 3
The ta_Enable signal is transmitted to the interface circuit section 5 of the IEEE 1394 communication controller 3 of the personal computer 1 via the electrodes 15 and 35. This signal is
The Data_Tx signal output from the buffer B6 of the IEEE 1394 communication controller 3 of the docking station 2 is input to the first decoder 7 of the interface circuit unit 5 of the IEEE 1394 communication controller 3 of the personal computer 1.

FIG. 8 is a diagram showing the internal structure of the first decoder 7. As shown in FIG. 8, the first decoder 7 is
It includes a 2-input NAND gate circuit 29 and a 2-input NAND gate circuit 30 which inverts one input signal and performs a NAND operation with the other input signal. IEEE 1394 communication controller 3 of personal computer 1
Of the first decoder 7 of the interface circuit unit 5 of
The D gate circuit 29 is an IE of the docking station 2.
Data_Tx signal output from the buffer B6 of the EE1394 communication controller 3 and the IEEE of the docking station 2
The NAND operation of the Data_Enable signal output from the buffer B7 of the E1394 communication controller 3 is performed, and the signal as the operation result is output. Personal computer 1 I
NAND gate circuit 30 of the first decoder 7 of the interface circuit section 5 of the EEE1394 communication controller 3
Is an inverted signal of the Data_Tx signal output from the buffer B6 of the IEEE 1394 communication controller 3 of the docking station 2 and the IEEE of the docking station 2.
Output from the buffer B7 of the 1394 communication controller 3
The NAND operation of the Data_Enable signal is performed, and the signal as the operation result is output. IE of personal computer 1
The output signals of the NAND gates 29 and 30 of the first decoder 7 of the interface circuit unit 5 of the IEEE 1394 communication controller 3 are output to the logic circuit unit 4 of the IEEE 1394 communication controller 3 of the personal computer 1 as Arb_A_Rx (1: 0) signals. To be done.

Referring again to FIG. 6, the buffers B10 and B11 of the interface circuit section 5 of the IEEE 1394 communication controller 3 of the docking station 2 output Speed_Tx (1 :) output from the logic circuit section 4 of the IEEE 1394 communication controller 3 of the docking station 2. 0) The signal is transmitted to the buffers B4 and B5 of the interface circuit section 5 of the IEEE 1394 communication controller 3 of the personal computer 1 via the electrodes 16, 17, 36 and 37, respectively. IEEE139 of personal computer 1
4 The buffers B4 and B5 of the interface circuit unit 5 of the communication controller 3 use these signals as Speed_Rx (1: 0) signals to the IEEE1394 of the personal computer 1.
Output to the logic circuit unit 4 of the communication controller 3.

IEEE 13 of personal computer 1
The buffer B6 of the interface circuit section 5 of the 94 communication controller 3 is the IEEE1 of the personal computer 1.
394 Da output by the logic circuit unit 4 of the communication controller 3
The ta_Tx signal is transmitted to the buffer B3 of the interface circuit section 5 of the IEEE 1394 communication controller 3 of the docking station 2 via the electrodes 38 and 18. The buffer B3 of the interface circuit unit 5 of the IEEE 1394 communication controller 3 of the docking station 2 is
This signal is output to the logic circuit unit 4 of the IEEE 1394 communication controller 3 of the docking station 2 as a Data_Rx signal.

IEEE 13 of the personal computer 1
The buffer B7 of the interface circuit section 5 of the 94 communication controller 3 is the IEEE1 of the personal computer 1.
394 Da output by the logic circuit unit 4 of the communication controller 3
The ta_Enable signal is transmitted to the interface circuit unit 5 of the IEEE 1394 communication controller 3 of the docking station 2 via the electrodes 39 and 19. This signal is
The Data_Tx signal output from the buffer B6 of the IEEE 1394 communication controller 3 of the personal computer 1 is input to the first decoder 7 of the interface circuit unit 5 of the IEEE 1394 communication controller 3 of the docking station 2. Docking station 2 I
Based on these signals, the first decoder 7 of the interface circuit unit 5 of the IEEE 1394 communication controller 3 outputs the Arb_A_Rx (1: 0) signal to the logic circuit unit 4 of the IEEE 1394 communication controller 3 of the docking station 2.

IEEE 13 of docking station 2
The buffer B1 of the interface circuit unit 5 of the 94 communication controller 3 is the IEEE1 of the docking station 2.
394 St output by the logic circuit unit 4 of the communication controller 3
The rb_Tx signal is transmitted to the buffer B8 of the interface circuit section 5 of the IEEE 1394 communication controller 3 of the personal computer 1 via the electrodes 20 and 40. The buffer B8 of the interface circuit section 5 of the IEEE 1394 communication controller 3 of the personal computer 1 is
This signal is output to the logic circuit unit 4 of the IEEE 1394 communication controller 3 of the personal computer 1 as a Strb_Rx signal.

IEEE 13 of docking station 2
The buffer B2 of the interface circuit unit 5 of the 94 communication controller 3 is the IEEE1 of the docking station 2.
394 St output by the logic circuit unit 4 of the communication controller 3
The rb_Enable signal is transmitted to the interface circuit section 5 of the IEEE 1394 communication controller 3 of the personal computer 1 via the electrodes 21 and 41. This signal is
The Strb_Tx signal output from the buffer B1 of the IEEE 1394 communication controller 3 of the docking station 2 is input to the second decoder 8 of the interface circuit unit 5 of the IEEE 1394 communication controller 3 of the personal computer 1. Personal computer 1 I
The second decoder 8 of the interface circuit unit 5 of the IEEE 1394 communication controller 3 outputs the Arb_B_Rx (1: 0) signal to the logic circuit unit 4 of the IEEE 1394 communication controller 3 of the personal computer 1 based on these signals.

IEEE 13 of the docking station 2
The inverter 6 of the interface circuit unit 5 of the 94 communication controller 3 is connected to the IEEE 1 of the docking station 2.
394 Tp output from the logic circuit unit 4 of the communication controller 3
Inverts the Bias_disable signal and outputs it. The output signal of the inverter 6 is input to the buffer B9 of the interface circuit section 5 of the IEEE 1394 communication controller 3 of the personal computer 1 via the electrodes 22 and 42. Buffer B of interface circuit section 5 of IEEE 1394 communication controller 3 of personal computer 1
9 uses this signal as the Bias_Detect signal and the IEEE 1394 communication controller 3 of the personal computer 1.
To the logic circuit section 4 of.

IEEE 13 of the personal computer 1
The buffers B10 and B11 of the interface circuit unit 5 of the 94 communication controller 3 connect the electrodes 43 and 23, and 44 and 24 to the Speed_Tx (1: 0) signal output from the logic circuit unit 4 of the IEEE 1394 communication controller 3 of the personal computer 1. To the buffers B4 and B5 of the interface circuit section 5 in the IEEE 1394 communication controller 3 of the docking station 2, respectively.
The buffer B4 of the interface circuit section 5 of the IEEE 1394 communication controller 3 of the docking station 2,
B5 outputs these signals as Speed_Rx (1: 0) signals to the logic circuit unit 4 of the IEEE 1394 communication controller 3 of the docking station 2.

As described above, according to the interface circuit section 5, the logical operation section 4 of the personal computer 1 and the logical operation section 4 of the docking station 2 are used without using an analog circuit such as an operational amplifier unlike the conventional IEEE 1394 communication controller. It is possible to realize IEEE 1394 communication between and. Further, according to the interface circuit unit 5, the termination resistance circuit can be eliminated in the personal computer 1 and the docking station 2. Further, according to the interface circuit unit 5, the Connect_detect signal, the TpBias_disable signal, which are digital signals defined in the IEEE 1394 standard,
Strb_Tx signal, Strb_Enable signal, Data_Rx signal, Arb_A_R
x (1: 0) signal, Speed_Rx (1: 0) signal, Data_Tx signal, Data_E
nable signal, Strb_Rx signal, Arb_B_Rx (1: 0) signal, Bias_De
Since the tect signal and the Speed_Tx (1: 0) signal are transmitted / received to / from the logic circuit unit 4, the conventional logic circuit unit 4 can be used without modification, and the IEEE 1394 communication controller 3 can be easily designed. it can.

Next, a second embodiment of the present invention will be described. FIG. 9 shows a part of the configuration of a personal computer 51 and a docking station 52 using a communication controller according to the second embodiment of the present invention. Figure 9
As shown in, the personal computer 51 and the docking station 52 each include an IEEE 1394 communication controller 53. The IEEE 1394 communication controller 53 of the personal computer 51 and the IEEE 1394 communication controller 53 of the docking station 52 have electrodes 12 to 15, 18 to 21, 27, and
Signals are transmitted and received via 28, 32-35, 38-41, 47 and 48. FIG. 10 is a diagram showing the configuration of the IEEE 1394 communication controller 53. As shown in FIG. 10, the IEEE 1394 communication controller 53 includes a logic circuit unit 4 and an interface circuit unit 55.

The interface circuit section 55 has an IEEE 1
The digital signal defined in 394 is applied to the logic circuit unit 4
The digital signal of the IEEE 1394 standard is generated as a communication result, and is output to the logic circuit unit 4.
The logic circuit unit 4 and the interface circuit unit 55 are IEEE
Co, which is a digital signal specified in the 1394 standard
nnect_detect signal, TpBias_disable signal, Strb_Tx signal, Strb_Enable signal, Data_Rx signal, Arb_A_Rx (1: 0) signal, Speed_Rx (1: 0) signal, Data_Tx signal, Data_Enable signal, Strb_Rx signal, Arb_B_Rx (1: 0) signal, Bias_Detect signal , Speed_Tx (1: 0) signals are transmitted and received.

FIG. 11 shows the interface circuit section 55 of the IEEE 1394 communication controller 53 of the personal computer 51 and the IEEE of the docking station 52.
It is a figure which shows the internal structure of the interface circuit part 55 of the E1394 communication controller 53. The interface circuit unit 55 includes buffers B1 to B3 and B6 to B8, a first decoder circuit 7, a second decoder circuit 8, a third decoder circuit 56, and a first encoder circuit 57. There is.

IEEE1 of the personal computer 51
Interface circuit unit 5 of the 394 communication controller 53
5 is Connect_de for the first power supply potential (here, V _DD ).
As a tect signal, the IEEE of the personal computer 51
Output to the logic circuit unit 4 of the E1394 communication controller 53. Similarly, the docking station 52 IEEE
The interface circuit unit 55 of the 1394 communication controller 53 outputs V _DD as a Connect_detect signal to the logic circuit unit 4 of the IEEE 1394 communication controller 53 of the docking station 52.

IEEE1 of the personal computer 51
Interface circuit unit 5 of the 394 communication controller 53
The buffer B1 of No. 5 is I of the personal computer 51.
The Strb_Tx signal output from the logic circuit unit 4 of the IEEE 1394 communication controller 53 is transmitted via the electrodes 32 and 12 to the buffer B of the interface circuit unit 55 of the IEEE 1394 communication controller 53 of the docking station 52.
Send to 8. IEEE of docking station 52
The buffer B8 of the interface circuit unit 55 of the 1394 communication controller 53 outputs this signal to the logic circuit unit 4 of the IEEE 1394 communication controller 53 of the docking station 52 as a Strb_Rx signal.

IEEE1 of the personal computer 51
Interface circuit unit 5 of the 394 communication controller 53
The buffer B2 of No. 5 is I of the personal computer 51.
The Strb_Enable signal output from the logic circuit unit 4 of the IEEE 1394 communication controller 53 is transmitted to the interface circuit unit 55 of the IEEE 1394 communication controller 53 of the docking station 52 via the electrodes 33 and 13. This signal is transmitted to the IE of the personal computer 51.
The Strb_Tx signal output from the buffer B1 of the interface circuit unit 55 of the IEEE 1394 communication controller 53, and the second portion of the interface circuit unit 55 of the IEEE 1394 communication controller 53 of the docking station 52.
Is input to the decoder 8. Docking station 5
The second decoder 8 of the interface circuit unit 55 of the IEEE 1394 communication controller 53 of No. 2 outputs the Arb_B_Rx (1: 0) signal to the logic circuit unit 4 of the IEEE 1394 communication controller 53 of the docking station 52 based on these signals. .

IEEE1 of the docking station 52
Interface circuit unit 5 of the 394 communication controller 53
The buffer B6 of No. 5 is I of docking station 52.
The buffer B of the interface circuit unit 55 of the IEEE 1394 communication controller 53 of the personal computer 51 receives the Data_Tx signal output from the logic circuit unit 4 of the IEEE 1394 communication controller 53 via the electrodes 14 and 34.
Send to 3. IEEE of the personal computer 51
The buffer B3 of the interface circuit unit 55 of the 1394 communication controller 53 outputs this signal as a Data_Rx signal to the logic circuit unit 4 of the IEEE 1394 communication controller 53 of the personal computer 51.

IEEE1 of the docking station 52
Interface circuit unit 5 of the 394 communication controller 53
The buffer B7 of No. 5 is I of docking station 52.
The Data_Enable signal output from the logic circuit unit 4 of the IEEE 1394 communication controller 53 is transmitted to the interface circuit unit 55 of the IEEE 1394 communication controller 53 of the personal computer 51 via the electrodes 15 and 35. This signal is sent to the docking station 52 IE
The data_Tx signal output from the buffer B6 of the IEEE 1394 communication controller 53 is input to the first decoder 7 of the interface circuit unit 55 of the IEEE 1394 communication controller 53 of the personal computer 51.
The first decoder 7 of the interface circuit unit 55 of the IEEE 1394 communication controller 53 of the personal computer 51, based on these signals, Arb_A_Rx (1: 0).
Signal to personal computer 51 IEEE1394
Output to the logic circuit unit 4 of the communication controller 53.

IEEE1 of the docking station 52
Interface circuit unit 5 of the 394 communication controller 53
The first encoder circuit 57 of No. 5 is a TpBias_disable signal output by the logic circuit unit 4 of the IEEE 1394 communication controller 53 of the docking station 52, Speed_Tx.
Receives the (1: 0) signal. FIG. 12 is a diagram showing an internal configuration of the first encoder circuit 57. As shown in FIG. 12, the first encoder circuit 57 includes D-type flip-flops 58 to 61 and 2-input AND gate circuits 62 and 63.
It also includes a 3-input OR gate circuit 64 and an inverter 65.

A clock signal is input to the clock input terminals of the D-type flip-flops 58 to 61. The data input terminal D of the D-type flip-flop 58 has Speed_Tx
(1) A signal is input. The non-inverting output signal output from the non-inverting output terminal Q of the D-type flip-flop 58 is input to the data input terminal D of the D-type flip-flop 59. The Speed_Tx (0) signal is input to the data input terminal D of the D flip-flop 60.

The Speed_Tx (1) signal is input to one input terminal of the AND gate circuit 62, and the inverted output signal output from the inverted output terminal Q bar of the D-type flip-flop 59 is input to the other input terminal. Is entered. The Speed_Tx (0) signal is input to one input terminal of the AND gate circuit 63, and the D-type flip-flop 6 is input to the other input terminal.
The inverted output signal output from the inverted output terminal Q of 0 is input.

The output signal of the AND gate circuit 62 is input to the first input terminal of the OR gate circuit 64, and the second input terminal
The output signal of the AND gate circuit 63 is input to the input terminal of, and the TpBias_disable signal is input to the third input terminal. The output signal of the OR gate circuit 64 is input to the input terminal of the inverter 65. The output signal of the inverter 65 is input to the data input terminal D of the D flip-flop 61. The non-inverted output signal output from the non-inverted output terminal Q of the D-type flip-flop 61 becomes the output signal of the first encoder circuit 57.

As a result of the configuration shown in FIG. 12, the first encoder circuit 57 outputs a low level signal as shown in FIG. 13 when the TpBias_disable signal is at a high level. In addition, the first encoder circuit 57 uses TpBias_dis
When the able signal is low level, the Speed_Tx (1) signal is low level, and the Speed_Tx (0) signal is low level (S100
(When performing data communication at 100 Mbps))
As shown in 4, a high level signal is output.

Further, the first encoder circuit 57 uses TpBi
When the as_disable signal is low level, the Speed_Tx (1) signal is low level, and the Speed_Tx (0) signal changes from low level to high level (when data communication is performed at S200 (200 Mbps)), it is shown in FIG. As described above, a low-level pulse signal having a one-clock width is output. Also,
In the first encoder circuit 57, when the TpBias_disable signal is low level, the Speed_Tx (1) signal changes from low level to high level, and the Speed_Tx (0) signal changes from low level to high level (S400 (400 Mbps)). When performing data communication), as shown in FIG. 16, a low-level pulse signal having a 2-clock width is output.

Referring again to FIG. 11, the IEEE 1394 communication controller 53 of the personal computer 51.
Third decoder circuit 56 of the interface circuit unit 55 of
Is the first of the interface circuit section 55 of the IEEE 1394 communication controller 53 of the docking station 52.
The signal output from the encoder circuit 57 of is received. Figure 1
FIG. 7 is a diagram showing an internal configuration of the third decoder circuit 56. As shown in FIG. 17, the third decoder circuit 56 is
D-type flip-flops 66 to 75, a 3-input OR gate circuit 76, a 2-input AND gate circuit 77, a 4-input OR gate circuit 78, and a 5-input OR gate circuit 7.
Including 9 and.

A clock signal is input to the clock input terminals of the D flip-flops 66 to 75. The output signal of the first encoder circuit 57 is input to the data input terminal D of the D flip-flop 66. The non-inverting output signal output from the non-inverting output terminal Q of the D-type flip-flop 66 is input to the data input terminal D of the D-type flip-flop 67 and output from the non-inverting output terminal Q of the D-type flip-flop 67. The non-inverted output signal is input to the data input terminal D of the D flip-flop 68. OR
The non-inverting output signal output from the non-inverting output terminal Q of the D-type flip-flop 66 is input to the first input terminal of the gate circuit 76, and the non-inverting output signal of the D-type flip-flop 67 is input to the second input terminal. The non-inverting output signal output from the inverting output terminal Q is input, and the non-inverting output signal output from the non-inverting output terminal Q of the D-type flip-flop 68 is input to the third input terminal. The OR gate circuit 76 performs an OR operation on these signals and outputs the signal as the operation result to Bi.
Output as as_Detect signal.

The inverted output signal output from the inverted output terminal Q of the D-type flip-flop 66 is input to the first input terminal of the AND gate circuit 77, and the D-type flip-flop is input to the second input terminal. The inverted output signal output from the inverted output terminal Q bar of 67 is input. The output signal of the AND gate circuit 77 is input to the data input terminal D of the D-type flip-flop 69. The non-inverting output signal output from the non-inverting output terminal Q of the D-type flip-flop 69 is input to the data input terminal D of the D-type flip-flop 70, and the non-inverting output terminal Q of the D-type flip-flop 70.
The non-inverted output signal output from is input to the data input terminal D of the D-type flip-flop 71. The output signal of the AND gate circuit 77 is input to the first input terminal of the OR gate circuit 78, and the non-inverted output output from the non-inverted output terminal Q of the D-type flip-flop 69 is input to the second input terminal. A signal is input, a non-inverting output signal output from the non-inverting output terminal Q of the D-type flip-flop 70 is input to the third input terminal, and a fourth input terminal of the D-type flip-flop 71 is input. The non-inverting output signal output from the non-inverting output terminal Q is input. The OR gate circuit 78 is
An OR operation of these signals is performed, and the resulting signal is output as the Speed_Rx (1) signal.

The data input terminal D of the D-type flip-flop 72 is connected to the inverting output terminal Q of the D-type flip-flop 66.
The inverted output signal output from the bar is input. The non-inverting output signal output from the non-inverting output terminal Q of the D-type flip-flop 72 is input to the data input terminal D of the D-type flip-flop 73 and output from the non-inverting output terminal Q of the D-type flip-flop 73. The non-inverted output signal is input to the data input terminal D of the D flip-flop 74,
The non-inverting output signal output from the non-inverting output terminal Q of the D-type flip-flop 74 is input to the data input terminal D of the D-type flip-flop 75. The inverted output signal output from the inverted output terminal Q bar of the D-type flip-flop 66 is input to the first input terminal of the OR gate circuit 79, and the non-input of the D-type flip-flop 72 is input to the second input terminal. The non-inverted output signal output from the inverting output terminal Q is input, and the D-type flip-flop 73 is input to the third input terminal.
The non-inverted output signal output from the non-inverted output terminal Q of the D-type flip-flop 7 is input to the fourth input terminal.
The non-inverting output signal output from the non-inverting output terminal Q of No. 4 is input, and the non-inverting output signal output from the non-inverting output terminal Q of the D-type flip-flop 75 is input to the fifth input terminal. . The OR gate circuit 79 performs an OR operation on these signals and outputs the resulting signal as Speed_Rx (0).
Output as a signal.

As a result of the configuration as shown in FIG. 17, the third decoder circuit 56 has the first encoder circuit 57 shown in FIG.
When outputting the signal shown in, the low level Bi
Outputs as_Detect signal. In addition, the third decoder circuit 56 outputs the high-level Bias_Detect when the first encoder circuit 57 outputs a signal as shown in FIG.
The signal, the low-level Speed_Rx (1) signal, and the low-level Speed_Rx (0) signal are output. Further, when the first encoder circuit 57 outputs the signal as shown in FIG. 15, the third decoder circuit 56 outputs the high-level Bias_D.
It outputs an etect signal, a Low-level Speed_Rx (1) signal, and a Speed_Rx (0) signal that is a high-level pulse for 5 clocks. Furthermore, the third decoder circuit 56 is
16 outputs a signal as shown in FIG. 16, Bias_Detect signal of high level, Speed_Rx (1) signal which becomes a high level pulse for 4 clocks,
And Speed_ that becomes a high-level pulse for 5 clocks
Output the Rx (0) signal.

Referring again to FIG. 11, the IEEE 1394 communication controller 53 of the personal computer 51.
The buffer B6 of the interface circuit 55 of the docking station 52 receives the Data_Tx signal output from the logic circuit 4 of the IEEE 1394 communication controller 53 of the personal computer 51 via the electrodes 38 and 18.
To the buffer B3 of the interface circuit section 55 of the IEEE 1394 communication controller 53. The buffer B3 of the interface circuit unit 55 of the IEEE 1394 communication controller 53 of the docking station 52 outputs this signal as a Data_Rx signal to the logic circuit unit 4 of the IEEE 1394 communication controller 53 of the docking station 52.

IEEE1 of the personal computer 51
Interface circuit unit 5 of the 394 communication controller 53
The buffer B7 of No. 5 is the I of the personal computer 51.
The Data_Enable signal output from the logic circuit unit 4 of the IEEE 1394 communication controller 53 is transmitted to the interface circuit unit 55 of the IEEE 1394 communication controller 53 of the docking station 52 via the electrodes 39 and 19. This signal is transmitted to the IE of the personal computer 51.
The Data_Tx signal output from the buffer B6 of the interface circuit unit 55 of the IEEE 1394 communication controller 53 and the first interface circuit unit 55 of the IEEE 1394 communication controller 53 of the docking station 52
Is input to the decoder 7. Docking station 5
The first decoder 7 of the interface circuit unit 55 of the IEEE 1394 communication controller 53 of No. 2 outputs the Arb_A_Rx (1: 0) signal to the logic circuit unit 4 of the IEEE 1394 communication controller 53 of the docking station 52 based on these signals. .

IEEE1 of the docking station 52
Interface circuit unit 5 of the 394 communication controller 53
Buffer B1 of 5 is I of docking station 52
The Strb_Tx signal output from the logic circuit unit 4 of the IEEE 1394 communication controller 53 is transmitted via the electrodes 20 and 40 to the buffer B of the interface circuit unit 55 of the IEEE 1394 communication controller 53 of the personal computer 51.
Send to 8. IEEE of the personal computer 51
The buffer B8 of the interface circuit unit 55 of the 1394 communication controller 53 outputs this signal as a Strb_Rx signal to the logic circuit unit 4 of the IEEE 1394 communication controller 53 of the personal computer 51.

IEEE1 of the docking station 52
Interface circuit unit 5 of the 394 communication controller 53
The buffer B2 of No. 5 is I of docking station 52.
The Strb_Enable signal output from the logic circuit unit 4 of the IEEE 1394 communication controller 53 is transmitted to the interface circuit unit 55 of the IEEE 1394 communication controller 53 of the personal computer 51 via the electrodes 21 and 41. This signal is sent to the docking station 52 IE
The Strb_Tx signal output from the buffer B1 of the interface circuit unit 55 of the IEEE 1394 communication controller 53 is used together with the second signal of the interface circuit unit 55 of the IEEE 1394 communication controller 53 of the personal computer 51.
Is input to the decoder circuit 8. The second decoder 8 of the interface circuit section 55 of the IEEE 1394 communication controller 53 of the personal computer 51 sends the Arb_B_Rx (1: 0) signal to the IEEE 1394 communication controller 53 of the personal computer 51 based on these signals.
To the logic circuit section 4 of.

IEEE1 of the personal computer 51
Interface circuit unit 5 of the 394 communication controller 53
The first encoder circuit 57 of No. 5 is the TpBias_disable signal output by the logic circuit unit 4 of the IEEE 1394 communication controller 53 of the personal computer 51, Speed_Tx.
Receives the (1: 0) signal. The output signal of the first encoder circuit 57 of the interface circuit section 55 of the IEEE 1394 communication controller 53 of the personal computer 51 is transmitted through the electrodes 48 and 28 to the third output signal of the interface circuit section 55 of the IEEE 1394 communication controller 53 of the docking station 52. It is input to the decoder circuit 56. Docking station 52 IEEE 1394
The third decoder circuit 56 of the interface circuit unit 55 of the communication controller 53 is the personal computer 51.
Bias_Detect signal, Speed_Rx (1: 0) signal based on the output signal of the first encoder circuit 57 of the interface circuit unit 55 of the IEEE 1394 communication controller 53 of
The signal is output to the logic circuit unit 4 of the interface circuit unit 55 of the IEEE 1394 communication controller 53 of the docking station 52.

As described above, according to the interface circuit section 55, the interface circuit 5 shown in FIG. 6 uses 14 sets of electrodes (electrodes 11 to 24, 31 to 44).
Less 10 sets of electrodes (electrodes 12-15, 18-2
1, 27, 28, 32-35, 38-41, 47, 4
By using 8), IEEE communication between the logical operation unit 4 of the personal computer 1 and the logical operation unit 4 of the docking station 2 can be realized.

Next, a third embodiment of the present invention will be described. In the interface circuits 5 and 55 described above, since data transmission / reception is performed serially, S40
It may be difficult to perform data communication equivalent to 0 (400 Mbps). The present embodiment can prevent such a situation. FIG. 18 shows a personal computer 81 and a docking station 8 using a communication controller according to the third embodiment of the present invention.
2 shows a part of the configuration of 2. As shown in FIG. 18, a personal computer 81 and a docking station 82
Each include an IEEE 1394 communication controller 83. IEEE1 of personal computer 81
The 394 communication controller 83 and the IEEE 1394 communication controller 83 of the docking station 82 have electrodes 27, 28, 91-94, 47, 48, 101-10.
4, 231 to 262, and 271 to 302. IEEE13 of personal computer 81
94 Communication controller 83 and docking station 8
The second IEEE 1394 communication controller 83 is an IEEE
Data communication corresponding to S400 (400 Mbps) in the E1394 standard is performed.

FIG. 19 is a diagram showing the configuration of the IEEE 1394 communication controller 83. As shown in FIG.
The IEEE 1394 communication controller 83 includes a logic circuit section 84 and an interface circuit section 85. The logic circuit section 84 performs digital signal processing and outputs the digital signal to the interface circuit section 85. The interface circuit unit 85 converts the digital signal into the logic circuit unit 8
4 to communicate with an external device based on the received digital signal, generate a digital signal as a communication result, and output the digital signal to the logic circuit unit 84.

Logic circuit section 84 and interface circuit section 8
5 is a Connect_detect signal, TpBias_disable signal, Strb_Enable signal, Arb_A_Rx (1: 0) signal, Speed_Rx which are digital signals defined by the IEEE 1394 standard.
(1: 0) signal, Data_Enable signal, Arb_B_Rx (1: 0) signal, Bia
Sends / receives the s_Detect signal and Speed_Tx (1: 0) signal. Further, the logic circuit unit 84 and the interface circuit unit 85 are
Strb_Tx signal, which is supposed to be transmitted / received bit by bit in the EEE 1394 standard, has a width of 8 bits.
Tx (7: 0) signal, Data_Rx (7: 0) signal with 8-bit width of Data_Rx signal, which is supposed to be sent / received bit by bit in the IEEE 1394 standard, and sent / received bit by bit in the IEEE 1394 standard It is said that Da
Data_Tx (7: 0) signal in which ta_Tx signal is 8 bits wide, IE
The Strb_Rx signal, which is supposed to be transmitted and received bit by bit in the EE1394 standard, has a width of 8 bits.
Sends and receives the (7: 0) signal. Further, the logic circuit unit 84 and the interface circuit unit 85 are connected to each other by an arbitration signal (arbitration si).
It sends and receives Arb / Data bar signals that go to high level when sending gnal) and go to low level when sending data that is synchronized with a clock signal (clocked data). this
The Arb / Data bar signal is a signal that is not in the IEEE 1394 standard.

FIG. 20 shows the interface circuit section 85 of the IEEE 1394 communication controller 83 of the personal computer 81 and the IEEE of the docking station 82.
It is a figure which shows the internal structure of the interface circuit part 85 of the E1394 communication controller 83. As shown in FIG. 20, the interface circuit unit 85 includes buffers B21 to B21.
52, a third decoder circuit 56, a first encoder circuit 57, a second encoder circuit 86, a fourth decoder circuit 87, a third encoder circuit 88, and a fifth decoder circuit 89. Is included.

IEEE1 of personal computer 81
Interface circuit unit 8 of the 394 communication controller 83
5 is Connect_de for the first power supply potential (here, V _DD ).
As a tect signal, the IEEE of the personal computer 81
Output to the logic circuit unit 84 of the E1394 communication controller 83. Similarly, the docking station 82 IEEE
The interface circuit unit 85 of the E1394 communication controller 83 outputs V _DD as a Connect_detect signal to the logic circuit unit 84 of the IEEE 1394 communication controller 83 of the docking station 82.

IEEE1 of personal computer 81
Interface circuit unit 8 of the 394 communication controller 83
The buffers B21 to B28 of No. 5 output the Strb_Tx (7: 0) signals output from the logic circuit section 84 of the IEEE 1394 communication controller 83 of the personal computer 81 to the electrodes 271 to 271.
It transmits to the buffer B45-B52 of the interface circuit part 85 of the IEEE1394 communication controller 83 of the docking station 82 via 278 and 231-238. IEEE 13 of docking station 82
Interface circuit section 85 of communication controller 83
The buffers B45 to B52 of the Strb_Rx
IE of docking station 82 as (7: 0) signal
Output to the logic circuit section 84 of the EE1394 communication controller 83.

IEEE1 of personal computer 81
Interface circuit unit 8 of the 394 communication controller 83
The second encoder circuit 86 of No. 5 is a predetermined one bit of the Strb_Tx (7: 0) signal output by the logic circuit unit 84 of the IEEE 1394 communication controller 83 of the personal computer 81, the Strb_Enable signal, and the Arb / Data bar. Receive the signal. FIG. 21 is a diagram showing an internal configuration of the second encoder circuit 86. As shown in FIG. 21, the second encoder circuit 86 includes a 3-input AND gate circuit 111.
And an inverter 112 and a 2-input OR gate circuit 11
3 and a D-type flip-flop 114.

An Arb / Data bar signal is input to the first input terminal of the AND gate circuit 111, and a predetermined 1 bit of the Strb_Tx (7: 0) signal is input to the second input terminal. , The third input terminal has a D-type flip-flop 114
The inversion output signal output from the inversion output terminal Q of is input. The output signal of the AND gate circuit 111 is OR
It is input to the first input terminal of the gate circuit 113. The Strb_Enable signal is input to the inverter 112, and the output signal of the inverter 112 is input to the second input terminal of the OR gate circuit 113. The output signal of the OR gate circuit 113 is input to the data input terminal D of the D-type flip-flop 114. In addition, the D-type flip-flop 114
A clock signal is input to the clock input terminal of.

Referring again to FIG. 20, the IEEE 1394 communication controller 83 of the personal computer 81.
Second encoder circuit 8 of the interface circuit section 85 of
The output signal of 6 is input to the fifth decoder circuit 89 of the interface circuit unit 85 of the IEEE 1394 communication controller 83 of the docking station 82 via the electrodes 101 and 91. Docking station 82 I
The fifth decoder circuit 89 of the interface circuit unit 85 of the IEEE 1394 communication controller 83 has a predetermined 1 bit in the Data_Tx (7: 0) signal output from the logical operation unit 84 of the IEEE 1394 communication controller 83 of the docking station 82 and The Data_Enable signal is also input.
FIG. 22 is a diagram showing the internal structure of the fifth decoder circuit 89. As shown in FIG. 22, a fifth decoder circuit 89
Are D-type flip-flops 115 and 116 and EXNO.
R gate circuit 117, inverter 118, AND gate circuits 119, 120, 125, and OR gate circuit 1
21, 124, 126 and the NAND gate circuit 122
And a NOR gate circuit 123.

A clock signal is input to the clock input terminals of the D-type flip-flops 115 and 116. The data input terminal D of the D-type flip-flop 115 has a second
The output signal of the encoder circuit 86 is input. The non-inverting output signal output from the non-inverting output terminal Q of the D-type flip-flop 115 is input to the data input terminal D of the D-type flip-flop 116.

The inverted input signal output from the inverted output terminal Q of the D-type flip-flop 115 is input to the first input terminal of the EXNOR gate circuit 117, and the D-type flip-flop is input to the second input terminal. The inverted output signal output from the inverted output terminal Q bar of 116 is input.
The Data_Enable signal is input to the inverter 118.

A predetermined one bit of the Strb_Tx (7: 0) signal is input to the non-inverting input terminal of the AND gate circuit 119, and the output signal of the inverter 118 is input to the inverting input terminal. The output signal of the inverter 118 is input to one input terminal of the AND gate circuit 120, and the non-inverting output signal output from the non-inverting output terminal Q of the D-type flip-flop 116 is input to the other input terminal. It

The output signal of the AND gate circuit 119 is input to one input terminal of the OR gate circuit 121, and the output signal of the AND gate circuit 120 is input to the other input terminal. The output signal of the OR gate circuit 121 is input to the inverting input terminal of the NAND gate circuit 122,
The output signal of the EXNOR gate circuit 117 is input to the non-inverting input terminal. The output signal of the NAND gate circuit 122 is output as an Arb_B_Rx (1) signal.

One input terminal of the Strb_Tx (7: 0) signal is input to one input terminal of the NOR gate circuit 123, and the output signal of the inverter 118 is input to the other input terminal. The output signal of the inverter 118 is input to one input terminal of the OR gate circuit 124, and the inverted output signal output from the inverted output terminal Q bar of the D-type flip-flop 116 is input to the other input terminal. .

The output signal of the OR gate circuit 124 is input to one input terminal of the AND gate circuit 125, and the output signal of the EXNOR gate circuit 117 is input to the other input terminal. The output signal of the AND gate circuit 125 is input to one input terminal of the OR gate circuit 126, and the output signal of the NOR gate circuit 123 is input to the other input terminal. The output signal of the OR gate circuit 126 is output as the Arb_B_Rx (0) signal.

Referring again to FIG. 20, the IEEE 1394 communication controller 83 of the docking station 82.
B37 to B44 of the interface circuit unit 85 of
Is the Data_T output from the logic circuit unit 84 of the IEEE 1394 communication controller 83 of the docking station 82.
The x (7: 0) signal is transmitted via the electrodes 239 to 246 and 279 to 286 to the IEEE 139 of the personal computer 81.
4 to the buffers B29 to B36 of the interface circuit unit 85 of the communication controller 83. Buffers B29 to B36 of the interface circuit unit 85 of the IEEE 1394 communication controller 83 of the personal computer 81
Outputs these signals as Data_Rx (7: 0) signals to the logic circuit section 84 of the IEEE 1394 communication controller 83 of the personal computer 81.

IEEE 1 of the docking station 82
Interface circuit unit 8 of the 394 communication controller 83
The third encoder circuit 88 of No. 5 is a predetermined one bit of the Data_Tx (7: 0) signal output by the logic circuit unit 84 of the IEEE 1394 communication controller 83 of the docking station 82, the Data_Enable signal, and the Arb / Data bar. Receive the signal. FIG. 23 is a diagram showing an internal configuration of the third encoder circuit 88. As shown in FIG. 22, the third encoder circuit 88 includes a 3-input AND gate circuit 127.
, An inverter 128, and a 2-input OR gate circuit 12
9 and a D-type flip-flop 130.

An Arb / Data bar signal is input to the first input terminal of the AND gate circuit 127, and a predetermined 1 bit of the Data_Tx (7: 0) signal is input to the second input terminal. , The D-type flip-flop 130 is connected to the third input terminal.
The inversion output signal output from the inversion output terminal Q of is input. The output signal of the AND gate circuit 127 is OR
It is input to one input terminal of the gate circuit 129. The Data_Enable signal is input to the inverter 128, and the output signal of the inverter 128 is input to the other input terminal of the OR gate circuit 129. The output signal of the OR gate circuit 129 is input to the data input terminal D of the D-type flip-flop 130. In addition, the D-type flip-flop 130
A clock signal is input to the clock input terminal of.

Referring again to FIG. 20, the IEEE 1394 communication controller 83 of the docking station 82.
Third encoder circuit 8 of the interface circuit section 85 of
The output signal of No. 8 is input to the fourth decoder circuit 87 of the interface circuit unit 85 of the IEEE 1394 communication controller 83 of the personal computer 81 via the electrodes 92 and 102. I of the personal computer 81
The fourth decoder circuit 87 of the interface circuit unit 85 of the IEEE 1394 communication controller 83 has a predetermined one bit of the Strb_Tx (7: 0) signal output from the logical operation unit 84 of the IEEE 1394 communication controller 83 of the personal computer 81 and Strb_Enable signal is also input.
FIG. 24 is a diagram showing the internal structure of the fourth decoder circuit 87. As shown in FIG. 24, the fourth encoder circuit 8
7 is a D-type flip-flop 131, 132 and EXN
OR gate circuit 133, inverter 134, AND
Gate circuits 135, 136 and 141, OR gate circuits 137, 140 and 142, and a NAND gate circuit 138.
And a NOR gate circuit 139.

A clock signal is input to the clock input terminals of the D-type flip-flops 131 and 132. The data input terminal D of the D-type flip-flop 131 has a third
The output signal of the encoder circuit 88 of is input. The non-inverting output signal output from the non-inverting output terminal Q of the D-type flip-flop 131 is input to the data input terminal D of the D-type flip-flop 132.

The inverted output signal output from the inverted output terminal Q bar of the D-type flip-flop 131 is input to the first input terminal of the EXNOR gate circuit 133, and the D-type flip-flop is input to the second input terminal. The inverted output signal output from the inverted output terminal Q bar of 132 is input.
The Strb_enable signal is input to the inverter 134.

A predetermined 1 bit of the Strb_Tx (7: 0) signal is input to the non-inverting input terminal of the AND gate circuit 135, and the output signal of the inverter 134 is input to the inverting input terminal. The output signal of the inverter 134 is input to one input terminal of the AND gate circuit 136, and the non-inverting output signal output from the non-inverting output terminal Q of the D-type flip-flop 132 is input to the other input terminal. It

The output signal of the AND gate circuit 135 is input to one input terminal of the OR gate circuit 137, and the output signal of the AND gate circuit 136 is input to the other input terminal. The output signal of the OR gate circuit 137 is input to the inverting input terminal of the NAND gate circuit 138,
The output signal of the EXNOR gate circuit 133 is input to the non-inverting input terminal. The output signal of the NAND gate circuit 138 is output as the Arb_A_Rx (1) signal.

One bit of the Strb_Tx (7: 0) signal is input to one input terminal of the NOR gate circuit 139, and the output signal of the inverter 134 is input to the other input terminal. The output signal of the inverter 134 is input to one input terminal of the OR gate circuit 140, and the inverted output signal output from the inverted output terminal Q bar of the D-type flip-flop 132 is input to the other input terminal. .

The output signal of the OR gate circuit 140 is input to one input terminal of the AND gate circuit 141, and the output signal of the EXNOR gate circuit 133 is input to the other input terminal. The output signal of the AND gate circuit 141 is input to one input terminal of the OR gate circuit 142, and the output signal of the NOR gate circuit 139 is input to the other input terminal. The output signal of the OR gate circuit 142 is output as the Arb_A_Rx (0) signal.

Referring again to FIG. 20, the IEEE 1394 communication controller 83 of the docking station 82.
First encoder circuit 5 of the interface circuit unit 85 of
7 is the docking station 82 IEEE 1394
TpBi output by the logic circuit unit 84 of the communication controller 83
Receives as_disable signal and Speed_Tx (1: 0) signal. The first encoder circuit 57 of the interface circuit unit 85 of the IEEE 1394 communication controller 83 of the docking station 82 is connected to the third decoder circuit 56 of the interface circuit unit 85 of the IEEE 1394 communication controller 83 of the personal computer 81 via the electrodes 92 and 102. To send a signal to. Personal computer 81
The third decoder circuit 56 of the interface circuit unit 85 of the IEEE 1394 communication controller 83 receives the signal output from the first encoder circuit 57 of the interface circuit unit 85 of the IEEE 1394 communication controller 83 of the docking station 82. Third decoder circuit 56 of interface circuit section 85 of IEEE 1394 communication controller 83 of personal computer 81
Bias_Detect signal, Speed_Rx based on this signal
The (1: 0) signal is sent to the IEEE1 of the personal computer 81
394 Output to the logic circuit unit 84 of the communication controller 83.

IEEE1 of personal computer 81
Interface circuit unit 8 of the 394 communication controller 83
The buffers B37 to B44 of No. 5 output the Data_Tx (7: 0) signals output from the logic circuit section 84 of the IEEE 1394 communication controller 83 of the personal computer 81 to the electrodes 287 to 287.
It transmits to the buffer B29-B36 of the interface circuit part 85 of the IEEE1394 communication controller 83 of the docking station 82 via 294 and 247-254. IEEE 13 of docking station 82
Interface circuit section 85 of communication controller 83
The buffers B29 to B36 of Data_Rx
IE of docking station 82 as (7: 0) signal
Output to the logic circuit section 84 of the EE1394 communication controller 83.

IEEE1 of personal computer 81
Interface circuit unit 8 of the 394 communication controller 83
The third encoder circuit 88 of No. 5 has a predetermined 1 bit in the Data_Tx (7: 0) signal output from the logic circuit section 84 of the IEEE 1394 communication controller 83 of the personal computer 81, the Data_Enable signal, and the Arb / Data bar. Receive the signal. IEEE1 of personal computer 81
Interface circuit unit 8 of the 394 communication controller 83
The third encoder circuit 88 of No. 5 via the electrodes 103, 93 causes the IEEE 139 of the docking station 82 to
The signal is transmitted to the fourth decoder circuit 87 of the interface circuit section 85 of the 4-communication controller 83. In the fourth decoder circuit 87 of the interface circuit section 85 of the IEEE 1394 communication controller 83 of the docking station 82, the IEEE 13 of the docking station 82 is connected.
94 Output from the logical operation unit 84 of the communication controller 83
Strb_Tx (7: 0) signal with a predetermined 1 bit and Strb_Enabl
The e signal is also input. Docking station 82 I
The fourth decoder circuit 87 of the interface circuit unit 85 of the EEE1394 communication controller 83 has Arb_A_Rx (1:
0) signal to the docking station 82 IEEE13
Interface circuit section 85 of communication controller 83
To the logic circuit section 84.

IEEE 1 of the docking station 82
Interface circuit unit 8 of the 394 communication controller 83
The buffers B21 to B28 of No. 5 output the Strb_Tx (7: 0) signals output from the logic circuit section 84 of the IEEE 1394 communication controller 83 of the docking station 82 to the electrodes 255 to 255.
It transmits to the buffer B45-B52 of the interface circuit part 85 of the IEEE1394 communication controller 83 of the personal computer 81 via 262 and 295-302. IEEE13 of personal computer 81
Interface circuit section 85 of communication controller 83
The buffers B45 to B52 of the Strb_Rx
As the (7: 0) signal, the IE of the personal computer 81
Output to the logic circuit section 84 of the EE1394 communication controller 83.

IEEE1 of the docking station 82
Interface circuit unit 8 of the 394 communication controller 83
The second encoder circuit 86 of No. 5 is a predetermined 1 bit of the Strb_Tx (7: 0) signal output by the logic circuit unit 84 of the IEEE 1394 communication controller 83 of the docking station 82, the Strb_Enable signal, and the Arb / Data bar. Receive the signal. IEEE1 of docking station 82
Interface circuit unit 8 of the 394 communication controller 83
The second encoder circuit 86 of No. 5 is connected to the IEEE 139 of the personal computer 81 via the electrodes 94 and 104.
The signal is output to the fifth decoder circuit 89 of the interface circuit unit 85 of the 4-communication controller 83. The fifth decoder circuit 89 of the interface circuit unit 85 of the IEEE 1394 communication controller 83 of the personal computer 81 sends the Arb_B_Rx (1: 0) signal to the logical operation unit 84 of the interface circuit unit 85 of the IEEE 1394 communication controller 83 of the personal computer 81. Output.

IEEE1 of personal computer 81
Interface circuit unit 8 of the 394 communication controller 83
The first encoder circuit 57 of No. 5 is the TpBias_disable signal output by the logic circuit unit 84 of the IEEE 1394 communication controller 83 of the personal computer 81, Speed_Tx.
Receives the (1: 0) signal. The first encoder circuit 57 of the interface circuit unit 85 of the IEEE 1394 communication controller 83 of the personal computer 81 has the electrode 4
IE of docking station 82 via 8, 28
The signal is transmitted to the third decoder circuit 56 of the interface circuit section 85 of the EE1394 communication controller 83.
The third decoder circuit 56 of the interface circuit section 85 of the IEEE 1394 communication controller 83 of the docking station 82 is the IEEE of the personal computer 81.
The signal output from the first encoder circuit 57 of the interface circuit unit 85 of the EE1394 communication controller 83 is received. IEEE 13 of docking station 82
Interface circuit section 85 of communication controller 83
Based on this signal, the third decoder circuit 56 of
The as_Detect signal and the Speed_Rx (1: 0) signal are output to the logic circuit unit 84 of the IEEE 1394 communication controller 83 of the docking station 82.

As described above, according to the interface circuit section 85, since the Strb_Tx signal and the Data_Tx signal are transmitted / received with an 8-bit width, data communication equivalent to S400 (400 Mbps) can be performed at an operating frequency of 50 MHz.

Next explained is the fourth embodiment of the invention. FIG. 25 is a personal computer 151 using a communication controller according to the fourth embodiment of the present invention.
A part of the configuration of the docking station 152 is shown. As shown in FIG. 25, the personal computer 15
1 and the docking station 152 are IEEE13
Each includes a 94 communication controller 153. I
The EEE1394 communication controller 153 includes an interface circuit unit 155. The IEEE 1394 communication controller 153 of the personal computer 151 and the IEEE 1394 communication controller 153 of the docking station 152 have electrodes 27, 28, 91-94,
47, 48, 101-104, 231-234, 239
~ 242, 247-250, 255-258, 271-
274, 279 to 282, 287 to 290, 295 to 2
Signals are transmitted and received via 98. The IEEE 1394 communication controller 153 of the personal computer 151 and the IEEE 1394 communication controller 153 of the docking station 152 perform data communication corresponding to S200 (200 Mbps) in the IEEE 1394 standard.

FIG. 26 is a diagram showing the configuration of the IEEE 1394 communication controller 153. As shown in FIG. 26, the IEEE 1394 communication controller 153 includes a logic circuit unit 154 and an interface circuit unit 155. The logic circuit unit 154 performs digital signal processing and outputs the digital signal to the interface circuit unit 155. The interface circuit unit 155 receives a digital signal from the logic circuit unit 154, communicates with an external device based on the received digital signal, generates a digital signal as a communication result, and outputs the digital signal to the logic circuit unit 154.

The logic circuit section 154 and the interface circuit section 155 are connected to the Connect_detect signal and TpBias_disable signal which are digital signals defined in the IEEE 1394 standard.
Signal, Strb_Enable signal, Arb_A_Rx (1: 0) signal, Speed_Rx
(1: 0) signal, Data_Enable signal, Arb_B_Rx (1: 0) signal, Bia
Sends / receives the s_Detect signal and Speed_Tx (1: 0) signal. Further, the logic circuit unit 154 and the interface circuit unit 155
Is a Strb_Tx (3: 0) signal that has a 4-bit width for the Strb_Tx signal that is supposed to be transmitted / received bit by bit in the IEEE 1394 standard, and a Data_Rx signal that is sent and received bit by bit in the IEEE 1394 standard. Data_Rx (3: 0) signal with 4 bits width, IEEE139
The Data_Tx (3: 0) signal, which has a 4-bit width for the Data_Tx signal that is transmitted / received in 1 bit in the 4 standards, and the Strb_Rx signal, which is transmitted / received in 1 bit in the IEEE 1394 standard, are used. Strb_Rx (3: 0) signals with a bit width are transmitted and received. Further, the logic circuit unit 154 and the interface circuit unit 155 are connected to each other by the arbitration signal (ar
It sends and receives an Arb / Data bar signal that goes high when transmitting a bitration signal) and goes low when transmitting data (clocked data) synchronized with a clock signal. This Arb / Data bar signal is an IEEE 1394 signal.
This signal is not in the standard.

FIG. 27 shows a personal computer 151.
Interface circuit section 155 of the IEEE 1394 communication controller 153 and the docking station 152
3 is a diagram showing an internal configuration of an interface circuit unit 155 of the IEEE 1394 communication controller 153 of FIG. FIG. 27
As shown in, the interface circuit unit 155 includes buffers B21 to B24, B29 to B32, B37 to B40,
B45 to B48, a third decoder circuit 56, a first encoder circuit 57, a second encoder circuit 86,
Fourth decoder circuit 87 and third encoder circuit 88
And a fifth decoder circuit 88.

In this way, the interface circuit section 155
According to this, since the Strb_Tx signal and the Data_Tx signal are transmitted / received with a 4-bit width, data communication equivalent to S200 (200 Mbps) can be performed at an operating frequency of 50 MHz.

Next explained is the fifth embodiment of the invention. FIG. 28 shows a personal computer 161 using a communication controller according to the fifth embodiment of the present invention.
A part of the configuration of the docking station 162 is shown. As shown in FIG. 28, the personal computer 16
1 and docking station 162 are IEEE13
94 communication controllers 163 are included. I
The EEE1394 communication controller 163 includes an interface circuit unit 165. The IEEE 1394 communication controller 163 of the personal computer 161 and the IEEE 1394 communication controller 163 of the docking station 162 include electrodes 27, 28, 91-94,
47, 48, 101-104, 231-232, 239
~ 240, 247-248, 255-256, 271-
272, 279-280, 287-288, 295-2
Send and receive signals via 96. The IEEE 1394 communication controller 163 of the personal computer 161 and the IEEE 1394 communication controller 163 of the docking station 162 perform data communication corresponding to S100 (100 Mbps) in the IEEE 1394 standard.

FIG. 29 is a diagram showing the configuration of the IEEE 1394 communication controller 163. As shown in FIG. 29, the IEEE 1394 communication controller 163 includes a logic circuit section 164 and an interface circuit section 165. The logic circuit unit 164 performs digital signal processing and outputs the digital signal to the interface circuit unit 165. The interface circuit unit 165 receives a digital signal from the logic circuit unit 164, communicates with an external device based on the received digital signal, generates a digital signal as a communication result, and outputs the digital signal to the logic circuit unit 164.

The logic circuit section 164 and the interface circuit section 165 are connected to the Connect_detect signal and TpBias_disable signal which are digital signals defined in the IEEE 1394 standard.
Signal, Strb_Enable signal, Arb_A_Rx (1: 0) signal, Speed_Rx
(1: 0) signal, Data_Enable signal, Arb_B_Rx (1: 0) signal, Bia
Sends / receives the s_Detect signal and Speed_Tx (1: 0) signal. The logic circuit unit 164 and the interface circuit unit 165 are also provided.
Is a Strb_Tx (1: 0) signal in which the Strb_Tx signal, which is supposed to be transmitted / received bit by bit in the IEEE1394 standard, has a 2-bit width, and a Data_Rx signal, which is sent / received bit by bit in the IEEE1394 standard. Data_Rx (1: 0) signal with 2 bits width, IEEE139
The Data_Tx (1: 0) signal, which has a 2 bit width for the Data_Tx signal, which is supposed to be transmitted / received in 1 bit in the 4 standards, and the Strb_Rx signal, which is supposed to be sent / received in 1 bit in the IEEE 1394 standard, are used. Strb_Rx (1: 0) signals with a bit width are transmitted and received. Further, the logic circuit unit 164 and the interface circuit unit 165 are connected to the arbitration signal (ar
It sends and receives an Arb / Data bar signal that goes high when transmitting a bitration signal) and goes low when transmitting data (clocked data) synchronized with a clock signal. This Arb / Data bar signal is an IEEE 1394 signal.
This signal is not in the standard.

FIG. 30 shows a personal computer 161.
Interface circuit section 165 of the IEEE 1394 communication controller 163 and the docking station 162
3 is a diagram showing an internal configuration of an interface circuit section 165 of the IEEE 1394 communication controller 163 of FIG. Figure 30
As shown in, the interface circuit unit 165 includes buffers B21 to B22, B29 to B30, B37 to B38,
B45 to B46, a third decoder circuit 56, a first encoder circuit 57, a second encoder circuit 86,
Fourth decoder circuit 87 and third encoder circuit 88
And a fifth decoder circuit 88.

In this way, the interface circuit section 165
According to this, since the Strb_Tx signal and the Data_Tx signal are transmitted / received with a 2-bit width, data communication equivalent to S100 (100 Mbps) can be performed at an operating frequency of 50 MHz.

[0106]

As described above, according to the present invention, it is possible to use IEEE without using an analog circuit such as an operational amplifier.
It is possible to receive a digital signal of the 1394 standard and perform communication with an external device based on the received digital signal.

[Brief description of drawings]

FIG. 1 is an IEEE 13 as a first embodiment of the present invention.
It is a figure which shows the structure of the system using a 94 communication controller.

2 is a diagram showing the docking station of FIG. 1. FIG.

FIG. 3 is a diagram showing the personal computer of FIG. 1.

FIG. 4 is a diagram showing a part of a configuration of a personal computer and a docking station of FIG.

FIG. 5 is an IEEE 13 as a first embodiment of the present invention.
It is a figure which shows the structure of a 94 communication controller.

6 is a diagram showing a configuration of an interface circuit unit in FIG.

7 is a diagram showing a configuration of a second decoder circuit of FIG.

FIG. 8 is a diagram showing a configuration of a first decoder circuit of FIG.

FIG. 9 is an IEEE 13 as a second embodiment of the present invention.
It is a figure which shows the structure of the system using a 94 communication controller.

FIG. 10 is an IEEE1 as a second embodiment of the present invention.
It is a figure which shows the structure of a 394 communication controller.

11 is a diagram showing a configuration of an interface circuit unit in FIG.

12 is a diagram showing a configuration of a first encoder circuit of FIG.

13 is a diagram showing an example of a waveform of an output signal of the first encoder circuit of FIG.

14 is a diagram showing an example of a waveform of an output signal of the first encoder circuit of FIG.

FIG. 15 is a diagram showing an example of a waveform of an output signal of the first encoder circuit of FIG.

16 is a diagram showing an example of a waveform of an output signal of the first encoder circuit of FIG.

17 is a diagram showing the configuration of the third decoder circuit of FIG. 11. FIG.

FIG. 18 is an IEEE1 as a third embodiment of the present invention.
It is a figure which shows the structure of the system using the 394 communication controller.

FIG. 19 is an IEEE1 as a third embodiment of the present invention.
It is a figure which shows the structure of a 394 communication controller.

20 is a diagram showing a configuration of an interface circuit unit in FIG.

21 is a diagram showing a configuration of a second encoder circuit of FIG. 20. FIG.

22 is a diagram showing a configuration of a fifth decoder circuit of FIG. 20. FIG.

FIG. 23 is a diagram showing a configuration of a third encoder circuit of FIG. 20.

24 is a diagram showing a configuration of a fourth decoder circuit of FIG. 20. FIG.

FIG. 25 is an IEEE1 as a fourth embodiment of the present invention.
It is a figure which shows the structure of the system using the 394 communication controller.

FIG. 26 is an IEEE1 as a fourth embodiment of the present invention.
It is a figure which shows the structure of a 394 communication controller.

27 is a diagram showing a configuration of an interface circuit unit in FIG. 26.

FIG. 28 is an IEEE1 as a fifth embodiment of the present invention.
It is a figure which shows the structure of the system using the 394 communication controller.

FIG. 29 is an IEEE1 as a fifth embodiment of the present invention.
It is a figure which shows the structure of a 394 communication controller.

FIG. 30 is a diagram showing a configuration of an interface circuit unit of FIG. 29.

FIG. 31 is a diagram showing a configuration of a system using a conventional IEEE 1394 communication controller.

32 is a diagram showing a part of the configuration of the personal computer and the digital video camera of FIG. 31.

33 is a diagram showing a configuration of the IEEE 1394 communication controller of FIG. 32.

34 is a diagram showing a configuration of a port interface circuit unit of FIG. 33.

35 is a diagram showing the structure of the terminating resistor circuit of FIG. 32.

36 is a diagram showing the structure of the terminating resistor circuit of FIG. 32.

FIG. 37 is a diagram showing a configuration of a system using a conventional IEEE 1394 communication controller.

[Explanation of symbols]

1, 51, 81, 151, 161, 170 Personal computer 2, 52, 82, 152, 162, 175 Docking station 3, 53, 83, 153, 163, 172 IEEE1
394 communication controller 4, 84, 154, 164, 190 logical operation section 5, 55, 85, 155, 165 interface circuit section 6, 65, 112, 118, 128 inverter 7 first decoder circuit 8 second decoder circuit 11 ~ 24, 27, 28, 31-44, 47, 48, 9
1-94, 101-104, 231-262, 271-
302 electrodes 45, 46, 122 NAND gate circuit 56 third decoder circuit 57 first encoder circuit 58-61, 66-75, 114-116, 130 D
Type flip-flops 62, 63, 77, 111, 119, 120, 125,
127 AND gate circuits 64, 76, 78, 79, 113, 121, 124, 1
26, 129 OR gate circuit 86 Second encoder circuit 87 Fourth decoder circuit 88 Third encoder circuit 89 Fifth decoder circuit 117 EXNOR gate circuit 123 NOR gate circuit 170 Digital video camera 173, 174 Termination resistance circuit 180 Cable 181, 182 wiring pairs 183, 184, 186 to 188, 210, 211, 2
17, 218 resistors 185, 189 capacitors 191 port interface units 201, 219, 220 constant current sources 202 to 209, 212 to 216 operational amplifiers B1 to B11, B21 to B52 buffers

Claims (6)

[Claims] 1. An interface circuit for communicating with an external device based on a digital signal received from a digital signal processing circuit, which receives a plurality of digital signals according to the IEEE 1394 standard from the digital signal processing circuit or An interface circuit which outputs to a digital signal processing circuit and transmits / receives a digital signal to / from the external device. 2. A first circuit that outputs a high-level Connect_detect signal to the digital signal processing circuit; an inverter that receives a TpBias_disable signal from the digital signal processing circuit, inverts the signal, and transmits the inverted signal to the external device; A first buffer that receives a Strb_Tx signal from a signal processing circuit and sends it to the external device; a second buffer that receives a Strb_Enable signal from the digital signal processing circuit and sends it to the external device; and a digital signal processing circuit from the digital signal processing circuit. A third buffer that receives a Data_Tx signal and sends it to the external device, a fourth buffer that receives a Data_Enable signal from the digital signal processing circuit and sends it to the external device, and a Speed_Tx (1: 0) fifth and sixth buffers for receiving signals and transmitting them to the external device; A seventh buffer that receives a Data_Tx signal from an external device and outputs it as a Data_Rx signal to the digital signal processing circuit, and a Speed_Tx (1: 0) signal from the external device,
Eighth and ninth buffers that output to the digital signal processing circuit as x (1: 0) signals, and a tenth buffer that receives a Strb_Tx signal from the external device and outputs to the digital signal processing circuit as a Strb_Rx signal. A buffer, an eleventh buffer that receives a signal obtained by inverting the TpBias_disable signal from the external device, and outputs the signal as a Bias_Detect signal to the digital signal processing circuit, and a signal that is received by receiving a Data_Tx signal and a Data_Enable signal from the external device. A second circuit for generating an Arb_A_Rx (1: 0) signal based on the received signal and outputting the digital signal processing circuit to the digital signal processing circuit, and a Strb_Tx signal and a Strb_Enable signal from the external device. 0) signal is generated and is output to the digital signal processing circuit. A third circuit, the interface circuit according to claim 1. 3. A first circuit that outputs a high-level Connect_detect signal to the digital signal processing circuit; a first buffer that receives a Strb_Tx signal from the digital signal processing circuit and transmits the Strb_Tx signal to the external device; A second buffer for receiving a Strb_Enable signal from the signal processing circuit and transmitting it to the external device, a third buffer for receiving a Data_Tx signal from the digital signal processing circuit and transmitting it to the external device, and a digital signal processing circuit A fourth buffer that receives a Data_Enable signal and sends it to the external device; a fifth buffer that receives a Data_Tx signal from the external device and outputs it as a Data_Rx signal to the digital signal processing circuit; and a Strb_Tx signal from the external device. And a sixth buffer for receiving the Strb_Rx signal and outputting it to the digital signal processing circuit as a Strb_Rx signal. A second circuit that receives a Data_Tx signal and a Data_Enable signal from the external device, generates an Arb_A_Rx (1: 0) signal based on these signals, and outputs the signal to the digital signal processing circuit; and a Strb_Tx signal from the external device. A signal and a Strb_Enable signal are received, an Arb_B_Rx (1: 0) signal is generated based on these signals, and a third circuit that outputs the signal to the digital signal processing circuit, and a TpBias_disable signal and Speed_Tx (from the digital signal processing circuit 1: 0) signal is received, converted into a serial signal, and transmitted to the external device, and a TpBias_disable signal and Speed_Tx from the external device.
A fifth circuit which receives a signal obtained by converting the (1: 0) signal into a serial signal, generates an Arb_B_Rx (1: 0) signal based on the received signal, and outputs the signal to the digital signal processing circuit. The interface circuit according to claim 1, wherein 4. A first circuit that outputs a high-level Connect_detect signal to the digital signal processing circuit, and an N-bit width (N:
A first buffer group including N buffers for receiving a Strb_Tx signal of 2 or more) and transmitting the Strb_Tx signal to the external device; and a Data_T having an N-bit width from the digital signal processing circuit.
a second buffer group including N buffers for receiving an x signal and transmitting it to the external device; and a Data_Tx signal having an N-bit width from the external device, and the digital signal processing as a Data_Rx signal having an N-bit width. A third buffer group including N buffers to be output to the circuit, and N number of N-bit width Strb_Tx signals received from the external device and output to the digital signal processing circuit as N-bit width Strb_Rx signals. A fourth buffer group including a buffer; a second circuit which receives the TpBias_disable signal and the Speed_Tx (1: 0) signal from the digital signal processing circuit, converts the signal into a serial signal, and transmits the serial signal to the external device; Strb_Tx signal, Strb_En from processing circuit
A third signal that receives a signal that becomes a high level when transmitting an able signal and an arbitration signal and that becomes a low level when transmitting data synchronized with a clock signal, converts the signal into a serial signal, and transmits the serial signal to the external device. Circuit, and Data_Tx signal, Data_En from the digital signal processing circuit
A fourth signal that receives a signal that becomes a high level when transmitting an able signal and an arbitration signal and that becomes a low level when transmitting data synchronized with a clock signal, converts the signal into a serial signal, and transmits the serial signal to the external device. A signal obtained by converting a signal that becomes a high level when transmitting a Data_Tx signal, a Data_Enable signal, and an arbitration signal from the external device and a low level when transmitting data synchronized with a clock signal into a serial signal. From the digital signal processing circuit and receives the Strb_Tx signal and Strb_Tx signal.
Receive Enable signal and based on the received signal Arb_
A fifth circuit that generates an A_Rx (1: 0) signal and outputs it to the digital signal processing circuit, and a high level when the Strb_Tx signal, the Strb_Enable signal, and the arbitration signal are transmitted from the external device Receives a signal obtained by converting a signal that becomes a low level into a serial signal when transmitting data synchronized with the signal, and outputs the Data_Tx signal and the Data_Tx signal from the digital signal processing circuit.
Receive Enable signal and based on the received signal Arb_
A sixth circuit for generating a B_Rx (1: 0) signal and outputting it to the digital signal processing circuit, the interface circuit according to claim 1. 5. A semiconductor device comprising the interface circuit according to claim 1. Description: 6. The semiconductor device according to claim 5, further comprising the digital signal processing circuit.