TW201617913A - Multi-part apparatus, connecting apparatus and connection detection method thereof - Google Patents

Multi-part apparatus, connecting apparatus and connection detection method thereof Download PDF

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TW201617913A
TW201617913A TW103138899A TW103138899A TW201617913A TW 201617913 A TW201617913 A TW 201617913A TW 103138899 A TW103138899 A TW 103138899A TW 103138899 A TW103138899 A TW 103138899A TW 201617913 A TW201617913 A TW 201617913A
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pin
common
coupled
clock
pins
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TW103138899A
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Chinese (zh)
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羅濟瑄
呂紹正
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宏碁股份有限公司
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Abstract

A multi-part apparatus, a connecting apparatus and a connection detection method thereof are provided. The connecting apparatus includes a connecting interface and a control unit. The connecting interface includes a first common pin and a second common pin, which are symmetrically configured to a central axis of the connecting interface. One of the first and second common pins is coupled to a clock pin of an electronic apparatus, and the other one of the first and second common pins is coupled to a data pin of the electronic apparatus. The control unit is coupled to the first and second common pins. According to a voltage change on the first and second common pins, the control unit determines whether the first common pin is coupled to the clock pin or the data pin, and determines whether the second common pin is coupled to the clock pin or the data pin.

Description

複合裝置、連接裝置及其連接偵測方法 Composite device, connection device and connection detection method thereof

本發明是有關於一種連接技術,且特別是有關於一種可提供電子裝置以正面或反面連接的複合裝置、連接裝置及其連接偵測方法。 The present invention relates to a connection technology, and more particularly to a composite device, a connection device, and a connection detection method thereof that can provide an electronic device connected to the front or the back.

隨著科技的快速發展,筆記型電腦、平板電腦、智慧型手機等電子裝置也隨之問世。電子裝置除了可提供使用者即時處理及收發資料之外,還可藉由搭配連接裝置(例如基座(Dock))來擴充電子裝置的功能,從而提升電子裝置的操作便利性。 With the rapid development of technology, electronic devices such as notebook computers, tablet computers, and smart phones have also come out. In addition to providing the user with instant processing and transceiving data, the electronic device can also expand the function of the electronic device by collocation with a connecting device (such as a dock), thereby improving the operational convenience of the electronic device.

例如,圖1A至圖1C是一種電子組件的示意圖。請參照圖1A,電子組件10包括連接裝置12及電子裝置14。當電子裝置14組裝於連接裝置12時,連接埠122、142相連以進行電源傳輸或資料傳輸。依照組裝方向的不同,電子裝置14的顯示面144可朝向(如圖1A)或背向連接裝置12的輸入介面126,以下分別以『正面』及『反面』連接來表示。 For example, Figures 1A-1C are schematic illustrations of an electronic component. Referring to FIG. 1A, the electronic component 10 includes a connecting device 12 and an electronic device 14. When the electronic device 14 is assembled to the connection device 12, the ports 122, 142 are connected for power transmission or data transmission. Depending on the direction of assembly, the display surface 144 of the electronic device 14 can be oriented (as in FIG. 1A) or back to the input interface 126 of the connection device 12, hereinafter referred to as "front" and "reverse" connections, respectively.

圖1B與圖1C分別繪示電子裝置14以正面及反面連接至連接裝置12的情形。以連接埠122、142為內部整合電路(Inter-Integrated Circuit,I2C)匯流排介面為例,連接埠142的接腳組由左至右地配置接地接腳GND3、電源接腳PWR3、偵測接腳DET3、時脈接腳CLK3、資料接腳DAT3及中斷接腳INT3,且連接埠122可由中心分別向兩側依序地配置中斷接腳INT、資料接腳DAT1、DAT2、時脈接腳CLK1、CLK2、偵測接腳DET1、DET2、電源接腳PWR1、電源接腳PWR2及接地接腳GND1、GND2。其中時脈接腳CLK1、CLK2分別連接至嵌入式控制器124的時脈接腳CLK以傳輸時脈訊號,且資料接腳DAT1、DAT2分別連接至嵌入式控制器124的資料接腳DAT以傳輸資料訊號。 FIG. 1B and FIG. 1C respectively illustrate the case where the electronic device 14 is connected to the connecting device 12 in front and back. Taking the ports 122 and 142 as the bus interface of the Inter-Integrated Circuit (I2C) as an example, the pin group of the port 142 is configured with the ground pin GND3, the power pin PWR3, and the detection terminal from left to right. The foot DET3, the clock pin CLK3, the data pin DAT3 and the interrupt pin INT3, and the port 122 can be sequentially arranged from the center to the two sides, respectively, the interrupt pin INT, the data pin DAT1, DAT2, the clock pin CLK1 CLK2, detection pin DET1, DET2, power pin PWR1, power pin PWR2, and ground pins GND1, GND2. The clock pins CLK1 and CLK2 are respectively connected to the clock pin CLK of the embedded controller 124 to transmit the clock signal, and the data pins DAT1 and DAT2 are respectively connected to the data pin DAT of the embedded controller 124 for transmission. Information signal.

換言之,目前的技術必須將連接埠122中的接腳成對配置,且相當於配置兩組連接埠142的接腳組,才可讓電子裝置14實現如圖1B的正面連接及圖1C的反面連接。然而,上述作法將因接腳數量的限制而導致製作成本高昂。 In other words, the current technology must configure the pins in the port 122 in pairs, and is equivalent to the pin group configuring the two sets of ports 142, so that the electronic device 14 can realize the front connection of FIG. 1B and the reverse side of FIG. 1C. connection. However, the above practice will result in high manufacturing costs due to the limitation of the number of pins.

有鑑於此,本發明提供一種複合裝置、連接裝置及其連接偵測方法,可使電子裝置以雙面進行連接並有效減少接腳數量。 In view of this, the present invention provides a composite device, a connection device, and a connection detecting method thereof, which can connect the electronic device on both sides and effectively reduce the number of pins.

本發明提出一種連接裝置。所述連接裝置包括連接介面以及控制單元。連接介面包括第一及第二共同接腳,其對稱於連接介面的中心軸線以進行配置。其中,第一及第二共同接腳的其 中之一耦接電子裝置的時脈接腳,第一及第二共同接腳的其中之另一耦接電子裝置的資料接腳。控制單元耦接至第一及第二共同接腳。控制單元依據第一及第二共同接腳上的電壓變化以判斷第一共同接腳耦接至時脈接腳或資料接腳,以及判斷第二共同接腳耦接至時脈接腳或資料接腳。 The invention proposes a connecting device. The connecting device includes a connection interface and a control unit. The connection interface includes first and second common pins that are symmetric with respect to a central axis of the connection interface for configuration. Wherein the first and second common pins are One of the first and second common pins is coupled to the data pin of the electronic device. The control unit is coupled to the first and second common pins. The control unit determines that the first common pin is coupled to the clock pin or the data pin according to the voltage change on the first and second common pins, and determines that the second common pin is coupled to the clock pin or the data Pin.

本發明另提出一種連接裝置的連接偵測方法。所述連接偵測方法包括下列步驟。提供第一及第二共同接腳對稱於連接介面的中心軸線以進行配置。其中,第一及第二共同接腳的其中之一耦接電子裝置的時脈接腳,第一及第二共同接腳的其中之另一耦接電子裝置的資料接腳。依據第一及第二共同接腳上的電壓變化以判斷第一共同接腳耦接至時脈接腳或資料接腳,以及判斷第二共同接腳耦接至時脈接腳或資料接腳。 The invention further provides a connection detection method for a connection device. The connection detection method includes the following steps. The first and second common pins are provided symmetrically about a central axis of the connection interface for configuration. The one of the first and second common pins is coupled to the clock pin of the electronic device, and the other of the first and second common pins is coupled to the data pin of the electronic device. Determining that the first common pin is coupled to the clock pin or the data pin according to the voltage change on the first and second common pins, and determining that the second common pin is coupled to the clock pin or the data pin .

本發明另提出一種複合裝置。所述複合裝置包括電子裝置以及連接裝置。電子裝置包括第一控制單元以及第一連接介面。第一連接介面包括第一時脈接腳及第一資料接腳,其分別耦接至第一控制單元。連接裝置包括第二連接介面以及第二控制單元。第二連接介面包括第一及第二共同接腳,其對稱於第二連接介面的中心軸線以進行配置。其中,第一及第二共同接腳的其中之一耦接第一時脈接腳,第一及第二共同接腳的其中之另一耦接第一資料接腳。第二控制單元耦接至第一及第二共同接腳。第二控制單元依據第一及第二共同接腳上的電壓變化以判斷第一共同接腳耦接至第一時脈接腳或第一資料接腳,以及判斷第二共同接 腳耦接至第一時脈接腳或第一資料接腳。 The invention further provides a composite device. The composite device includes an electronic device and a connection device. The electronic device includes a first control unit and a first connection interface. The first connection interface includes a first clock pin and a first data pin, which are respectively coupled to the first control unit. The connecting device includes a second connection interface and a second control unit. The second connection interface includes first and second common pins that are symmetric with respect to a central axis of the second connection interface for configuration. The one of the first and second common pins is coupled to the first clock pin, and the other of the first and second common pins is coupled to the first data pin. The second control unit is coupled to the first and second common pins. The second control unit determines that the first common pin is coupled to the first clock pin or the first data pin according to the voltage change on the first and second common pins, and determines the second common connection The pin is coupled to the first clock pin or the first data pin.

基於上述,本發明實施例所提出的複合裝置、連接裝置及其連接偵測方法使用連接裝置其連接介面上的兩個共同接腳來傳輸時脈訊號及資料訊號,並依據共同接腳上的電壓變化來判斷電子裝置是以正面或反面連接至連接裝置。藉此,可以實現連接裝置和電子裝置之間的雙面連接的功能,並且有效地減少接腳數量以降低製作成本。 Based on the above, the composite device, the connection device and the connection detection method thereof according to the embodiments of the present invention use the two common pins on the connection interface of the connection device to transmit the clock signal and the data signal, and according to the common pin The voltage change determines whether the electronic device is connected to the connection device in front or back. Thereby, the function of the double-sided connection between the connection device and the electronic device can be realized, and the number of pins can be effectively reduced to reduce the manufacturing cost.

為讓本發明的上述特徵和優點能更明顯易懂,下文特舉實施例,並配合所附圖式作詳細說明如下。 The above described features and advantages of the invention will be apparent from the following description.

10‧‧‧電子組件 10‧‧‧Electronic components

GND‧‧‧接地電壓 GND‧‧‧ Grounding voltage

12、21‧‧‧連接裝置 12, 21‧‧‧Connecting device

GPA0、GPA1‧‧‧控制訊號 GPA0, GPA1‧‧‧ control signals

122、142‧‧‧連接埠 122, 142‧‧‧ Connections

L‧‧‧中心軸線 L‧‧‧ center axis

124‧‧‧嵌入式控制器 124‧‧‧ embedded controller

M1~M4‧‧‧電晶體 M1~M4‧‧‧O crystal

126‧‧‧輸入介面 126‧‧‧Input interface

R1~R8‧‧‧電阻 R1~R8‧‧‧ resistance

14、25‧‧‧電子裝置 14, 25‧‧‧ Electronic devices

VDD‧‧‧電源電壓 VDD‧‧‧Power supply voltage

144‧‧‧顯示面 144‧‧‧ display surface

S402~S404‧‧‧步驟 S402~S404‧‧‧Steps

20‧‧‧複合裝置 20‧‧‧Composite device

COM1、COM2‧‧‧共同接腳 COM1, COM2‧‧‧ common feet

22、26‧‧‧連接介面 22, 26‧‧‧ Connection interface

DET1~DET3‧‧‧偵測接腳 DET1~DET3‧‧‧Detection pin

23‧‧‧切換電路 23‧‧‧Switching circuit

GND1~GND3‧‧‧接地接腳 GND1~GND3‧‧‧ Grounding Pin

24、27‧‧‧控制單元 24, 27‧‧‧Control unit

PWR1~PWR3‧‧‧電源接腳 PWR1~PWR3‧‧‧ power pin

CLK、CLK1~CLK3、DCK、PCK‧‧‧時脈接腳 CLK, CLK1~CLK3, DCK, PCK‧‧‧ clock pin

DAT、DAT1~DAT3、DDA、PDA‧‧‧資料接腳 DAT, DAT1~DAT3, DDA, PDA‧‧‧ data pin

INT、INT3、DINT、PINT‧‧‧中斷接腳 INT, INT3, DINT, PINT‧‧‧ interrupt pins

圖1A至圖1C是一種電子組件的示意圖。 1A to 1C are schematic views of an electronic component.

圖2A與圖2B是依照本發明一實施例所繪示的複合裝置的方塊圖。 2A and 2B are block diagrams of a composite device according to an embodiment of the invention.

圖3是依照本發明一實施例所繪示的複合裝置的方塊圖。 3 is a block diagram of a composite device in accordance with an embodiment of the invention.

圖4是依照本發明一實施例所繪示的連接裝置的連接偵測方法的流程圖。 FIG. 4 is a flow chart of a method for detecting connection of a connection device according to an embodiment of the invention.

本發明實施例的複合裝置、連接裝置及其連接偵測方法使用連接裝置的兩個共同接腳來進行時脈訊號及資料訊號的傳 輸,並藉由共同接腳上的電壓變化來偵測電子裝置是以正面或背面連接至連接裝置,可以有效減少接腳數量,並實現連接裝置和電子裝置之間的雙面連接功能。此外,還可藉由共同接腳來進行連接裝置與電子裝置之間的介面認證程序及其相關設定,以利用內部整合電路協定的通訊功能來提升連接裝置的擴充性。 The composite device, the connecting device and the connection detecting method thereof according to the embodiments of the present invention use two common pins of the connecting device to transmit the clock signal and the data signal By inputting and detecting the electronic device by the voltage change on the common pin, the electronic device is connected to the connecting device on the front or the back, which can effectively reduce the number of pins and realize the double-sided connection function between the connecting device and the electronic device. In addition, the interface authentication procedure between the connection device and the electronic device and related settings can be performed by a common pin to enhance the expandability of the connection device by utilizing the communication function of the internal integrated circuit protocol.

圖2A與圖2B是依照本發明一實施例所繪示的複合裝置的方塊圖。請先參照圖2A,本實施例的複合裝置20包括電子裝置25及連接裝置21。電子裝置25例如是平板電腦、智慧型手機等可攜式電子裝置,連接裝置21例如是基座、鍵盤等具有連接介面的裝置,在此不限制其種類。電子裝置25包括連接介面26及控制單元27。連接裝置21包括連接介面22及控制單元24。連接介面26、22例如是內部整合電路匯流排。控制單元27、24例如是嵌入式控制器、微處理器等具有處理能力的裝置或元件。 2A and 2B are block diagrams of a composite device according to an embodiment of the invention. Referring first to FIG. 2A, the composite device 20 of the present embodiment includes an electronic device 25 and a connection device 21. The electronic device 25 is, for example, a portable electronic device such as a tablet computer or a smart phone. The connection device 21 is, for example, a device having a connection interface such as a cradle or a keyboard, and the type thereof is not limited thereto. The electronic device 25 includes a connection interface 26 and a control unit 27. The connection device 21 includes a connection interface 22 and a control unit 24. The connection interfaces 26, 22 are, for example, internal integrated circuit bus bars. The control units 27, 24 are, for example, devices or components having processing capabilities such as embedded controllers, microprocessors, and the like.

在本實施例中,連接介面22可包括共同接腳COM1、COM2,其對稱於連接介面22的中心軸線L以進行配置。其中,共同接腳COM1、COM2的其中之一可耦接電子裝置25的時脈接腳CLK3,且共同接腳COM1、COM2的其中之另一可耦接電子裝置25的資料接腳DAT3。 In the present embodiment, the connection interface 22 may include common pins COM1, COM2 that are symmetric with respect to the central axis L of the connection interface 22 for configuration. The one of the common pins COM1 and COM2 can be coupled to the clock pin CLK3 of the electronic device 25, and the other of the common pins COM1 and COM2 can be coupled to the data pin DAT3 of the electronic device 25.

具體而言,連接介面22中可由左至右依序地配置接地接腳GND1、電源接腳PWR1、共同接腳COM1、中斷接腳INT、共同接腳COM2、電源接腳PWR2及接地接腳GND2。其中,中斷接腳INT配置於共同接腳COM1、COM2之間,並位於連接介面 22的中心軸線L上。電源接腳PWR1、PWR2對稱配置於中心軸線L且分別耦接至電源電壓VDD。接地接腳GND1、GND2對稱配置於中心軸線L且分別耦接至接地電壓GND。 Specifically, the grounding pin GND1, the power pin PWR1, the common pin COM1, the interrupt pin INT, the common pin COM2, the power pin PWR2, and the ground pin GND2 may be sequentially arranged from left to right in the connection interface 22. . The interrupt pin INT is disposed between the common pins COM1 and COM2 and is located at the connection interface. 22 is on the central axis L. The power pins PWR1 and PWR2 are symmetrically disposed on the central axis L and coupled to the power supply voltage VDD, respectively. The ground pins GND1 and GND2 are symmetrically disposed on the central axis L and coupled to the ground voltage GND, respectively.

另一方面,電子裝置25的連接介面26中則可由左至右依序地配置接地接腳GND3、電源接腳PWR3、時脈接腳CLK3、中斷接腳INT3及資料接腳DAT3。藉此,電子裝置25與連接裝置21中相對應的各個接腳便可以圖2A或圖2B的連接方式而互相接觸,從而實現正面或反面連接的功能。 On the other hand, in the connection interface 26 of the electronic device 25, the ground pin GND3, the power pin PWR3, the clock pin CLK3, the interrupt pin INT3, and the data pin DAT3 can be sequentially arranged from left to right. Thereby, the respective pins of the electronic device 25 and the connecting device 21 can be brought into contact with each other by the connection manner of FIG. 2A or FIG. 2B, thereby realizing the function of front or back connection.

控制單元27耦接至時脈接腳CLK3及資料接腳DAT3,且控制單元24耦接至共同接腳COM1、COM2。其中,控制單元24依據共同接腳COM1、COM2上的電壓變化以判斷共同接腳COM1耦接至時脈接腳CLK3或資料接腳DAT3,以及判斷共同接腳COM2耦接至時脈接腳CLK3或資料接腳DAT3。 The control unit 27 is coupled to the clock pin CLK3 and the data pin DAT3, and the control unit 24 is coupled to the common pins COM1 and COM2. The control unit 24 determines that the common pin COM1 is coupled to the clock pin CLK3 or the data pin DAT3 according to the voltage change on the common pins COM1 and COM2, and determines that the common pin COM2 is coupled to the clock pin CLK3. Or data pin DAT3.

需說明的是,當電子裝置25如圖2A而正面連接至連接裝置21時,共同接腳COM1、COM2可分別耦接至時脈接腳CLK3及資料接腳DAT3。而當電子裝置25如圖2B而反面連接至連接裝置21時,共同接腳COM1、COM2則可分別耦接至資料接腳DAT3及CLK3。本發明對於上述正面或反面的連接方式不限制。 It should be noted that when the electronic device 25 is connected to the connecting device 21 as shown in FIG. 2A, the common pins COM1 and COM2 can be respectively coupled to the clock pin CLK3 and the data pin DAT3. When the electronic device 25 is connected to the connecting device 21 on the reverse side as shown in FIG. 2B, the common pins COM1 and COM2 are respectively coupled to the data pins DAT3 and CLK3. The present invention is not limited to the above-described front or back connection.

具體而言,在一實施例中,共同接腳COM1、COM2上的電壓準位可依據電子裝置25經由時脈接腳CLK3所發出的時脈訊號而變化。更明確地說,當共同接腳COM1上的電壓準位依據時脈訊號而變化時,控制單元24可判定共同接腳COM1耦接至時 脈接腳CLK3,且共同接腳COM2耦接至資料接腳DAT3。相對而言,當共同接腳COM2上的電壓準位依據時脈訊號而變化時,控制單元24則可判定共同接腳COM1耦接至資料接腳DAT3,且共同接腳COM2耦接至時脈接腳CLK3。 Specifically, in an embodiment, the voltage level on the common pins COM1 and COM2 can be changed according to the clock signal sent by the electronic device 25 via the clock pin CLK3. More specifically, when the voltage level on the common pin COM1 changes according to the clock signal, the control unit 24 can determine that the common pin COM1 is coupled to the time. The pin CLK3 is coupled to the data pin DAT3. In contrast, when the voltage level on the common pin COM2 changes according to the clock signal, the control unit 24 can determine that the common pin COM1 is coupled to the data pin DAT3, and the common pin COM2 is coupled to the clock. Pin CLK3.

例如,共同接腳COM1、COM2、時脈接腳CLK3及資料接腳DAT3的電壓準位可初始化為高電壓準位(致能準位)。當電子裝置25連接至連接裝置21並經由時脈接腳CLK3發出低電壓準位(禁能準位)的時脈訊號時,若電子裝置25以正面連接至連接裝置21(如圖2A),共同接腳COM1將接收時脈訊號且轉變成低電壓準位。而若電子裝置25以反面連接至連接裝置21(如圖2B),則由共同接腳COM2接收時脈訊號且轉變成低電壓準位。因此,透過共同接腳COM1、COM2上的電壓準位變化,可藉以判斷電子裝置25是以正面或背面連接至連接裝置21。 For example, the voltage levels of the common pins COM1, COM2, the clock pin CLK3, and the data pin DAT3 can be initialized to a high voltage level (enable level). When the electronic device 25 is connected to the connection device 21 and sends a low voltage level (disabling level) clock signal via the clock pin CLK3, if the electronic device 25 is connected to the connection device 21 on the front side (as shown in FIG. 2A), The common pin COM1 will receive the clock signal and convert to a low voltage level. If the electronic device 25 is connected to the connecting device 21 on the reverse side (as shown in FIG. 2B), the clock signal is received by the common pin COM2 and converted to a low voltage level. Therefore, by changing the voltage level on the common pins COM1 and COM2, it can be judged that the electronic device 25 is connected to the connection device 21 on the front or back side.

接著說明本實施例的詳細裝置架構。請參照圖3,圖3是依照本發明一實施例所繪示的複合裝置的方塊圖。在此以電子裝置25以正面連接至連接裝置21,並僅繪示連接介面22、26中的部份接腳以便於說明。其中,控制單元27透過時脈接腳PCK及資料接腳PDA分別連接時脈接腳CLK3及資料接腳DAT3,以分別傳輸時脈訊號和資料訊號。換句話說,時脈接腳PCK、CLK3的電路作動實質上相同,且資料接腳PDA、DAT3的電路作動實質上相同,故以下統一使用時脈接腳PCK及資料接腳PDA進行說明。 Next, the detailed device architecture of this embodiment will be described. Please refer to FIG. 3. FIG. 3 is a block diagram of a composite device according to an embodiment of the invention. Here, the electronic device 25 is connected to the connecting device 21 on the front side, and only a part of the connecting interfaces 22, 26 are shown for convenience of explanation. The control unit 27 connects the clock pin CLK3 and the data pin DAT3 through the clock pin PCK and the data pin PDA to respectively transmit the clock signal and the data signal. In other words, the circuit operations of the clock pins PCK and CLK3 are substantially the same, and the circuit operations of the data pins PDA and DAT3 are substantially the same. Therefore, the clock pin PCK and the data pin PDA are collectively described below.

連接裝置21可透過共同接腳COM1、COM2以分別與電 子裝置25的時脈接腳PCK及資料接腳PDA連接。而在連接裝置21內部,控制單元24所包括的時脈接腳DCK、資料接腳DDA及共同接腳COM1、COM2之間的耦接關係則可由切換電路23決定。 The connecting device 21 can communicate with the common pins COM1 and COM2 respectively The clock pin PCK of the sub-device 25 and the data pin PDA are connected. In the connection device 21, the coupling relationship between the clock pin DCK, the data pin DDA and the common pins COM1 and COM2 included in the control unit 24 can be determined by the switching circuit 23.

詳言之,在一實施例中,切換電路23耦接於共同接腳COM1、COM2及控制單元24之間,並可依據控制訊號GPA0、GPA1以建立第一傳輸路徑,藉以將共同接腳COM1耦接至控制單元24的時脈接腳DCK或資料接腳DDA,以及依據控制訊號GPA0、GPA1以建立第二傳輸路徑,藉以將共同接腳COM2耦接至控制單元24的時脈接腳DCK或資料接腳DDA。其中,控制單元24可依據共同接腳COM1、COM2上的電壓變化以決定控制訊號GPA0、GPA1的電壓準位,且控制訊號GPA0、GPA1互為反相。 In detail, in an embodiment, the switching circuit 23 is coupled between the common pins COM1, COM2 and the control unit 24, and can establish a first transmission path according to the control signals GPA0, GPA1, thereby sharing the common pin COM1. The clock pin DCK or the data pin DDA is coupled to the control unit 24, and the second transmission path is established according to the control signals GPA0, GPA1, thereby coupling the common pin COM2 to the clock pin DCK of the control unit 24. Or data pin DDA. The control unit 24 can determine the voltage levels of the control signals GPA0 and GPA1 according to the voltage changes on the common pins COM1 and COM2, and the control signals GPA0 and GPA1 are mutually inverted.

具體而言,本實施例的切換電路23包括電晶體M1~M4(例如NMOS電晶體)。電晶體M1~M2受控於控制訊號GPA0,且電晶體M3~M4受控於控制訊號GPA1。以低電壓準位的時脈訊號為例,當連接裝置21連接至電子裝置25且共同接腳COM1接收到時脈訊號而轉變成低電壓準位時,控制單元24可決定控制訊號GPA0為高電壓準位,且控制訊號GPA1為低電壓準位。此時,電晶體M1~M2導通且電晶體M3~M4斷開,使得共同接腳COM1透過第一傳輸路徑連接時脈接腳DCK,且共同接腳COM2透過第二傳輸路徑連接資料接腳DDA。 Specifically, the switching circuit 23 of the present embodiment includes transistors M1 to M4 (for example, NMOS transistors). The transistors M1~M2 are controlled by the control signal GPA0, and the transistors M3~M4 are controlled by the control signal GPA1. Taking the clock signal of the low voltage level as an example, when the connection device 21 is connected to the electronic device 25 and the common pin COM1 receives the clock signal and transitions to the low voltage level, the control unit 24 can determine that the control signal GPA0 is high. The voltage level is, and the control signal GPA1 is at a low voltage level. At this time, the transistors M1 to M2 are turned on and the transistors M3 to M4 are turned off, so that the common pin COM1 is connected to the clock pin DCK through the first transmission path, and the common pin COM2 is connected to the data pin DDA through the second transmission path. .

藉此,控制單元24可判斷電子裝置25是以正面或反面連接至連接裝置21,並進一步地透過切換電路23決定共同接腳 COM1、COM2及時脈接腳DCK、資料接腳DDA之間的傳輸路徑,使電子裝置25無論是以正面或反面與連接裝置21連接,電子裝置25的時脈接腳PCK及資料接腳PDA皆可分別連接至連接裝置21的時脈接腳DCK及資料接腳DDA。 Thereby, the control unit 24 can determine that the electronic device 25 is connected to the connecting device 21 on the front or the back, and further determines the common pin through the switching circuit 23. COM1, COM2, the transmission path between the DCK and the data pin DDA, so that the electronic device 25 is connected to the connection device 21 on the front or the back, and the clock pin PCK and the data pin PDA of the electronic device 25 are both The clock pin DCK and the data pin DDA of the connection device 21 can be respectively connected.

需說明的是,切換電路23還可藉由將控制訊號GPA0反相以產生控制訊號GPA1,或亦可使用PMOS電晶體作為電晶體M3~M4並僅以控制訊號GPA0來控制電晶體M1~M4來實現。 It should be noted that the switching circuit 23 can also generate the control signal GPA1 by inverting the control signal GPA0, or can also use the PMOS transistor as the transistors M3~M4 and control the transistors M1~M4 only by the control signal GPA0. to realise.

特別的是,在一實施例中,連接裝置21可初始設定為上電(Power On)狀態。此時,連接裝置21的共同接腳6OM1、COM2、時脈接腳DCK及資料接腳DDA未與電子裝置25連接,且分別透過電阻R1~R4接收電源電壓VDD而被抬升至高電壓準位。 In particular, in an embodiment, the connection device 21 can be initially set to a Power On state. At this time, the common pins 6OM1, COM2, the clock pin DCK and the data pin DDA of the connection device 21 are not connected to the electronic device 25, and are respectively received by the resistors R1 to R4 to receive the power supply voltage VDD and are raised to a high voltage level.

而考慮裝置內部各元件的操作時序可能不易控制,在一實施例中,電子裝置25的控制單元27可在判斷連接裝置21連接至電子裝置25之後,才提供電源電壓VDD至時脈接腳DCK及資料接腳DDA。具體而言,在一實施例中,電子裝置25可透過中斷接腳INT3以偵測是否連接連接介面22以產生偵測訊號。當控制單元27依據偵測訊號判斷與連接介面22連接時,控制單元27可提供電源電壓VDD以初始化共同接腳COM1、COM2的電壓準位。 Considering that the operation timing of each component inside the device may be difficult to control, in an embodiment, the control unit 27 of the electronic device 25 may provide the power supply voltage VDD to the clock pin DCK after determining that the connection device 21 is connected to the electronic device 25. And data pin DDA. Specifically, in an embodiment, the electronic device 25 can detect whether the connection interface 22 is connected to generate a detection signal through the interrupt pin INT3. When the control unit 27 determines to connect to the connection interface 22 according to the detection signal, the control unit 27 can supply the power supply voltage VDD to initialize the voltage levels of the common pins COM1 and COM2.

如圖3所示,連接裝置21的中斷接腳INT可透過電阻R8耦接至接地電壓GND,且控制單元24透過中斷接腳DINT而獲得中斷接腳INT上的電壓準位。另外,電子裝置25的中斷接腳INT3可透過電阻R7耦接至電源電壓VDD,且控制單元27透過 中斷接腳PINT而獲得中斷接腳INT3上的電壓準位。 As shown in FIG. 3, the interrupt pin INT of the connection device 21 can be coupled to the ground voltage GND through the resistor R8, and the control unit 24 obtains the voltage level on the interrupt pin INT through the interrupt pin DINT. In addition, the interrupt pin INT3 of the electronic device 25 can be coupled to the power supply voltage VDD through the resistor R7, and the control unit 27 transmits The voltage pin on the interrupt pin INT3 is obtained by interrupting the pin PINT.

基於上述架構,若中斷接腳INT、INT3未相連,則中斷接腳INT3將被抬升至電源電壓VDD。而當中斷接腳INT、INT3相連時,中斷接腳INT3上的電壓準位將被拉低至接地電壓GND。換言之,控制單元27可將中斷接腳INT3上的電壓準位作為偵測訊號,並依據中斷接腳INT3或中斷接腳PINT上的電壓準位是否被拉低來判斷是否與連接介面22連接。 Based on the above architecture, if the interrupt pins INT and INT3 are not connected, the interrupt pin INT3 will be raised to the power supply voltage VDD. When the interrupt pins INT and INT3 are connected, the voltage level on the interrupt pin INT3 will be pulled down to the ground voltage GND. In other words, the control unit 27 can use the voltage level on the interrupt pin INT3 as the detection signal, and determine whether to connect with the connection interface 22 according to whether the voltage level on the interrupt pin INT3 or the interrupt pin PINT is pulled low.

藉此,控制單元27可在判定連接裝置21與電子裝置25連接之後,才對連接裝置21提供電源電壓VDD,以分別透過電阻R1~R4將共同接腳COM1、COM2、時脈接腳DCK及資料接腳DDA初始化為高電壓準位,從而完成連接裝置21的初始設定。 Therefore, the control unit 27 can supply the power supply voltage VDD to the connection device 21 after determining that the connection device 21 is connected to the electronic device 25, so as to respectively transmit the common pins COM1, COM2, the clock pin DCK through the resistors R1 R R4 and The data pin DDA is initialized to a high voltage level, thereby completing the initial setting of the connection device 21.

至於電子裝置25的初始設定,時脈接腳PCK可透過電阻R5被拉低為接地電壓GND,且資料接腳PDA可透過電阻R6被抬升至電源電壓VDD。因此,當電子裝置25連接至連接裝置21時,共同接腳COM1、COM2上的高電壓準位將使時脈接腳PCK被抬升至高電壓準位。換言之,電子裝置25也可依據時脈接腳PCK上的電壓變化以判斷是否連接至連接裝置21。 As for the initial setting of the electronic device 25, the clock pin PCK can be pulled down to the ground voltage GND through the resistor R5, and the data pin PDA can be raised to the power supply voltage VDD through the resistor R6. Therefore, when the electronic device 25 is connected to the connection device 21, the high voltage level on the common pins COM1, COM2 will cause the clock pin PCK to be raised to a high voltage level. In other words, the electronic device 25 can also determine whether to connect to the connection device 21 according to the voltage change on the clock pin PCK.

基於上述,下表一列出連接裝置21在『初始狀態1』(未上電且未與電子裝置25連接)、『初始狀態2』(未上電且與電子裝置25連接)、『初始狀態3』(上電且連接至電子裝置25)的情況下,時脈接腳PCK、DCK、資料接腳PDA、DDA、中斷接腳PINT及控制訊號GPA0、GPA1其個別的電壓準位。其中,『1』代表高 電壓準位,『0』代表低電壓準位,『X』代表浮動值。 Based on the above, the following table 1 lists the connection device 21 in "initial state 1" (unpowered and not connected to the electronic device 25), "initial state 2" (unpowered and connected to the electronic device 25), "initial state" 3 (in the case of power-on and connection to the electronic device 25), the individual voltage levels of the clock pin PCK, DCK, data pin PDA, DDA, interrupt pin PINT and control signals GPA0, GPA1. Among them, "1" stands for high The voltage level, "0" represents the low voltage level, and "X" represents the floating value.

值得一提的是,在一實施例中,當連接裝置21連接電子裝置25之後,控制單元27還可藉由連接裝置21的共同接腳COM1、COM2來執行介面認證程序,以透過交握(Handshaking)過程來對時脈接腳PCK、DCK及資料接腳PDA、DDA進行認證,並將上述接腳設定為內部整合電路介面以進行通訊。 It is worth mentioning that, in an embodiment, after the connection device 21 is connected to the electronic device 25, the control unit 27 can also perform an interface authentication procedure by using the common pins COM1, COM2 of the connection device 21 to pass the handshake ( The Handshaking process authenticates the clock pins PCK, DCK and data pins PDA, DDA, and sets the pins as internal integrated circuit interfaces for communication.

以下搭配圖3說明介面認證程序的流程。首先,當電子裝置25與連接裝置21連接時,時脈接腳PCK、DCK及資料接腳PDA、DDA可初始化為高電壓準位,且控制單元27可使控制單元24分別將控制訊號GPA0、GPA1設定為高電壓準位及低電壓準位,以使時脈接腳DCK透過共同接腳COM1耦接時脈接腳PCK,且資料接腳PDA透過共同接腳COM2耦接資料接腳DDA。 The following describes the flow of the interface authentication program with Figure 3. First, when the electronic device 25 is connected to the connection device 21, the clock pins PCK, DCK and the data pins PDA, DDA can be initialized to a high voltage level, and the control unit 27 can cause the control unit 24 to respectively control the control signal GPA0, The GPA1 is set to the high voltage level and the low voltage level, so that the clock pin DCK is coupled to the clock pin PCK through the common pin COM1, and the data pin PDA is coupled to the data pin DDA through the common pin COM2.

接著,電子裝置25可將時脈接腳PCK下拉為低電壓準位。此低電壓準位的訊號可視為介面認證程序的第一請求訊號,換言之,電子裝置25可透過時脈接腳PCK傳送第一請求訊號至連接裝置21的時脈接腳DCK,使時脈接腳DCK接收第一請求訊號的低電壓準位,並使連接裝置21反應於第一請求訊號以調整資 料接腳DDA上的電壓準位為低電壓準位,並使電子裝置25的資料接腳PDA接收到低電壓準位。上述低電壓準位的訊號可視為第二請求訊號,亦即,連接裝置21可透過資料接腳PDA傳送第二請求訊號至電子裝置25的資料接腳PDA。 Next, the electronic device 25 can pull down the clock pin PCK to a low voltage level. The signal of the low voltage level can be regarded as the first request signal of the interface authentication program. In other words, the electronic device 25 can transmit the first request signal to the clock pin DCK of the connection device 21 through the clock pin PCK, so that the clock is connected. The pin DCK receives the low voltage level of the first request signal, and causes the connection device 21 to react to the first request signal to adjust the resource. The voltage level on the material pin DDA is at a low voltage level, and the data pin PDA of the electronic device 25 receives the low voltage level. The signal of the low voltage level can be regarded as the second request signal, that is, the connecting device 21 can transmit the second request signal to the data pin PDA of the electronic device 25 through the data pin PDA.

藉此,當電子裝置25回應於連接裝置21的資料接腳DDA上的電壓準位,而調整資料接腳PDA上的電壓準位時,電子裝置25即可使時脈接腳PCK與連接裝置21的時脈接腳DCK相連,以及使資料接腳PDA與該連接裝置21的資料接腳DDA相連。此時,介面認證程序的交握過程完成,藉以認證並設定時脈接腳PCK、DCK及資料接腳PDA、DDA為內部整合電路介面以進行傳輸,且使控制單元24、27之間可以進行通訊。上述流程也可適用於電子裝置25以反面連接至連接裝置21的情況,且致能或禁能準位的設定亦可調整,在此不贅述。 Therefore, when the electronic device 25 adjusts the voltage level on the data pin PDA in response to the voltage level on the data pin DDA of the connection device 21, the electronic device 25 can make the clock pin PCK and the connecting device. The clock pin DCK of 21 is connected, and the data pin PDA is connected to the data pin DDA of the connecting device 21. At this time, the handshake process of the interface authentication program is completed, thereby authenticating and setting the clock pins PCK, DCK and the data pins PDA, DDA to the internal integrated circuit interface for transmission, and enabling the control units 24 and 27 to perform communication. The above process can also be applied to the case where the electronic device 25 is connected to the connecting device 21 on the reverse side, and the setting of the enabling or disabling level can also be adjusted, and details are not described herein.

下表二列出連接裝置21在『初始狀態』、『認證步驟1』(接收第一請求訊號)、『認證步驟2』(回應第一請求訊號)的情況下,時脈接腳PCK、DCK、資料接腳PDA、DDA、中斷接腳PINT及控制訊號GPA0、GPA1其個別的電壓準位。其中,『1』代表高電壓準位,『0』代表低電壓準位。同一欄位中列出兩個數值可分別對應電子裝置25以正面/反面連接至連接裝置21的情況。 Table 2 below lists the connection device 21 in the "initial state", "authentication step 1" (receive the first request signal), "authentication step 2" (in response to the first request signal), the clock pin PCK, DCK , data pin PDA, DDA, interrupt pin PINT and control signals GPA0, GPA1 their individual voltage levels. Among them, "1" represents the high voltage level, and "0" represents the low voltage level. Two values listed in the same field may correspond to the case where the electronic device 25 is connected to the connecting device 21 in front/back.

表二 Table II

在一實施例中,表一及表二還可建立成查找表,其可用以比對並判斷電子裝置25與連接裝置21的連接情形。 In an embodiment, Tables 1 and 2 may also be established as a lookup table that can be used to compare and determine the connection of the electronic device 25 to the connection device 21.

從另一角度而言,本發明實施例提出一種連接裝置的連接偵測方法。請參照圖4,圖4是依照本發明一實施例所繪示的連接裝置的連接偵測方法的流程圖。在步驟S402中,提供第一及第二共同接腳對稱於連接介面的中心軸線以進行配置,其中第一及第二共同接腳的其中之一耦接電子裝置的時脈接腳,第一及第二共同接腳的其中之另一耦接電子裝置的資料接腳。在步驟S404中,依據第一及第二共同接腳上的電壓變化以判斷第一共同接腳耦接至時脈接腳或資料接腳,以及判斷第二共同接腳耦接至時脈接腳或資料接腳。 In another aspect, an embodiment of the present invention provides a connection detection method for a connection device. Please refer to FIG. 4. FIG. 4 is a flowchart of a method for detecting connection of a connection device according to an embodiment of the invention. In step S402, the first and second common pins are symmetrically disposed on the central axis of the connection interface for configuration, wherein one of the first and second common pins is coupled to the clock pin of the electronic device, first And the other of the second common pins is coupled to the data pin of the electronic device. In step S404, according to the voltage change on the first and second common pins, it is determined that the first common pin is coupled to the clock pin or the data pin, and the second common pin is coupled to the clock pin. Foot or data pin.

綜上所述,本發明實施例的複合裝置、連接裝置及其連接偵測方法可使用連接裝置的兩個共同接腳來傳輸時脈訊號及資料訊號,並藉由共同接腳上的電壓變化來判斷電子裝置是以正面或反面而連接至連接裝置。此外,電子裝置和連接裝置之間還可透過共同接腳進行介面認證程序,從而利用內部整合電路協定來相互通訊。藉此,本發明實施例可有效減少連接裝置的接腳數量並提升擴充性。 In summary, the composite device, the connecting device and the connection detecting method thereof according to the embodiments of the present invention can transmit the clock signal and the data signal by using two common pins of the connecting device, and change the voltage on the common pin. It is judged that the electronic device is connected to the connecting device in front or back. In addition, an interface authentication procedure can be performed between the electronic device and the connection device through a common pin to communicate with each other by using an internal integrated circuit protocol. Thereby, the embodiment of the invention can effectively reduce the number of pins of the connecting device and improve the expandability.

雖然本發明已以實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明的精神和範圍內,當可作些許的更動與潤飾,故本發明的保護範圍當視後附的申請專利範圍所界定者為準。 Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

20‧‧‧複合裝置 20‧‧‧Composite device

21‧‧‧連接裝置 21‧‧‧Connecting device

22、26‧‧‧連接介面 22, 26‧‧‧ Connection interface

24、27‧‧‧控制單元 24, 27‧‧‧Control unit

25‧‧‧電子裝置 25‧‧‧Electronic devices

CLK3‧‧‧時脈接腳 CLK3‧‧‧ clock pin

COM1、COM2‧‧‧共同接腳 COM1, COM2‧‧‧ common feet

DAT3‧‧‧資料接腳 DAT3‧‧‧ data pin

GND1~GND3‧‧‧接地接腳 GND1~GND3‧‧‧ Grounding Pin

INT、INT3‧‧‧中斷接腳 INT, INT3‧‧‧ interrupt pin

L‧‧‧中心軸線 L‧‧‧ center axis

PWR1~PWR3‧‧‧電源接腳 PWR1~PWR3‧‧‧ power pin

Claims (10)

一種連接裝置,用於連接一電子裝置,該連接裝置包括:一連接介面,包括;一第一及第二共同接腳,對稱於該連接介面的一中心軸線以進行配置,其中該第一及第二共同接腳的其中之一耦接該電子裝置的一第一時脈接腳,該第一及第二共同接腳的其中之另一耦接該電子裝置的一第一資料接腳;以及一控制單元,耦接至該第一及第二共同接腳,該控制單元依據該第一及第二共同接腳上的電壓變化以判斷該第一共同接腳耦接至該第一時脈接腳或該第一資料接腳,以及判斷該第二共同接腳耦接至該第一時脈接腳或該第一資料接腳。 A connecting device for connecting an electronic device, the connecting device comprising: a connecting interface, comprising: a first and a second common pin, symmetrically arranged with a central axis of the connecting interface, wherein the first One of the first common pins is coupled to a first clock pin of the electronic device, and the other of the first and second common pins is coupled to a first data pin of the electronic device; And a control unit coupled to the first and second common pins, wherein the control unit determines that the first common pin is coupled to the first time according to a voltage change on the first and second common pins a pulse pin or the first data pin, and determining that the second common pin is coupled to the first clock pin or the first data pin. 如申請專利範圍第1項所述的連接裝置,其中該第一及第二共同接腳上的電壓準位依據該電子裝置經由該第一時脈接腳所發出的一時脈訊號而變化。 The connecting device of claim 1, wherein the voltage levels on the first and second common pins are changed according to a clock signal sent by the electronic device via the first clock pin. 如申請專利範圍第2項所述的連接裝置,其中當該第一共同接腳的電壓準位依據該時脈訊號而變化時,該控制單元判定該第一共同接腳耦接至該第一時脈接腳,且該第二共同接腳耦接至該第一資料接腳,以及當該第二共同接腳的電壓準位依據該時脈訊號而變化時,該控制單元判定該第一共同接腳耦接至該第一資料接腳,且該第二共同接腳耦接至該第一時脈接腳。 The connection device of claim 2, wherein when the voltage level of the first common pin changes according to the clock signal, the control unit determines that the first common pin is coupled to the first a clock pin, wherein the second common pin is coupled to the first data pin, and when the voltage level of the second common pin changes according to the clock signal, the control unit determines the first The common pin is coupled to the first data pin, and the second common pin is coupled to the first clock pin. 如申請專利範圍第1項所述的連接裝置,其中該連接裝置更包括: 一切換電路,耦接於該第一、第二共同接腳及該控制單元之間,依據一第一及第二控制訊號以建立一第一傳輸路徑以耦接該第一共同接腳至該控制單元的一第二時脈接腳或一第二資料接腳,以及建立一第二傳輸路徑以耦接該第二共同接腳至該控制單元的該第二時脈接腳或該第二資料接腳,其中該控制單元依據該第一及第二共同接腳上的電壓變化以決定該第一及第二控制訊號的電壓準位,且該第一及第二控制訊號互為反相。 The connecting device of claim 1, wherein the connecting device further comprises: a switching circuit coupled between the first and second common pins and the control unit to establish a first transmission path to couple the first common pin to the first and second control signals a second clock pin or a second data pin of the control unit, and establishing a second transmission path to couple the second common pin to the second clock pin or the second of the control unit a data pin, wherein the control unit determines a voltage level of the first and second control signals according to a voltage change on the first and second common pins, and the first and second control signals are mutually inverted . 如申請專利範圍第1項所述的連接裝置,其中該電子裝置更包括一第一中斷接腳,其配置於該第一時脈接腳及第一資料接腳之間,用以偵測是否連接該連接介面以產生一偵測訊號,其中當該電子裝置依據該偵測訊號判斷連接該連接介面時,該電子裝置提供一電源電壓以初始化該連接裝置的該第一及第二共同接腳上的電壓準位。 The connection device of claim 1, wherein the electronic device further includes a first interrupt pin disposed between the first clock pin and the first data pin for detecting whether Connecting the connection interface to generate a detection signal, wherein when the electronic device determines to connect the connection interface according to the detection signal, the electronic device provides a power supply voltage to initialize the first and second common pins of the connection device The voltage level on the top. 如申請專利範圍第5項所述的連接裝置,其中該連接介面更包括:一第二中斷接腳,配置於該第一及第二共同接腳之間,用以下拉該第一中斷接腳上的電壓準位以使該電子裝置產生該偵測訊號;一第一及第二電源接腳,對稱於該連接介面的該中心軸線以進行配置,耦接至該電源電壓;以及一第一及第二接地接腳,對稱於該連接介面的該中心軸線以進行配置,耦接至接地電壓。 The connection device of claim 5, wherein the connection interface further comprises: a second interrupt pin disposed between the first and second common pins for pulling down the first interrupt pin a voltage level on the electronic device to generate the detection signal; a first and a second power pin symmetrical to the central axis of the connection interface for being coupled to the power supply voltage; and a first And the second grounding pin is symmetrically disposed to the central axis of the connection interface and coupled to the ground voltage. 一種連接裝置的連接偵測方法,包括:提供一第一及第二共同接腳對稱於一連接介面的一中心軸線以進行配置,其中該第一及第二共同接腳的其中之一耦接一電子裝置的一第一時脈接腳,該第一及第二共同接腳的其中之另一耦接該電子裝置的一第一資料接腳;以及依據該第一及第二共同接腳上的電壓變化以判斷該第一共同接腳耦接至該第一時脈接腳或該第一資料接腳,以及判斷該第二共同接腳耦接至該第一時脈接腳或該第一資料接腳。 A method for detecting a connection of a connecting device includes: providing a first and second common pin symmetrically to a central axis of a connection interface for configuration, wherein one of the first and second common pins is coupled a first clock pin of the electronic device, the other of the first and second common pins being coupled to a first data pin of the electronic device; and according to the first and second common pins a voltage change to determine that the first common pin is coupled to the first clock pin or the first data pin, and determining that the second common pin is coupled to the first clock pin or the The first data pin. 如申請專利範圍第7項所述的連接偵測方法,其中該電子裝置更執行一初始化程序,且該初始化程序的步驟包括:偵測是否連接該連接介面以產生一偵測訊號;以及當依據該偵測訊號判斷連接該連接介面時,提供一電源電壓以初始化該連接裝置的該第一及第二共同接腳上的電壓準位。 The connection detection method of claim 7, wherein the electronic device further performs an initialization process, and the step of the initialization process includes: detecting whether the connection interface is connected to generate a detection signal; When the detection signal determines that the connection interface is connected, a power supply voltage is provided to initialize a voltage level on the first and second common pins of the connection device. 如申請專利範圍第7項所述的連接偵測方法,其中該電子裝置更執行一介面認證程序,且該介面認證程序的步驟包括:使該連接裝置的一第二時脈接腳透過該第一共同接腳耦接至該電子裝置的該第一時脈接腳,且使該連接裝置的一第二資料接腳透過該第二共同接腳耦接至該電子裝置的該第一資料接腳;透過該第一時脈接腳傳送一第一請求訊號至該連接裝置的該第二時脈接腳,使該連接裝置反應於該第一請求訊號以調整該第二資料接腳上的電壓準位以傳送一第二請求訊號至該電子裝置的該第一資料接腳;以及 當回應該連接裝置的該第二資料接腳上的電壓準位而調整該第一資料接腳上的電壓準位時,使該第一時脈接腳與該連接裝置的該第二時脈接腳相連,以及使該第一資料接腳與該連接裝置的該第二資料接腳相連,並且認證並設定該第一、第二時脈接腳以及該第一、第二資料接腳為內部整合電路介面以進行傳輸。 The connection detection method of claim 7, wherein the electronic device further performs an interface authentication procedure, and the step of the interface authentication procedure comprises: transmitting a second clock pin of the connection device through the A first pin is coupled to the first clock pin of the electronic device, and a second data pin of the connecting device is coupled to the first data connector of the electronic device through the second common pin Sending a first request signal to the second clock pin of the connecting device through the first clock pin, causing the connecting device to react to the first request signal to adjust the second data pin Voltage level to transmit a second request signal to the first data pin of the electronic device; When the voltage level on the first data pin is adjusted in response to the voltage level on the second data pin of the connection device, the first clock pin and the second clock of the connection device are caused Connecting the pins, and connecting the first data pin to the second data pin of the connecting device, and authenticating and setting the first and second clock pins and the first and second data pins The internal integrated circuit interface is used for transmission. 一種複合裝置,包括:一電子裝置,包括:一第一控制單元;以及一第一連接介面,包括一第一時脈接腳及一第一資料接腳,分別耦接至該第一控制單元;以及一連接裝置,包括:一第二連接介面,包括一第一及第二共同接腳,對稱於該第二連接介面的一中心軸線以進行配置,其中該第一及第二共同接腳的其中之一耦接該第一時脈接腳,該第一及第二共同接腳的其中之另一耦接該第一資料接腳;以及一第二控制單元,耦接至該第一及第二共同接腳,該第二控制單元依據該第一及第二共同接腳上的電壓變化以判斷該第一共同接腳耦接至該第一時脈接腳或該第一資料接腳,以及判斷該第二共同接腳耦接至該第一時脈接腳或該第一資料接腳。 A composite device includes: an electronic device, comprising: a first control unit; and a first connection interface, including a first clock pin and a first data pin, respectively coupled to the first control unit And a connecting device, comprising: a second connecting interface, comprising a first and second common pins symmetrically disposed on a central axis of the second connecting interface, wherein the first and second common pins One of the first and second common pins is coupled to the first data pin; and the second control unit is coupled to the first And the second common pin, the second control unit is configured to determine that the first common pin is coupled to the first clock pin or the first data connection according to the voltage change on the first and second common pins And determining that the second common pin is coupled to the first clock pin or the first data pin.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160335219A1 (en) * 2015-05-13 2016-11-17 Ite Tech. Inc. Data transmission system and transmission method thereof
CN110244161A (en) * 2018-03-07 2019-09-17 和硕联合科技股份有限公司 Connecting detection system and its detection method

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160335219A1 (en) * 2015-05-13 2016-11-17 Ite Tech. Inc. Data transmission system and transmission method thereof
US9898436B2 (en) * 2015-05-13 2018-02-20 Ite Tech. Inc. Data transmission system and transmission method thereof including connection and orientation detection
CN110244161A (en) * 2018-03-07 2019-09-17 和硕联合科技股份有限公司 Connecting detection system and its detection method

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