JP2003259564A - Charging current detecting circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the cost by canceling an input DC offset voltage of an amplifier for detecting a charging current with no temperature fluctuation, eliminating the need for adjusting at shipping, and omitting a large scale circuit such as an A/D converter and a CPU. <P>SOLUTION: A resistor 5 is connected in series to a battery 4. A zero voltage is inputted between both input terminals of an amplifier 6 in a first phase, while the charging current detection voltage that appears at the resistor 5 is inputted between both input terminals of the amplifier 6 in a second phase using a switch 9. A second switch 10 is closed in the first phase to write an output voltage of the amplifier 6 into a voltage storage element 8. A third switch 11 whose one end is connected to the output terminal of the amplifier 6 is closed in the second phase. A voltage at the other end of the third switch 11 added with a reference voltage 14 which regulates a stop point for charging operation is compared to the storage voltage of the voltage storage element 8 using a comparator 7, and the output of the comparator 7 is held by a latch circuit 12. <P>COPYRIGHT: (C)2003,JPO

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a charging current detection circuit. 2. Description of the Related Art In recent years, portable devices have rapidly become widespread.
In response to the demand for long-term operation of these portable devices, demand for a highly accurate charging current detection circuit is increasing. In order to operate the battery for a long time, it is necessary to stop charging when the battery has been charged up to the maximum stored power (full charge). The charging current detection circuit has the function of determining full charge based on the amount of charging current and stopping charging.However, if the accuracy of this determination is poor, there is a possibility of charging more than the maximum accumulated charge of the battery to be charged. For this reason, it is necessary to stop charging before full charging in anticipation of safety. As a result, the operation time of the portable device is shortened. The charging current determination accuracy is the most important specification of the charging current detection circuit. The determination of full charge is made by detecting that the charge current has become equal to or less than a predetermined current. FIG. 5 is a block diagram showing a configuration of a conventional charging current detection circuit. 5, 1 is an external power supply terminal, 2 is a battery terminal, 3 is an output terminal, 4 is a battery to be charged, 5
Is a charging current detecting resistor, 6 is an amplifier, 15 is reference data corresponding to a charging current value when charging is completed, 16 is an A / D converter, 17 is an adder, 18
Is a CPU. The operation of the conventional charging current detection circuit will be described below with reference to FIG. A charging current ICHG is supplied from an external power supply terminal 1 to a battery 4 to be charged through a charging current detecting resistor 5. Thus, the product of the resistance value R of the charging current detection resistor 5 and the charging current ICHG is the charging current detection voltage ΔVin (= ICHG ×
R) can be detected. That is, the external power supply terminal 1
A charging current detection voltage ΔVin (= ICHG × R) is obtained as a potential difference between the battery terminal 2 and the battery terminal 2. However, the charging current detection voltage ΔVin is several m
V is a very small value, and it is difficult to judge the charging current until it is. Therefore, the charging current detection voltage ΔVin needs to be amplified by α (amplification degree) times by the amplifier 6. The output voltage ΔVo of the amplifier 6 is represented by ΔVo = α × ΔVin. The voltage ΔVo is input to an A / D converter 16 controlled by a CPU 18 and converted into a digital value. The output digital value of the D converter 16 is compared with the reference data 15 by the adder 17, and the result is output to the output terminal 3. Here, the configuration and operation of the adder 17 will be specifically described. For example, the A / D converter 16
Is 8 bits, and assuming that charging is stopped when the A / D output decreases to 0Ah (h means a hexadecimal number), -0Ah is put in the reference data,
The charging is continued while the added data is a positive value, and the charging is stopped when the added data becomes a negative value. In FIG. 5, the adder 17 has a terminal for outputting 1-bit data indicating the polarity (±) of the data after addition as the output terminal 3. The above is the operation of the ideal charging current detecting circuit. In practice, however, the input DC offset voltage Δ
The amplifier 6 is amplified in a state where Voffset is added to the charging current detection voltage ΔVin. Therefore, the output voltage ΔVo of the amplifier 6 becomes ΔVo = α × (ΔVin + ΔVoffset). The input DC offset voltage ΔVoffset has an absolute value substantially equal to the charging current detection voltage ΔVin, and the detection accuracy is deteriorated as it is. The input DC offset voltage ΔVoffset is caused by a relative error of the input differential transistor inside the amplifier 6, and the absolute value per one product is fixed, but varies for each product. Therefore, at the time of product shipment, the input DC offset voltage ΔVoffset is measured for each product, and an accurate stop point of the charging operation is digitally stored as reference data 15 in the form of digital data in consideration of the measurement result of the input DC offset voltage ΔVoffset. The measures are taken by writing. To realize this operation, reference data 15, A / D converter 16, adder 17, and CPU 18 are required. With the above configuration, the input DC offset voltage Δ
The effect of Voffset is eliminated to realize accurate charging current detection. However, in the above-described conventional circuit configuration, since the input DC offset voltage ΔVoffset of the amplifier 6 fluctuates due to temperature, a temperature fluctuation occurs in the output voltage ΔVo of the amplifier 6. Will occur. Therefore, even if the above adjustment is performed at the time of product shipment, there is a disadvantage that the charging current detection accuracy is deteriorated during the actual charging due to a change in ambient temperature. Further, at the time of product shipment, it is necessary to measure the input DC offset voltage ΔVoffset for each product and write an accurate charging stop point as internal reference data 15 as digital data. And the disadvantage that the reference data 15, the A / D converter 16, the adder 17, and the CPU 18 are required to improve the accuracy, the circuit scale is increased, and the cost is increased. I was SUMMARY OF THE INVENTION An object of the present invention is to provide a low-cost charging current detection circuit which is free from temperature fluctuations, has high accuracy, does not require an adjustment step at the time of product shipment, and solves the above conventional problems. . In order to achieve this object, a charging current detection circuit according to the present invention comprises a charging current detection resistor connected in series with a battery to be charged, and one and other inputs. An amplifier for amplifying a voltage applied between the terminals, a zero voltage between one and the other input terminals of the amplifier in a first phase, and a charging current between one and the other input terminals of the amplifier in a second phase. A first switch for inputting a charging current detection voltage appearing at both ends of the detection resistor, a voltage storage element for storing a voltage appearing at an output terminal of the amplifier, and one end connected to the output terminal of the amplifier and the other end connected to the voltage storage element And a second switch that closes one of the first and second phases to write a voltage appearing at the output terminal of the amplifier into the voltage storage element, and a first switch that is connected at one end to the output terminal of the amplifier.
A third switch that closes at one of the other phase and the second phase, a voltage obtained by adding a reference voltage defining a stop point of the charging operation to a voltage appearing at the other end of the third switch, and a storage voltage of the voltage storage element. And a latch circuit for holding the output of the comparator. According to this configuration, the voltage obtained by adding the reference voltage to the voltage at the output terminal of the amplifier when the charging current detection voltage is input and the voltage at the output terminal of the amplifier when the zero voltage is input are calculated. It will be compared with a comparator. As a result, the error due to the input offset voltage of the amplifier that appears in the voltage at the output terminal of the amplifier when the charging current detection voltage is input is equal to the input voltage of the amplifier that appears in the voltage at the output terminal of the amplifier when zero voltage is input. The error is canceled by the error due to the DC offset voltage. Therefore, it is possible to eliminate the influence of the input DC offset voltage of the amplifier when detecting the charging current. Therefore, the temperature fluctuation due to the input DC offset voltage of the amplifier does not occur in the charging current detection result, and the charging current can be detected with high accuracy. In addition, there is no need for an adjustment process at the time of product shipment as in the conventional example, and further, no components such as an A / D converter, a CPU, reference data, and an adder are required to improve accuracy, and charging is inexpensive. A current detection circuit can be obtained. Embodiments of the present invention will be described below with reference to FIG. FIG. 1 is a block diagram showing a configuration of a charging current detection circuit according to an embodiment of the present invention. In FIG. 1, 1 is an external power supply terminal, 2 is a battery terminal, 3 is an output terminal,
4 is a battery to be charged, 5 is a resistor for detecting a charging current, 6 is an amplifier, 7 is a comparator, 8 is a voltage storage element such as a capacitance element, 9
Is a switch that switches to the battery terminal 2 side in the first phase, switches to the external power supply terminal 1 side in the second phase, 10 is a switch that closes in the first phase, 11 is a switch that closes in the second phase, and 12 is a switch that closes in the second phase. A latch circuit, 13 is a clock generation circuit, and 14 is a reference voltage which is a voltage (negative value) corresponding to a charging current value when charging is completed. The operation of the charging current detection circuit will be described below. The charging current ICHG is supplied from the external power supply terminal 1 to the battery 4 through the charging current detection resistor 5.
The charging current detection voltage ΔVin (= ICHG × R) can be detected from the product of the resistance value R of the charging current detection resistor 5 and the charging current ICHG. That is, as the potential difference between the external power supply terminal 1 and the battery terminal 2, the charging current detection voltage ΔVin (=
ICHG × R) is obtained. First, in the first phase, when both input terminals of the amplifier 6 are short-circuited by the changeover switch 9, zero voltage is input, that is, the voltage of the battery terminal 4 is input to both input terminals of the amplifier 6. Therefore, the output voltage ΔVo1 of the amplifier 6 is ΔVo1 = α × ΔVoffset. This value is input to the voltage storage element 8 via the switch 10 that closes in the first phase. Next, in the second phase, the changeover switch 9 applies a charging current detection voltage ΔVin (= ICHG × R) between both input terminals of the amplifier 6. At this time, the output voltage ΔVo2 of the amplifier 6 is ΔVo2 = α × (Vin + ΔVoffset). At this time, since the switch 10 is open, the voltage difference ΔVoave between both ends of the switch 10 becomes ΔVoave = ΔVo2−ΔVo1 = α × Vin, and the input DC offset voltage ΔVoffset of the amplifier 6 is obtained.
The effects of are offset. Then, the voltage difference ΔVoave and the reference voltage 14 are added via the switch 11 that closes in the second phase, and are added to one input terminal of the comparator 7. The voltage appearing in the voltage storage element 8 is input to the other input terminal of the comparator 7. As a result, the comparator 7 can realize a highly accurate comparison operation without being affected by the input DC offset voltage ΔVoffset of the amplifier 6. Then, the output of the comparator 7 is latched by the latch circuit 12 at the timing when the second phase ends, and output from the output terminal 3. Here, the comparison operation in the comparator 7 will be specifically described with reference to an equivalent circuit diagram of FIG. In FIG. 2, the amplifier 6, the reference voltage 14
And the voltage storage element 8 is represented by a voltage source. here,
The voltage of the voltage storage element 8 is ΔVo1, the voltage of the amplifier 6 is ΔVo2, and the reference voltage 14 is −α · Vin.
Set to 0. Here, ΔVo1 = α · ΔVoffset ΔVo2 = α · (Vin + ΔVoffset). When the charging current is still large, that is, Vin
When> Vin0, the voltage of the upper input terminal (ΔVo2−α · Vin0) of the comparator 7 is higher than the voltage ΔVo1 of the lower input terminal of the comparator 7. When the charging proceeds and Vin = Vin0, the voltage of the upper input terminal of the comparator 7 (ΔVo2-α
Vin0) is the voltage ΔVo of the lower input terminal of the comparator 7
1 and the output of the comparator 7 is inverted. Here, the signals for setting the first phase and the second phase are generated by the clock generation circuit 13,
Changeover switch 9, switches 10, 11 and latch circuit 1
2 and given. The first phase and the second phase are alternately repeated. S1 is a signal that becomes active in the first phase, and S2 is a signal that becomes active in the second phase. FIG. 3 is a timing chart of each part of the charging current detection circuit of FIG. FIG. 3 shows the signals S1 and S2 output from the clock generation circuit 13, the states of the changeover switches 9 and the switches 10 and 11, and the latch timing of the latch circuit 12. In FIG. 3, when the signal S1 is low and the signal S2 is high, the changeover switch 9 is switched to the external power supply terminal 1, the switch 10 is off, and the switch 11 is on. When signal S1 is high and signal S
When 2 is low, the changeover switch 9 switches to the battery terminal 2 side, the switch 10 is on, and the switch 11 is off. The latch timing of the latch circuit 12 is as follows.
This is the timing when the signal S2 switches from high to low. Note that, in the timing diagram of FIG.
2 has just the opposite phase and there is no pause between the high sections of the signals S1 and S2, but there may be a pause. FIG. 4 shows a temporal change with the progress of the charging of the current and voltage of each part in FIG. FIG. 4 shows the signal S1
2, the charging current ICHG, the output of the amplifier 6, the upper input, the lower input and the output of the comparator 7, the latch timing of the latch circuit 12, and the state of the output terminal 3. In FIG. 4, the charging current gradually decreases over time. The output of the amplifier 6 becomes a voltage corresponding to the charging current when the signal S1 is low, and the signal S1
Is high, the offset voltage. The upper input of the comparator 7 receives the output of the amplifier 6 when the signal S1 is low, and becomes indefinite when the signal S1 is high. The lower input of the comparator 7 always becomes the holding voltage (offset voltage) of the voltage storage element 8. The output of the comparator 7 has a value corresponding to the comparison result between the upper input and the lower input when the signal S1 is low, and becomes undefined when the signal S1 is high. In this example, the latch timing of the latch circuit 12 is a timing at which the signal S1 changes from low to high (a timing at which the signal S2 changes from high to low). The value of output terminal 3 is
It changes in synchronization with the latch timing. By adopting this configuration, the amplifier 6
Of the input DC offset voltage ΔVoffset, the temperature dependence of the input offset voltage ΔVoffset can also be offset. Further, since there is no influence of the input offset voltage ΔVoffset, the adjustment / writing process at the time of product shipment is not required, and the reference data 15, the A / D converter 16, and the adder which are factors for increasing the circuit scale are also provided. 1
7. The CPU 18 becomes unnecessary, and the cost can be reduced. When both input terminals of the amplifier 6 are short-circuited, the voltage applied to the input terminal of the amplifier 7 may be the external power supply voltage 1, the battery voltage 2, or another reference voltage. That is, any voltage can be applied. Also, the first phase and the second phase, and
The same effect can be obtained by either combination of the phase of applying the charging current detection voltage ΔVin to the amplifier 6 and the phase of shorting the input terminal of the amplifier 6. That is, in the above embodiment, the switch 10 is closed in the first phase and the switch 11 is closed in the second phase. However, the switch 10 is closed in the second phase and the switch 11 is closed in the first phase. It is good also as a structure closed in the phase of. As described above, according to the charging current detection circuit of the present invention, the voltage obtained by adding the reference voltage to the voltage at the output terminal of the amplifier when the charging current detection voltage is input, and the zero voltage The comparator compares the voltage at the output terminal of the amplifier in the state where the voltage is input. As a result, the error due to the input offset voltage of the amplifier that appears in the voltage at the output terminal of the amplifier when the charging current detection voltage is input is equal to the input voltage of the amplifier that appears in the voltage at the output terminal of the amplifier when zero voltage is input. The error is canceled by the error due to the DC offset voltage. Therefore, it is possible to eliminate the influence of the input DC offset voltage of the amplifier when detecting the charging current. Therefore,
Temperature fluctuation due to the input DC offset voltage of the amplifier does not occur in the charging current detection result, and the charging current can be detected with high accuracy. Further, an adjustment process at the time of shipping the product as in the conventional example is unnecessary, and components such as an A / D converter, a CPU, reference data, and an adder are not required to improve the accuracy, and charging is inexpensive. A current detection circuit can be obtained.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a configuration of a charging current detection circuit according to an embodiment of the present invention. FIG. 2 is an equivalent circuit diagram for explaining an operation of the charging current detection circuit according to the embodiment of the present invention. FIG. 3 is a timing chart showing an operation of the charging current detection circuit according to the embodiment of the present invention. FIG. 4 is a timing chart showing an operation of the charging current detection circuit according to the embodiment of the present invention. FIG. 5 is a block diagram showing a configuration of a conventional charging current detection circuit. [Description of Signs] 1 External power supply terminal 2 Battery terminal 3 Output terminal 4 Battery to be charged 5 Charge current detecting resistor 6 Amplifier 7 Comparator 8 Voltage storage element 9 Changeover switch (first switch) 10 Switch (second switch) 11 switch (third switch) 12 latch circuit 13 clock generation circuit 14 reference voltage 15 reference data 16 A / D converter 17 adder 18 CPU

Continuation of front page    F term (reference) 2G016 CB31 CC01 CC03 CC04 CC05                       CC12 CC23 CD02 CD14                 5G003 CA01 CC02 FA08 GC05                 5H030 AA01 AS11 BB01 FF42                 5J090 AA01 AA51 CA02 CN01 FA18                       FN01 HA25 HA29 HA38 HN07                       HN10 KA11 KA17 KA19 KA28                       KA34 SA00 TA01 TA06                 5J500 AA01 AA51 AC02 AF18 AH25                       AH29 AH38 AK11 AK17 AK19                       AK28 AK34 AS00 AT01 AT06                       NC01 NF01 NH07 NH10

Claims (1)

Claims: 1. A charging current detecting resistor connected in series with a battery to be charged, an amplifier for amplifying a voltage applied between one and the other input terminals, and A zero voltage is input between one and the other input terminals of the amplifier, and a charging current detection voltage appearing at both ends of the charging current detection resistor is input between the one and the other input terminals of the amplifier in a second phase. 1 switch, a voltage storage element that stores a voltage appearing at an output terminal of the amplifier, and one end connected to the output terminal of the amplifier and the other end connected to the voltage storage element, the first and second phases. A second switch that closes one of the first and second amplifiers to write the voltage appearing at the output terminal of the amplifier into the voltage storage element; A third switch that is closed on the other side, a comparison that compares a voltage that appears at the other end of the third switch with a reference voltage that defines a stop point of the charging operation, and a storage voltage of the voltage storage element. And a latch circuit for holding an output of the comparator.