JP2003258304A - Semiconductor light emitting element and its fabricating method - Google Patents

Semiconductor light emitting element and its fabricating method

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Publication number
JP2003258304A
JP2003258304A JP2002052512A JP2002052512A JP2003258304A JP 2003258304 A JP2003258304 A JP 2003258304A JP 2002052512 A JP2002052512 A JP 2002052512A JP 2002052512 A JP2002052512 A JP 2002052512A JP 2003258304 A JP2003258304 A JP 2003258304A
Authority
JP
Japan
Prior art keywords
layer
light emitting
semiconductor light
transparent conductive
emitting device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2002052512A
Other languages
Japanese (ja)
Inventor
Taiichiro Konno
泰一郎 今野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Cable Ltd
Original Assignee
Hitachi Cable Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Cable Ltd filed Critical Hitachi Cable Ltd
Priority to JP2002052512A priority Critical patent/JP2003258304A/en
Publication of JP2003258304A publication Critical patent/JP2003258304A/en
Withdrawn legal-status Critical Current

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Abstract

<P>PROBLEM TO BE SOLVED: To obtain an LED of such a structure as a transparent conductive film of metal oxide is employed as a current distribution film in which the forward working voltage Vf is lowered while eliminating variation of Vf among the elements by making possible to lower the resistance of the transparent conductive film. <P>SOLUTION: A light emitting part consisting of a first conductivity type clad layer 2 and a second conductivity type clad layer 4 sandwiching an active layer 3 is formed on a first conductivity type substrate 1, a transparent conductive layer 8 of metal oxide is formed thereon, an upper electrode 9 is formed at a part on the surface of the transparent conductive layer, and an electrode 10 is formed entirely or partially on the surface of the first conductivity type substrate 1 opposite to the side where the light emitting layer is formed. In such a semiconductor light emitting element, a multilayer structure of a Zn layer 6 and an Ni layer 7 is provided between the second conductivity type clad layer 4 and the transparent conductive layer 8. <P>COPYRIGHT: (C)2003,JPO

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、高輝度の半導体発
光素子、特に順方向動作電圧の低い半導体発光素子及び
その製造方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-luminance semiconductor light emitting device, particularly to a semiconductor light emitting device having a low forward operation voltage and a method for manufacturing the same.

【0002】[0002]

【従来の技術】従来、発光ダイオード(Light Emitting
Diode:LED)は、GaPの緑色、AlGaAsの赤
色がほとんどであった。しかし、最近GaN系やAlG
aInP系の結晶層をMOVPE法で成長できるように
なったことから、橙色、黄色、緑色、青色の高輝度LE
Dが製作できるようになってきた。
2. Description of the Related Art Conventionally, light emitting diodes (Light Emitting)
Most of the diodes (LEDs) were GaP green and AlGaAs red. However, recently GaN and AlG
Since it became possible to grow an aInP-based crystal layer by the MOVPE method, high brightness LE of orange, yellow, green and blue was obtained.
D can be produced now.

【0003】MOVPE法で形成したエピタキシャルウ
ェハは、これまでに無かった短波長の発光や、高輝度を
示すLEDの製作を可能とした。しかし、高輝度を得る
ために、電流分散層の膜厚を厚く成長させようとする
と、LED用エピタキシャルウェハのコストが高くなる
ことが問題であった。
Epitaxial wafers formed by the MOVPE method have enabled the production of LEDs exhibiting short-wavelength light emission and high brightness, which have never existed before. However, if an attempt is made to grow the film thickness of the current spreading layer in order to obtain high brightness, there is a problem that the cost of the LED epitaxial wafer increases.

【0004】これらの問題を解決する方法としては、電
流分散層としてできるだけ抵抗の低い値が得られる材料
を用いる方法がある。例えばAlGaInP4元系の場
合には、電流分散層としてGaPやAlGaAsが用い
られたりしている。しかし、これらの抵抗率の低い材料
を用いてもやはり電流分散を良くするためには、膜厚を
8μm以上まで厚くする必要がある。
As a method of solving these problems, there is a method of using a material that can obtain a resistance value as low as possible for the current spreading layer. For example, in the case of AlGaInP quaternary system, GaP or AlGaAs is used as the current spreading layer. However, even if these materials having a low resistivity are used, it is necessary to increase the film thickness to 8 μm or more in order to improve the current distribution.

【0005】この膜を薄くするためには、電流分散層の
抵抗率を低くすることが考えられる。また移動度を大幅
に変えることは困難であることから、キャリア濃度を高
くしようとすることも試みられているが、現段階では電
流分散層を薄くできるほどキャリア濃度を高くすること
はできない。
In order to make this film thinner, it is conceivable to lower the resistivity of the current spreading layer. Further, since it is difficult to change the mobility drastically, attempts have been made to increase the carrier concentration, but at the present stage, the carrier concentration cannot be increased so that the current dispersion layer can be thinned.

【0006】この解決手段として、半導体の電流分散層
の変わりに、キャリア濃度が非常に高く、薄い膜厚で十
分な電流分散を得ることができるため、透明導電膜を用
いる方法が提案されている。
As a means for solving this problem, a method using a transparent conductive film has been proposed because the carrier concentration is very high and sufficient current distribution can be obtained with a thin film thickness, instead of the semiconductor current distribution layer. .

【0007】[0007]

【発明が解決しようとする課題】しかしながら、金属酸
化膜を用いた透明導電膜を用いた場合、その上に金属電
極が形成されるが、エピタキシャルウェハ最上層と透明
導電膜間に接触抵抗が発生してしまい、順方向動作電圧
が高くなるという問題が発生する。
However, when a transparent conductive film using a metal oxide film is used, a metal electrode is formed thereon, but contact resistance occurs between the uppermost layer of the epitaxial wafer and the transparent conductive film. Therefore, there arises a problem that the forward operating voltage becomes high.

【0008】この問題を解決するために、エピタキシャ
ルウェハ最上層と透明導電膜間にZn若しくはAu−Z
n合金膜を挿入して順方向動作電圧(以下Vfと略す)
を低くする方法が開示されている(特開平11−402
0号公報明細書参照)。
In order to solve this problem, Zn or Au--Z is provided between the uppermost layer of the epitaxial wafer and the transparent conductive film.
Forward operation voltage (hereinafter abbreviated as Vf) by inserting n-alloy film
A method of lowering the noise is disclosed (Japanese Patent Laid-Open No. 11-402).
No. 0 specification).

【0009】しかしこの方法では、透明導電膜を420
℃以上で形成すると、エピタキシャルウェハ最上層と透
明導電膜間に形成したZn若しくはAu−Zn合金膜が
球状化してしまい、半導体発光素子若しくはエピタキシ
ャルウェハ面内でZn若しくはAu−Zn合金膜が無い
部分ができてしまう。このため半導体発光素子の中に、
非常にVfが高いものができる。また、前記球状化を抑
止するために、透明導電膜形成温度を420℃より低く
すると、透明導電膜が十分に低抵抗化できず、透明導電
膜を形成した効果が無い。
However, according to this method, the transparent conductive film is formed as 420
If formed at a temperature of ℃ or higher, the Zn or Au-Zn alloy film formed between the uppermost layer of the epitaxial wafer and the transparent conductive film becomes spherical, and the Zn or Au-Zn alloy film does not exist in the semiconductor light emitting device or the epitaxial wafer. Will be created. Therefore, in the semiconductor light emitting device,
Something with very high Vf can be made. Further, if the transparent conductive film forming temperature is lower than 420 ° C. in order to suppress the spheroidization, the resistance of the transparent conductive film cannot be sufficiently lowered, and there is no effect of forming the transparent conductive film.

【0010】またエピタキシャルウェハ最上層と透明導
電膜間にZn、Au−Zn合金膜以外にNi、In、A
l、Au、Pt、Sb、Ag、Ti、Cr、Mo、V、
Au−Ge、Au−Sn、In−Sn、Au−Be、I
n−Znを挿入して、Vfを低くする方法が開示されて
いる(特開2001−36130、2001−6872
8号公報参照)。
In addition to the Zn and Au--Zn alloy films, Ni, In and A are provided between the uppermost layer of the epitaxial wafer and the transparent conductive film.
l, Au, Pt, Sb, Ag, Ti, Cr, Mo, V,
Au-Ge, Au-Sn, In-Sn, Au-Be, I
A method of lowering Vf by inserting n-Zn is disclosed (Japanese Patent Laid-Open No. 2001-36130, 2001-6872).
No. 8).

【0011】しかしIn−Znを用いた場合、上記した
透明導電膜の形成条件では、420℃以上で形成する
と、エピタキシャルウェハ最上層と透明導電膜間に形成
したIn−Zn合金膜が球状化してしまい、半導体発光
素子若しくはエピタキシャルウェハ面内でIn−Zn合
金膜が無い部分ができてしまう。このため半導体発光素
子の中に、非常にVfが高いものができる。
However, in the case of using In—Zn, under the above-mentioned conditions for forming the transparent conductive film, if formed at 420 ° C. or higher, the In—Zn alloy film formed between the uppermost layer of the epitaxial wafer and the transparent conductive film becomes spherical. As a result, a portion without the In—Zn alloy film is formed in the surface of the semiconductor light emitting device or the epitaxial wafer. Therefore, some semiconductor light emitting devices can have a very high Vf.

【0012】また、その他の材料でも、融点が420℃
以下の材料では、前記球状化現象が起こる。融点が42
0℃以上の前記材料を挿入すると、前記球状化現象を抑
えることができるが、Zn系材料を用いた時よりもVf
が高い。
Other materials have a melting point of 420 ° C.
The spheroidization phenomenon occurs in the following materials. Melting point 42
Insertion of the material at 0 ° C. or higher can suppress the spheroidization phenomenon, but Vf is higher than when Zn-based material is used.
Is high.

【0013】そこで、本発明の目的は、上記課題を解決
し、電流分散膜として金属酸化膜の透明導電膜を用いた
構造の半導体発光素子において、透明導電膜の低抵抗化
を可能として順方向動作電圧Vfを低くし、且つVfの
素子間バラツキをなくすことにある。
Therefore, an object of the present invention is to solve the above problems and to reduce the resistance of a transparent conductive film in a forward direction in a semiconductor light emitting device having a structure using a transparent conductive film of a metal oxide film as a current spreading film. The purpose is to lower the operating voltage Vf and to eliminate variations in Vf between elements.

【0014】[0014]

【課題を解決するための手段】上記目的を達成するた
め、本発明は、次のように構成したものである。
In order to achieve the above object, the present invention is configured as follows.

【0015】請求項1の発明に係る半導体発光素子は、
第一導電型の基板の上に、活性層を第一導電型のクラッ
ド層と第二導電型のクラッド層とで挟んだ発光部を形成
し、その上に金属酸化膜からなる透明導電層を形成し、
前記透明導電層の表面の一部に上部電極を形成し、第一
導電型の基板の発光部層が形成された反対側の面に、全
面又は部分的に電極を形成した半導体発光素子におい
て、前記第二導電型のクラッド層と前記透明導電層の間
に、Zn層とNi層が順次積層されていることを特徴と
する。
A semiconductor light emitting device according to the invention of claim 1 is
On the first conductivity type substrate, an active layer is sandwiched between a first conductivity type clad layer and a second conductivity type clad layer to form a light emitting portion, and a transparent conductive layer made of a metal oxide film is formed thereon. Formed,
An upper electrode is formed on a part of the surface of the transparent conductive layer, and on a surface opposite to the surface where the light emitting section layer of the first conductivity type substrate is formed, a semiconductor light emitting device in which an electrode is formed wholly or partially, A Zn layer and a Ni layer are sequentially stacked between the second conductive type clad layer and the transparent conductive layer.

【0016】請求項2の発明は、請求項1に記載の半導
体発光素子において、前記発光部と前記Zn層との間
に、第二導電型の電流分散層が形成されていることを特
徴とする。これはZn層が電流分散層側に存する形態で
ある。
According to a second aspect of the present invention, in the semiconductor light emitting element according to the first aspect, a second conductivity type current spreading layer is formed between the light emitting portion and the Zn layer. To do. This is a form in which the Zn layer is present on the side of the current spreading layer.

【0017】請求項3の発明は、請求項1又は2に記載
の半導体発光素子において、前記透明導電層の上に形成
された電極の直下にあたる部分の一部には、順次積層さ
れた前記Zn層とNi層が形成されていないことを特徴
とする。
According to a third aspect of the present invention, in the semiconductor light emitting element according to the first or second aspect, the Zn layers sequentially stacked are partially laminated on a portion of a portion immediately below the electrode formed on the transparent conductive layer. The layer and the Ni layer are not formed.

【0018】請求項4の発明は、請求項1〜3のいずれ
かに記載の半導体発光素子において、前記Zn層とNi
層の厚さがそれぞれ1nm以上であり、前記Zn層とN
i層の厚さが合わせて15nm以下であることを特徴と
する。
According to a fourth aspect of the invention, in the semiconductor light emitting device according to any one of the first to third aspects, the Zn layer and the Ni layer are formed.
Each of the layers has a thickness of 1 nm or more,
The i-layer has a total thickness of 15 nm or less.

【0019】請求項5の発明は、請求項1〜4のいずれ
かに記載の半導体発光素子において、前記上部電極が円
形、角形又は円形の角形に突起を付けた形状を具備する
ことを特徴とする。
According to a fifth aspect of the present invention, in the semiconductor light emitting element according to any one of the first to fourth aspects, the upper electrode has a circular shape, a rectangular shape, or a shape in which a protrusion is attached to a circular prism. To do.

【0020】請求項6の発明は、請求項3に記載の半導
体発光素子において、順次積層された前記Zn層とNi
層が形成されていない領域は、上部電極と中心が略合致
し、且つ前記電極の0.6〜1.3倍であることを特徴
とする。
According to a sixth aspect of the present invention, in the semiconductor light emitting device according to the third aspect, the Zn layer and the Ni layer are sequentially stacked.
The region where the layer is not formed is characterized in that the center thereof substantially coincides with the upper electrode and is 0.6 to 1.3 times as large as the electrode.

【0021】請求項7の発明は、請求項1〜6のいずれ
かに記載の半導体発光素子において、前記基板がGaA
sから成り、前記発光部がAlGaInP又はGaIn
Pから成ることを特徴とする。
According to a seventh aspect of the present invention, in the semiconductor light emitting element according to any one of the first to sixth aspects, the substrate is GaA.
s, and the light emitting portion is AlGaInP or GaIn
It is characterized by consisting of P.

【0022】請求項8の発明に係る半導体発光素子の製
造方法は、請求項1〜6のいずれかに記載の半導体発光
素子を製造する方法において、透明導電層の形成温度を
420℃以上とすることを特徴とする。
A method for manufacturing a semiconductor light emitting device according to an eighth aspect of the present invention is the method for manufacturing a semiconductor light emitting device according to any one of the first to sixth aspects, wherein the formation temperature of the transparent conductive layer is 420 ° C. or higher. It is characterized by

【0023】なお、請求項3及び請求項6に記載の半導
体発光素子において、電極を設けるに際しては、フォト
リソプロセスにより、エピタキシャルウェハ上に部分的
に金属薄膜層の形成されていない部分と中心を略合致さ
せる様に電極を配列するとよい。
In the semiconductor light emitting device according to the third and sixth aspects, when the electrodes are provided, a portion where the metal thin film layer is not partially formed on the epitaxial wafer and a center thereof are formed by a photolithography process. The electrodes may be arranged to match.

【0024】<発明の要点>本発明は、上記目的を達す
るために、電流分散膜として金属酸化膜の透明導電膜を
用いた構造のLEDにおいて、エピタキシャルウェハの
表面にVfを低くするための金属層としてZnとNiの
積層構造を設け、これにより半導体発光素子のVfの素
子間バラツキ、特にVfの高い素子の発生をなくし、且
つ透明導電膜の形成温度を高くして低抵抗の透明導電膜
の形成を可能とし、以てVfが低く、且つバラツキが少
ない高発光出力の透明電極付LEDを提供するものであ
る。
<Summary of the Invention> In order to achieve the above object, the present invention provides a metal for reducing Vf on the surface of an epitaxial wafer in an LED having a structure using a transparent conductive film of a metal oxide film as a current spreading film. A layered structure of Zn and Ni is provided as a layer, which eliminates the variation of Vf between elements of a semiconductor light emitting element, especially the generation of elements having a high Vf, and raises the formation temperature of the transparent conductive film to provide a low-resistance transparent conductive film. It is possible to provide a LED with a transparent electrode having a low Vf and a high emission output with a small variation.

【0025】Zn層とNi層の厚さは、図4に示すよう
に、Zn層及びNi層共にそれぞれ1nm以上であれ
ば、Zn層が均一化し、順方向動作電圧Vfを素子間バ
ラツキなしに、従来並に又はそれ以下に低くする効果
(図4で1.90V以下)が得られ、厚さを増すにつれ
てVfも低下するが、図3に示すように、Zn層とNi
層の層厚を厚くするに従って発光出力が低下するため、
発光出力の点からはあまり厚くすることは得策でなく、
前記Zn層とNi層の厚さを合わせて15nm以下とす
るのがよい。
As shown in FIG. 4, if the thickness of each of the Zn layer and the Ni layer is 1 nm or more, the Zn layer becomes uniform and the forward operating voltage Vf does not vary between elements. The effect of lowering the conventional level or lower (1.90 V or lower in FIG. 4) can be obtained, and Vf decreases as the thickness increases, but as shown in FIG.
Since the emission output decreases as the layer thickness increases,
It is not a good idea to make it too thick in terms of light output.
The total thickness of the Zn layer and the Ni layer is preferably 15 nm or less.

【0026】またZn層及びNi層の領域の内、透明導
電層の上に形成されている電極の直下にあたる部分つい
ては、Zn層及びNi層の一部を欠いた形態(図2)と
することもできる。この形態において、Zn層とNi層
が形成されていない領域は、上部電極と厳密に一致させ
る必要はなく、上部電極と中心が略合致し、且つ該電極
の0.6〜1.3倍とすることができる。
In addition, in the region of the Zn layer and the Ni layer, a portion directly below the electrode formed on the transparent conductive layer should be in a form in which a part of the Zn layer and the Ni layer is omitted (FIG. 2). You can also In this mode, the region where the Zn layer and the Ni layer are not formed does not need to be exactly aligned with the upper electrode, and the center is approximately aligned with the upper electrode, and is 0.6 to 1.3 times as large as that of the electrode. can do.

【0027】[0027]

【発明の実施の形態】以下、本発明を図示の実施形態に
基づいて説明する。以下の例は、第一導電型をn型と
し、第二導電型をp型とした例となっている。
BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be described below based on the illustrated embodiments. In the following example, the first conductivity type is n-type and the second conductivity type is p-type.

【0028】[従来例]従来例として、図5に示した構
造の発光波長630nm付近の赤色発光ダイオード用エ
ピタキシャルウェハを作製した。
[Conventional Example] As a conventional example, an epitaxial wafer for a red light emitting diode having the structure shown in FIG.

【0029】まず、n型GaAs基板1上に、MOVP
E法で、n型(Seドープ)GaAsバッファ層、n型
(Seドープ)(Al0.7Ga0.30.5In0.5P下クラ
ッド層2、アンドープ(Al0.15Ga0.850.5In0.5
P活性層3、p型(亜鉛ドープ)(Al0.7Ga0.3
0.5In0.5P上クラッド層4、を成長させ、その上にp
型(亜鉛ドープ)(Al0.7Ga0.30.5In0.5P及び
GaP電流分散層5をMOVPE成長で成長させた。
First, the MOVP is formed on the n-type GaAs substrate 1.
N-type (Se-doped) GaAs buffer layer, n-type (Se-doped) (Al 0.7 Ga 0.3 ) 0.5 In 0.5 P lower cladding layer 2, undoped (Al 0.15 Ga 0.85 ) 0.5 In 0.5 by E method
P active layer 3, p-type (zinc-doped) (Al 0.7 Ga 0.3 )
0.5 In 0.5 P upper clad layer 4 is grown, and p is grown on it.
A type (zinc-doped) (Al 0.7 Ga 0.3 ) 0.5 In 0.5 P and GaP current spreading layer 5 was grown by MOVPE growth.

【0030】次に、このエピタキシャルウェハにZnを
2nm蒸着し、Zn層6を形成した。更に前記エピタキ
シャルウェハを、上述の420℃より高い温度である5
00℃に加熱し、スプレー法にて透明導電膜8としての
ITO膜を形成した。
Next, Zn was evaporated to a thickness of 2 nm on this epitaxial wafer to form a Zn layer 6. Further, the epitaxial wafer is heated to a temperature higher than 420 ° C. 5
The ITO film was formed as the transparent conductive film 8 by heating to 00 ° C. and spraying.

【0031】エピタキシャルウェハ上面には、上部電極
として直径125μmの円形のp側電極(第二導電型チ
ップ上面電極)9を、マトリックス状に蒸着で形成し
た。p側電極9は、金・亜鉛、ニッケル、金を、それぞ
れ60nm、10nm、1000nmの順に蒸着した。
更にエピタキシャルウェハ底面には、全面にn側電極
(裏面電極)10を形成した。n側電極10は、金・ゲ
ルマニウム、ニッケル、金を、それぞれ60nm、10
nm、500nmの順に蒸着し、その後、電極の合金化
であるアロイを、窒素ガス雰囲気中430℃で5分行っ
た。
On the upper surface of the epitaxial wafer, a circular p-side electrode (second conductivity type chip upper surface electrode) 9 having a diameter of 125 μm was formed in a matrix by vapor deposition as an upper electrode. For the p-side electrode 9, gold, zinc, nickel, and gold were vapor-deposited in the order of 60 nm, 10 nm, and 1000 nm, respectively.
Further, an n-side electrode (back surface electrode) 10 was formed on the entire bottom surface of the epitaxial wafer. The n-side electrode 10 is made of gold / germanium, nickel, and gold each having a thickness of 60 nm and 10 nm.
nm and 500 nm were vapor-deposited in this order, and then alloying for alloying the electrodes was performed at 430 ° C. for 5 minutes in a nitrogen gas atmosphere.

【0032】前記ITO膜及び電極付きエピタキシャル
ウェハを、ダイシング等で加工して、チップサイズ30
0μm角の発光ダイオードチップを作製し、更にダイボ
ンディング、ワイヤボンディングを行って発光ダイオー
ドを製作した。
The ITO film and the epitaxial wafer with electrodes are processed by dicing or the like to obtain a chip size 30.
A 0 μm square light emitting diode chip was manufactured, and then die bonding and wire bonding were performed to manufacture a light emitting diode.

【0033】この従来例の発光ダイオードの発光特性を
調べた結果、発光出力は2.2mW、Vfは1.90V
〜6.07V(20mA通電時)であった。このように
Vfの値に1.90V〜6.07Vとバラツキがあるの
は、この従来例の発光ダイオードの場合、透明導電膜を
500℃(つまり420℃以上)で形成しているため、
エピタキシャルウェハ最上層と透明導電膜間に形成した
Zn膜が球状化してしまい、エピタキシャルウェハ面内
でZn膜が無い部分ができ、このため半導体発光素子の
中に、非常にVfが高いものができると考えられる。
As a result of examining the light emitting characteristics of the light emitting diode of the conventional example, the light emitting output is 2.2 mW and Vf is 1.90 V.
It was -6.07V (at the time of 20 mA energization). The Vf value thus varies from 1.90V to 6.07V because the transparent conductive film is formed at 500 ° C. (that is, 420 ° C. or higher) in the case of the light emitting diode of this conventional example.
The Zn film formed between the uppermost layer of the epitaxial wafer and the transparent conductive film becomes spherical, and a portion without the Zn film is formed in the plane of the epitaxial wafer. Therefore, a semiconductor light emitting device having a very high Vf can be formed. it is conceivable that.

【0034】また、エピタキシャルウェハにZn系以外
の金属を2nm蒸着してみたが、この場合は、発光出力
が2.2mW、Vfは2.01〜2.05V(20mA
通電時)であり、やはりVfの値にバラツキが生じた。
A metal other than Zn was vapor-deposited on the epitaxial wafer to a thickness of 2 nm. In this case, the emission output was 2.2 mW and Vf was 2.01 to 2.05 V (20 mA).
(When energized), and the value of Vf also varied.

【0035】[実施例1]次に、実施例1として、図1
に示した構造の発光波長630nm付近の赤色発光ダイ
オード用エピタキシャルウェハを作製した。
[Embodiment 1] Next, as Embodiment 1, FIG.
An epitaxial wafer for a red light emitting diode having an emission wavelength of about 630 nm having the structure shown in was prepared.

【0036】n型GaAs基板1上に、MOVPE法
で、n型(Seドープ)GaAsバッファ層、n型(S
eドープ)(Al0.7Ga0.30.5In0.5P下クラッド
層2、アンドープ(Al0.15Ga0.850.5In0.5P活
性層3、p型(亜鉛ドープ)(Al0.7Ga0.30.5
0.5P上クラッド層4、を成長させ、その上にp型
(亜鉛ドープ)(Al0.7Ga0.30.5In0.5P及びG
aP電流分散層5をMOVPE成長で成長させた。
An n-type (Se-doped) GaAs buffer layer and an n-type (S) are formed on the n-type GaAs substrate 1 by MOVPE.
e-doped) (Al 0.7 Ga 0.3 ) 0.5 In 0.5 P lower cladding layer 2, undoped (Al 0.15 Ga 0.85 ) 0.5 In 0.5 P active layer 3, p-type (zinc-doped) (Al 0.7 Ga 0.3 ) 0.5 I
An n 0.5 P upper cladding layer 4 is grown, and p-type (zinc-doped) (Al 0.7 Ga 0.3 ) 0.5 In 0.5 P and G are grown thereon.
The aP current dispersion layer 5 was grown by MOVPE growth.

【0037】次に、このエピタキシャルウェハにZnを
1nm蒸着してZn層6を形成し、更にNiを1nm蒸
着してNi層7を形成した。更に前記エピタキシャルウ
ェハを500℃に加熱し、スプレー法にて透明導電膜8
としてのITO膜を形成した。
Next, Zn was evaporated to a thickness of 1 nm on the epitaxial wafer to form a Zn layer 6, and Ni was further evaporated to a thickness of 1 nm to form a Ni layer 7. Furthermore, the epitaxial wafer is heated to 500 ° C., and the transparent conductive film 8 is sprayed.
An ITO film was formed.

【0038】エピタキシャルウェハ上面には、上部電極
として直径125μmの円形のp側電極(第二導電型チ
ップ上面電極)9を、マトリックス状に蒸着で形成し
た。p側電極9は、金・亜鉛、ニッケル、金を、それぞ
れ60nm、10nm、1000nmの順に蒸着した。
更にエピタキシャルウェハ底面には、全面にn側電極
(裏面電極)10を形成した。n側電極10は、金・ゲ
ルマニウム、ニッケル、金を、それぞれ60nm、10
nm、500nmの順に蒸着し、その後、電極の合金化
であるアロイを、窒素ガス雰囲気中430℃で5分行っ
た。
On the upper surface of the epitaxial wafer, a circular p-side electrode (second conductivity type chip upper surface electrode) 9 having a diameter of 125 μm was formed as an upper electrode by vapor deposition in a matrix. For the p-side electrode 9, gold, zinc, nickel, and gold were vapor-deposited in the order of 60 nm, 10 nm, and 1000 nm, respectively.
Further, an n-side electrode (back surface electrode) 10 was formed on the entire bottom surface of the epitaxial wafer. The n-side electrode 10 is made of gold / germanium, nickel, and gold each having a thickness of 60 nm and 10 nm.
nm and 500 nm were vapor-deposited in this order, and then alloying for alloying the electrodes was performed at 430 ° C. for 5 minutes in a nitrogen gas atmosphere.

【0039】前記ITO膜及び電極付きエピタキシャル
ウェハを、ダイシング等で加工して、チップサイズ30
0μm角の発光ダイオードチップを作製し、更にダイボ
ンディング、ワイヤボンディングを行って発光ダイオー
ドを製作した。
The ITO film and the epitaxial wafer with electrodes are processed by dicing or the like to obtain a chip size of 30.
A 0 μm square light emitting diode chip was manufactured, and then die bonding and wire bonding were performed to manufacture a light emitting diode.

【0040】この実施例1の発光ダイオードの発光特性
を調べた結果、発光出力は2.2mWであり、Vfは
1.90±0.02V(20mA通電時)と一定してい
た。つまり、この実施例1の発光ダイオードの場合、透
明導電膜を500℃(つまり420℃以上)で形成して
いるにも拘わらず、半導体発光素子の素子間バラツキが
なく、全ての素子のVfが1.90Vを中心とする±
0.02Vの偏差の中に収まっており、特にVfの高い
素子が発生するということはなかった。また、透明導電
膜の形成温度を500℃(つまり420℃以上)と高く
しているため、透明導電膜も低抵抗のものとなった。
As a result of examining the light emitting characteristics of the light emitting diode of Example 1, the light emitting output was 2.2 mW, and Vf was constant at 1.90 ± 0.02 V (at a current of 20 mA). That is, in the case of the light emitting diode of Example 1, even though the transparent conductive film is formed at 500 ° C. (that is, 420 ° C. or higher), there is no variation between elements of the semiconductor light emitting element, and Vf of all elements is Centered around 1.90V ±
The deviation was within 0.02 V, and there was no occurrence of an element with a particularly high Vf. Further, since the formation temperature of the transparent conductive film is as high as 500 ° C. (that is, 420 ° C. or higher), the transparent conductive film also has low resistance.

【0041】[実施例2]実施例2として、図2のよう
な構造の、発光波長630nm付近の赤色発光ダイオー
ド用エピタキシャルウェハを作製した。これは上記Zn
層及びNi層の領域の内、透明導電層の上に形成されて
いる電極の直下にあたる部分ついて、Zn層及びNi層
の一部を欠いた形態としたものである。
Example 2 As Example 2, an epitaxial wafer for a red light emitting diode having a structure as shown in FIG. 2 and an emission wavelength of around 630 nm was produced. This is the above Zn
In the region of the layer and the Ni layer, a portion directly below the electrode formed on the transparent conductive layer is formed by omitting a part of the Zn layer and the Ni layer.

【0042】MOVPE法によるエピタキシャル成長方
法、エピタキシャル層1〜5を有するエピタキシャル構
造等は、基本的に前記の従来例と同じとし、またITO
膜形成方法、電極形成方法及び電極形状も基本的に前記
の従来例と同じとした。更にプロセス加工及びワイヤボ
ンディング工程も、前記の実施例1と同じとした。
The epitaxial growth method by the MOVPE method, the epitaxial structure having the epitaxial layers 1 to 5 and the like are basically the same as those in the above-mentioned conventional example, and ITO is used.
The film forming method, the electrode forming method, and the electrode shape were basically the same as those in the above-mentioned conventional example. Further, the process processing and the wire bonding process were the same as those in the first embodiment.

【0043】上記エピタキシャル層1〜5を有するエピ
タキシャルウェハに対し、フォトリソにより、レジスト
マスクをマトリックス状に形成した。レジストマスクが
ある部分の大きさは、直径125μmの円形である。
A resist mask was formed in a matrix on the epitaxial wafer having the above-mentioned epitaxial layers 1 to 5 by photolithography. The size of the portion having the resist mask is a circle having a diameter of 125 μm.

【0044】このレジストマスク付エピタキシャルウェ
ハに、蒸着法でZn層6を1nm、更にその上にNi層
7を1nm形成し、更にレジスト膜を除去することで、
マトリックス状に直径125μmのZn層6とNi層7
が形成されていない金属層付きエピタキシャルウェハを
製作した。
On this epitaxial wafer with a resist mask, a Zn layer 6 having a thickness of 1 nm and a Ni layer 7 having a thickness of 1 nm are formed on the epitaxial wafer by a vapor deposition method, and the resist film is removed.
Zn layer 6 and Ni layer 7 having a diameter of 125 μm in a matrix
An epitaxial wafer with a metal layer in which no ridge was formed was manufactured.

【0045】その後、透明導電膜8としてのITO膜を
形成し、そのITO膜上に、直径1251μmの円形の
p側電極9を、Zn層6及びNi層7が無い部分の中心
と略合致させる様に、マトリックス状に蒸着で形成し
た。p側電極9は、金・亜鉛、ニッケル、金を、それぞ
れ60nm、10nm、1000nmの順に蒸着した。
更にエピタキシャルウェハ底面には、全面にn側電極1
0を形成し、n側電極10は、金・ゲルマニウム、ニッ
ケル、金を、それぞれ60nm、10nm、500nm
の順に蒸着し、その後、電極の合金化であるアロイを、
窒素ガス雰囲気中430℃で5分行った。
After that, an ITO film as the transparent conductive film 8 is formed, and the circular p-side electrode 9 having a diameter of 1251 μm is substantially aligned with the center of the portion where the Zn layer 6 and the Ni layer 7 are not formed on the ITO film. Similarly, a matrix was formed by vapor deposition. For the p-side electrode 9, gold, zinc, nickel, and gold were vapor-deposited in the order of 60 nm, 10 nm, and 1000 nm, respectively.
Further, on the bottom surface of the epitaxial wafer, the n-side electrode 1
0, and the n-side electrode 10 is made of gold / germanium, nickel, and gold of 60 nm, 10 nm, and 500 nm, respectively.
Then, the alloy that is the alloying of the electrodes is deposited.
It was performed at 430 ° C. for 5 minutes in a nitrogen gas atmosphere.

【0046】前記ITO膜及び電極付きエピタキシャル
ウェハを、ダイシング等で加工して、チップサイズ30
0μm角の発光ダイオードチップを作製した。
The ITO film and the epitaxial wafer with electrodes are processed by dicing or the like to obtain a chip size of 30.
A 0 μm square light emitting diode chip was produced.

【0047】この実施例2の発光ダイオードの発光特性
を調べた結果、発光出力は2.6mWであり、Vfは
1.92±0.02V(20mA通電時)と一定してい
た。つまり、この実施例2の発光ダイオードの場合、透
明導電膜を500℃(つまり420℃以上)で形成して
いるにも拘わらず、半導体発光素子の素子間バラツキが
なく、全ての素子のVfが±0.02Vの偏差の中に収
まっており、特にVfの高い素子が発生するということ
はなかった。また、透明導電膜の形成温度を500℃
(つまり420℃以上)と高くしているため、透明導電
膜も低抵抗のものとなった。
As a result of examining the light emission characteristics of the light emitting diode of this Example 2, the light emission output was 2.6 mW, and Vf was constant at 1.92 ± 0.02 V (at 20 mA energization). That is, in the case of the light emitting diode of Example 2, although the transparent conductive film is formed at 500 ° C. (that is, 420 ° C. or higher), there is no variation between the semiconductor light emitting elements, and Vf of all the elements is The deviation was within ± 0.02V, and there was no occurrence of an element with a particularly high Vf. In addition, the formation temperature of the transparent conductive film is 500 ° C.
Since it is as high as 420 ° C. or higher, the transparent conductive film also has low resistance.

【0048】[比較例]比較例として、図1のような構
造の、発光波長630nm付近の赤色発光ダイオード用
エピタキシャルウェハを作製した。
Comparative Example As a comparative example, an epitaxial wafer for a red light emitting diode having a structure as shown in FIG. 1 and having an emission wavelength of about 630 nm was produced.

【0049】MOVPE法によるエピタキシャル成長方
法、エピタキシャル層1〜5を有するエピタキシャル構
造等は、基本的に前記の実施例1と同じとし、またIT
O膜形成方法、電極形成方法及び電極形状も基本的に前
記の実施例1と同じとした。また更にプロセス加工も、
実施例1と同じとした。
The epitaxial growth method by the MOVPE method, the epitaxial structure having the epitaxial layers 1 to 5, and the like are basically the same as those in the first embodiment, and IT
The O film forming method, the electrode forming method, and the electrode shape were basically the same as those in the first embodiment. In addition, process processing,
Same as Example 1.

【0050】ただし、実施例1の場合と異なり、半導体
層とITO膜の間に形成する金属については、上記Zn
層6及びNi層7の代わりに、Mg、Be、Ge、Ni
及びそれらのAu化合物として、発光ダイオードを製作
した。
However, unlike the case of Example 1, regarding the metal formed between the semiconductor layer and the ITO film, the above-mentioned Zn is used.
Instead of the layer 6 and the Ni layer 7, Mg, Be, Ge, Ni
And a light emitting diode was manufactured as the Au compound thereof.

【0051】その結果、発光ダイオードの発光特性は、
順方向動作電圧(20mA通電時)が、それぞれ1.9
5V、1.94V、1.97V、1.94Vであり、そ
れらのAu化合物でも2.0V以下であった。また発光
出力は、上記構造全て2.5mW以上であった。
As a result, the light emitting characteristics of the light emitting diode are
Forward operating voltage (at 20mA current) is 1.9 each
It was 5V, 1.94V, 1.97V, 1.94V, and those Au compounds also had 2.0V or less. Further, the light emission output was 2.5 mW or more in all of the above structures.

【0052】上記実施例と従来例及び比較例との対比か
ら明らかなように、本発明に従って半導体層とITO膜
の間にZn層6及びNi層7を介在させることにより、
高出力でVfが低く、且つ素子間でのVfバラツキの非
常に小さいITO膜付きLEDができる。これによりL
ED用のエピタキシャル層の膜厚は五分の一から数十分
の一まで薄くすることができる。LEDを構成するエピ
タキシャルウェハの中で電流分散膜の厚さがもっとも厚
かったためである。これにより、エピタキシャルウェハ
の価格を大幅に低くすることができた。
As is clear from the comparison between the above-mentioned examples and the conventional examples and the comparative examples, by interposing the Zn layer 6 and the Ni layer 7 between the semiconductor layer and the ITO film according to the present invention,
An LED with an ITO film having a high output and a low Vf and a very small Vf variation between elements can be obtained. This gives L
The thickness of the epitaxial layer for ED can be reduced from one fifth to several tenths. This is because the current spreading film has the largest thickness in the epitaxial wafer that constitutes the LED. As a result, the cost of the epitaxial wafer could be reduced significantly.

【0053】上記実施例では、Zn層6及びNi層7の
厚さをそれぞれ1nmとしたが、これ以外の値を採るこ
とができる。ただし、半導体層とITO膜の間に挿入し
たZn層6が薄すぎると、Znの効果が薄れ、Vfが高
くなる。またNi層7が薄すぎるとZn層が均一になら
ず、Vfがばらつく。さらに半導体層とITO膜の間に
挿入したZn層6とNi層7の全厚が厚すぎると、金属
層での光吸収が大きくなることから、発光出力が低くな
る。このため、Zn層、Ni層とZn層とNi層の合計
膜厚には、最適値がある。
In the above embodiment, the thicknesses of the Zn layer 6 and the Ni layer 7 are set to 1 nm, but other values can be adopted. However, if the Zn layer 6 inserted between the semiconductor layer and the ITO film is too thin, the effect of Zn is weakened and Vf becomes high. If the Ni layer 7 is too thin, the Zn layer will not be uniform and Vf will vary. Further, if the total thickness of the Zn layer 6 and the Ni layer 7 inserted between the semiconductor layer and the ITO film is too thick, the light absorption in the metal layer becomes large, and the light emission output becomes low. Therefore, the total thickness of the Zn layer, the Ni layer, the Zn layer, and the Ni layer has an optimum value.

【0054】図3にZn層とNi層の総厚と光出力の関
係を、また図4にZn層とNi層の総厚とVfの関係を
示す。
FIG. 3 shows the relationship between the total thickness of the Zn layer and Ni layer and the light output, and FIG. 4 shows the relationship between the total thickness of the Zn layer and Ni layer and Vf.

【0055】Zn層とNi層の厚さは、図4に示すよう
に、Zn層及びNi層共にそれぞれ1nm以上であれ
ば、Zn層が均一化し、順方向動作電圧Vfを素子間バ
ラツキなしに、従来並に低くする効果(図4で1.90
V以下)が得られ、厚さを増すにつれてVfも低下す
る。一方、図3に示すように、Zn層とNi層を厚くす
るに従って発光出力が低下するため、発光出力の点から
はあまり厚くすることは得策でなく、前記Zn層とNi
層の厚さを合わせて15nm以下、好ましくは10nm
以下、更に好ましくは7.5nm以下とするのがよい。
As shown in FIG. 4, if the thickness of each of the Zn layer and the Ni layer is 1 nm or more, the Zn layer becomes uniform and the forward operating voltage Vf does not vary between elements. , The effect of making it as low as conventional (1.90 in FIG. 4)
V or less) is obtained, and Vf decreases as the thickness increases. On the other hand, as shown in FIG. 3, since the light emission output decreases as the Zn layer and the Ni layer become thicker, it is not a good idea to make it too thick in terms of light emission output.
The total layer thickness is 15 nm or less, preferably 10 nm
Hereafter, it is more preferable that the thickness is 7.5 nm or less.

【0056】上記実施例では、表面電極と金属層の形状
は、円形であるが、異形状、例えば四角、菱形、多角形
等としても、同様の効果が得られる。
In the above embodiment, the surface electrode and the metal layer have a circular shape. However, the same effect can be obtained even if the surface electrode and the metal layer have different shapes such as a square, a rhombus, and a polygon.

【0057】また、従来例及び実施例での透明導電膜形
成方法は、スプレー法で形成したものであるが、その他
の透明導電膜形成方法、例えばスパッタ法や蒸着法等で
形成しても、同様の効果を得ることができる。
Further, although the transparent conductive film forming method in the conventional example and the embodiment is formed by the spray method, it may be formed by other transparent conductive film forming methods such as the sputtering method and the vapor deposition method. The same effect can be obtained.

【0058】[0058]

【発明の効果】以上説明したように本発明によれば、電
流分散膜として金属酸化膜の透明導電膜を用いた構造の
LEDにおいて、エピタキシャルウェハの表面に順方向
動作電圧Vfを低くするための金属層としてZnとNi
の積層構造を設けているので、これにより半導体発光素
子の素子間バラツキ、特に順方向動作電圧Vfの高い素
子の発生をなくし、且つ透明導電膜の形成温度を高くし
て低抵抗の透明導電膜の形成を可能とし、以て順方向動
作電圧Vfが低く、且つバラツキが少ない高発光出力の
透明電極付LEDを得ることができる。
As described above, according to the present invention, in the LED having the structure in which the transparent conductive film of the metal oxide film is used as the current spreading film, it is possible to reduce the forward operating voltage Vf on the surface of the epitaxial wafer. Zn and Ni as metal layers
Since the laminated structure is provided, the variation in the elements of the semiconductor light emitting element, particularly the generation of the element having a high forward operation voltage Vf, is eliminated, and the formation temperature of the transparent conductive film is increased to reduce the resistance of the transparent conductive film. Therefore, it is possible to obtain an LED with a transparent electrode having a low forward operating voltage Vf and a small variation and a high light emission output.

【0059】また、高出力であり順方向動作電圧Vfが
低く、且つ素子間でのVfバラツキの非常に小さいIT
O膜付きLEDができる様になったことから、LED用
のエピタキシャル層の膜厚は五分の一から数十分の一ま
で薄くすることができるようになった。LEDを構成す
るエピタキシャルウェハの中で電流分散膜の厚さがもっ
とも厚かったためである。これにより、エピタキシャル
ウェハの価格を大幅に低くすることができた。
In addition, IT has a high output, a low forward operation voltage Vf, and a very small variation in Vf between elements.
Since it has become possible to form an LED with an O film, it has become possible to reduce the thickness of the epitaxial layer for an LED from one fifth to several tenths. This is because the current spreading film has the largest thickness in the epitaxial wafer that constitutes the LED. As a result, the cost of the epitaxial wafer could be reduced significantly.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の実施例1にかかるLEDの断面図であ
る。
FIG. 1 is a sectional view of an LED according to a first embodiment of the present invention.

【図2】本発明の実施側2にかかるLEDの断面図であ
る。
FIG. 2 is a sectional view of an LED according to an implementation side 2 of the present invention.

【図3】ZnとNi層の膜厚と発光出力との関係を示す
グラフである。
FIG. 3 is a graph showing the relationship between the film thickness of Zn and Ni layers and the light emission output.

【図4】ZnとNi層の膜厚とVfとの関係を示すグラ
フである。
FIG. 4 is a graph showing the relationship between the film thickness of Zn and Ni layers and Vf.

【図5】従来例にかかるLEDの断面図である。FIG. 5 is a sectional view of an LED according to a conventional example.

【符号の説明】[Explanation of symbols]

1 n型GaAs基板(第一導電型基板) 2 n型下クラッド層(第一導電型クラッド層) 3 活性層 4 p型上クラッド層(第二導電型クラッド層) 5 p型電流分散層(第二導電型電流分散層) 6 Zn層 7 Ni層 8 透明導電膜 1 n-type GaAs substrate (first conductivity type substrate) 2 n-type lower cladding layer (first conductivity type cladding layer) 3 Active layer 4 p-type upper clad layer (second conductivity type clad layer) 5 p-type current spreading layer (second conductivity type current spreading layer) 6 Zn layer 7 Ni layer 8 Transparent conductive film

Claims (8)

【特許請求の範囲】[Claims] 【請求項1】第一導電型の基板の上に、活性層を第一導
電型のクラッド層と第二導電型のクラッド層とで挟んだ
発光部を形成し、その上に金属酸化膜からなる透明導電
層を形成し、前記透明導電層の表面の一部に上部電極を
形成し、第一導電型の基板の発光部層が形成された反対
側の面に、全面又は部分的に電極を形成した半導体発光
素子において、 前記第二導電型のクラッド層と前記透明導電層の間に、
Zn層とNi層が順次積層されていることを特徴とする
半導体発光素子。
1. A light-emitting portion, in which an active layer is sandwiched between a first-conductivity-type cladding layer and a second-conductivity-type cladding layer, is formed on a first-conductivity-type substrate, and a metal oxide film is formed on the light-emitting portion. Forming a transparent conductive layer, and forming an upper electrode on a part of the surface of the transparent conductive layer, and entirely or partly forming an electrode on the surface of the first conductivity type substrate opposite to the surface on which the light emitting section layer is formed. In the semiconductor light emitting element having formed, between the second conductive type clad layer and the transparent conductive layer,
A semiconductor light emitting device, characterized in that a Zn layer and a Ni layer are sequentially laminated.
【請求項2】請求項1に記載の半導体発光素子におい
て、 前記発光部と前記Zn層との間に、第二導電型の電流分
散層が形成されていることを特徴とする半導体発光素
子。
2. The semiconductor light emitting device according to claim 1, wherein a current diffusion layer of a second conductivity type is formed between the light emitting portion and the Zn layer.
【請求項3】請求項1又は2に記載の半導体発光素子に
おいて、 前記透明導電層の上に形成された電極の直下にあたる部
分の一部には、順次積層された前記Zn層とNi層が形
成されていないことを特徴とする半導体発光素子。
3. The semiconductor light emitting device according to claim 1, wherein the Zn layer and the Ni layer, which are sequentially stacked, are formed in a part of a portion immediately below the electrode formed on the transparent conductive layer. A semiconductor light emitting device characterized by being not formed.
【請求項4】請求項1〜3のいずれかに記載の半導体発
光素子において、 前記Zn層とNi層の厚さがそれぞれ1nm以上であ
り、前記Zn層とNi層の厚さが合わせて15nm以下
であることを特徴とする半導体発光素子。
4. The semiconductor light emitting device according to claim 1, wherein the Zn layer and the Ni layer each have a thickness of 1 nm or more, and the Zn layer and the Ni layer have a total thickness of 15 nm. A semiconductor light emitting device characterized by the following:
【請求項5】請求項1〜4のいずれかに記載の半導体発
光素子において、 前記上部電極が円形、角形又は円形の角形に突起を付け
た形状を具備することを特徴とする半導体発光素子。
5. The semiconductor light emitting device according to claim 1, wherein the upper electrode has a circular shape, a rectangular shape, or a shape in which protrusions are formed in a rectangular shape.
【請求項6】請求項3に記載の半導体発光素子におい
て、 順次積層された前記Zn層とNi層が形成されていない
領域は、上部電極と中心が略合致し、且つ前記電極の
0.6〜1.3倍であることを特徴とする半導体発光素
子。
6. The semiconductor light emitting device according to claim 3, wherein the regions where the Zn layer and the Ni layer, which are sequentially stacked, are not substantially aligned with the center of the upper electrode, and the center of the electrode is 0.6. The semiconductor light emitting device is characterized by being 1.3 times.
【請求項7】請求項1〜6のいずれかに記載の半導体発
光素子において、 前記基板がGaAsから成り、前記発光部がAlGaI
nP又はGaInPから成ることを特徴とする半導体発
光素子。
7. The semiconductor light emitting device according to claim 1, wherein the substrate is made of GaAs, and the light emitting portion is AlGaI.
A semiconductor light-emitting device comprising nP or GaInP.
【請求項8】請求項1〜6のいずれかに記載の半導体発
光素子を製造する方法において、透明導電層の形成温度
を420℃以上とすることを特徴とする半導体発光素子
の製造方法。
8. A method for manufacturing a semiconductor light emitting device according to claim 1, wherein the transparent conductive layer is formed at a temperature of 420 ° C. or higher.
JP2002052512A 2002-02-28 2002-02-28 Semiconductor light emitting element and its fabricating method Withdrawn JP2003258304A (en)

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Publication Number Publication Date
JP2003258304A true JP2003258304A (en) 2003-09-12

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Country Link
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100428509C (en) * 2004-10-18 2008-10-22 三垦电气株式会社 Semiconductor luminescent device and manufacturing method thereof
JP2011199319A (en) * 2003-05-07 2011-10-06 Samsung Led Co Ltd Thin-film electrode and method for manufacturing the same
JP2013004925A (en) * 2011-06-21 2013-01-07 Disco Abrasive Syst Ltd Processing method of optical device wafer

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011199319A (en) * 2003-05-07 2011-10-06 Samsung Led Co Ltd Thin-film electrode and method for manufacturing the same
CN100428509C (en) * 2004-10-18 2008-10-22 三垦电气株式会社 Semiconductor luminescent device and manufacturing method thereof
JP2013004925A (en) * 2011-06-21 2013-01-07 Disco Abrasive Syst Ltd Processing method of optical device wafer

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