JP2003255916A - Display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display device which can have its display quality improved and its frame made small. <P>SOLUTION: A signal line driving circuit has a latch circuit which latches digital pixel data, a D/A converter which converts the latch output of the latch circuit into an analog video signal, an AMP 17 which amplifies the analog vide signal generated by the D/A converter, and a signal line selecting circuit 18 which selects a signal line as the supply destination of the analog video signal amplified by the AMP 17, which has odd numbers of cascaded inverters IV1 to IV3, capacitor elements C4 and C5 connected between the stages of the inverters and between the input terminal of the inverter of the starting stage and the output terminal of the final stage, a 1st power supply line XAVDD 1 which supplies a source voltage to the inverter INV1 of the starting stage, and a 2nd power supply line XAVDD2 which supplies the source voltage to the inverters other than the inverter of the starting stage. Thus only the power supply line of the starting-stage inverter is separated to improve the precision of the AMP 17. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a D / A converter for converting digital pixel data into an analog video signal, a D / A.
The present invention relates to a display device in which an amplifier for amplifying the output of a converter and a signal line selection circuit are formed integrally with a pixel array section on an insulating substrate.

[0002]

2. Description of the Related Art A liquid crystal display device in which a pixel array portion and a driving circuit are formed on the same glass substrate has been actively developed. By forming the pixel array section and the driving circuit on the same glass substrate, the liquid crystal display device as a whole can be made lighter, thinner and smaller, and can be widely used as a display device for mobile devices such as mobile phones and notebook computers.

In this type of liquid crystal display device integrated with a driving circuit, a TFT is formed of polysilicon or the like on a glass substrate, and both the pixel array section and the driving circuit are formed using these TFTs (thin film transistors).

[0004]

However, since the TFT formed on the glass substrate does not operate at a very high speed, various circuit arrangements are required to form a drive circuit. In addition, a TFT with uniform characteristics on a glass substrate
It is technically difficult to form
Due to the difference in characteristics, there is a possibility that display quality such as display unevenness may deteriorate.

Further, when the pixel array section and the drive circuit are formed on the same glass substrate, there is a problem that the ratio of the pixel array section to the area of the glass substrate is relatively small and the frame is large.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a display device capable of improving display quality.

Another object of the present invention is to provide a display device capable of reducing the frame.

[0008]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention provides a signal line and a scanning line vertically and horizontally arranged on an insulating substrate and near each intersection of the signal line and the scanning line. A display device comprising: a display element to be formed; a scanning line drive circuit for driving the scanning line; and a signal line drive circuit formed on the insulating substrate for driving the signal line, wherein the signal line drive circuit is provided. Is a latch circuit for latching digital pixel data, a D / A converter for converting a latch output of the latch circuit into an analog video signal, and the D / A
An amplifier for amplifying the analog video signal converted by the converter; and a signal line selection circuit for selecting a signal line to which the analog video signal amplified by the amplifier is supplied, the amplifier being connected in cascade. A first capacitor element connected to each of the odd-numbered inverters, between the stages of the inverters, and between the input terminal of the first-stage inverter and the output terminal of the last-stage inverter; It has a first power supply line for supplying a power supply voltage to the inverter and a second power supply line for supplying a power supply voltage to the inverters other than the first stage.

Further, according to the present invention, a signal line and a scanning line vertically and horizontally arranged on an insulating substrate, a display element formed near each intersection of the signal line and the scanning line, and the scanning line are driven. In a display device including a scanning line drive circuit and a signal line drive circuit formed on the insulating substrate and driving the signal line, the signal line drive circuit includes a latch circuit for latching digital pixel data, and A D / A converter for converting the latch output of the latch circuit into an analog video signal, an amplifier for amplifying the analog video signal converted by the D / A converter, and a supply destination of the analog video signal amplified by the amplifier And a signal line selection circuit for selecting a signal line, wherein the signal line selection circuit has, for each signal line, a plurality of analog switches connected in parallel, and the signal line selection circuit corresponds to the same signal line. Compound The analog switches are on-off controlled in the same direction.

Further, according to the present invention, a signal line and a scanning line vertically and horizontally arranged on an insulating substrate, a display element formed near each intersection of the signal line and the scanning line, and the scanning line are driven. In a display device including a scanning line drive circuit and a signal line drive circuit formed on the insulating substrate to drive the signal lines, at least a part of the analog switches on the insulating substrate are connected in series, respectively. A punch-through compensation analog switch that is on / off controlled in the opposite direction to the corresponding analog switch is provided, and the punch-through compensation analog switch includes a pMOS transistor connected in parallel.
It has an nMOS transistor and the source and
The drains are short-circuited.

Further, according to the present invention, a signal line and a scanning line which are vertically and horizontally arranged on an insulating substrate, a display element formed near each intersection of the signal line and the scanning line, and the scanning line are driven. In a display device including a scanning line drive circuit and a signal line drive circuit formed on the insulating substrate and driving the signal line, the signal line drive circuit includes a latch circuit for latching digital pixel data, and A D / A converter for converting the latch output of the latch circuit into an analog video signal, an amplifier for amplifying the analog video signal converted by the D / A converter, and a supply destination of the analog video signal amplified by the amplifier And a signal line selection circuit that selects a signal line that is an amplifier, the amplifier includes an odd number of inverters connected in cascade, a stage between the inverters, and an input terminal and a final stage of the first stage inverter. A first capacitor element connected to each of the output terminals of the inverter, and each of the odd number of inverters, and switches whether to short-circuit between the input and output terminals of the corresponding inverter. It has a possible switching circuit and a second capacitor element inserted between at least one input / output terminal of the second and subsequent inverters.

Further, according to the present invention, a signal line and a scanning line vertically and horizontally arranged on an insulating substrate, a display element formed near each intersection of the signal line and the scanning line, and the scanning line are driven. In a display device including a scanning line drive circuit and a signal line drive circuit formed on the insulating substrate and driving the signal line, the signal line drive circuit includes a latch circuit for latching digital pixel data, and A D / A converter for converting the latch output of the latch circuit into an analog video signal, an amplifier for amplifying the analog video signal converted by the D / A converter, and a supply destination of the analog video signal amplified by the amplifier And a signal line selection circuit that selects a signal line that is an amplifier, the amplifier includes an odd number of inverters connected in cascade, a stage between the inverters, and an input terminal and a final stage of the first stage inverter. A first capacitor element connected to each of the output terminals of the inverter, and each of the odd number of inverters, and switches whether to short-circuit between the input and output terminals of the corresponding inverter. It has a possible switching circuit, an output terminal of at least one of the inverters in the second and subsequent stages, and a second capacitor element inserted between the output terminal of the inverter in the preceding stage.

Further, according to the present invention, a signal line and a scanning line which are vertically and horizontally arranged on an insulating substrate, a display element formed near each intersection of the signal line and the scanning line, and the scanning line are driven. In a display device including a scanning line drive circuit and a signal line drive circuit formed on the insulating substrate and driving the signal line, the signal line drive circuit includes a latch circuit for latching digital pixel data, and A D / A converter for converting the latch output of the latch circuit into an analog video signal, an amplifier for amplifying the analog video signal converted by the D / A converter, and a supply destination of the analog video signal amplified by the amplifier A signal line selection circuit that selects a signal line that is, and a power supply line for the amplifier formed on the insulating substrate,
And a power supply line of the amplifier is arranged so as to be superposed on a common electrode on a counter substrate which is arranged to face the insulating substrate.

Further, according to the present invention, a signal line and a scanning line which are vertically and horizontally arranged on an insulating substrate, a display element formed near each intersection of the signal line and the scanning line, and the scanning line are driven. In a display device including a scanning line drive circuit and a signal line drive circuit formed on the insulating substrate and driving the signal line, the signal line drive circuit includes a latch circuit for latching digital pixel data, and A D / A converter for converting the latch output of the latch circuit into an analog video signal, an amplifier for amplifying the analog video signal converted by the D / A converter, and a supply destination of the analog video signal amplified by the amplifier And a signal line selection circuit that selects a signal line that is an amplifier, the amplifier includes an odd number of inverters connected in cascade, a stage between the inverters, and an input terminal and a final stage of the first stage inverter. A first capacitor element connected to each of the output terminals of the inverter, and each of the odd number of inverters, and switches whether to short-circuit between the input and output terminals of the corresponding inverter. A switching circuit capable of switching, and at least a part of the first capacitor element connected to an inverter other than the first-stage inverter is overlapped with a common electrode on a counter substrate which is arranged to face the insulating substrate. Is arranged as.

Further, according to the present invention, a signal line and a scanning line which are vertically and horizontally arranged on an insulating substrate, a display element formed near each intersection of the signal line and the scanning line, and the scanning line are driven. In a display device including a scanning line drive circuit and a signal line drive circuit formed on the insulating substrate and driving the signal line, the signal line drive circuit includes a latch circuit for latching digital pixel data, and A D / A converter for converting the latch output of the latch circuit into an analog video signal, an amplifier for amplifying the analog video signal converted by the D / A converter, and a supply destination of the analog video signal amplified by the amplifier And a signal line selection circuit that selects a signal line that is: Rcom <predetermined coefficient × ON period of the signal line selection circuit / (auxiliary capacity Capacity) / simultaneous write signal line number between the total amount / the common electrode and the insulating substrate is set to satisfy the relationship.

Further, according to the present invention, a signal line and a scanning line which are vertically and horizontally arranged on an insulating substrate, a display element formed near each intersection of the signal line and the scanning line, and the scanning line are driven. In a display device including a scanning line drive circuit and a signal line drive circuit formed on the insulating substrate and driving the signal line, the signal line drive circuit includes a latch circuit for latching digital pixel data, and A D / A converter for converting the latch output of the latch circuit into an analog video signal, an amplifier for amplifying the analog video signal converted by the D / A converter, and a supply destination of the analog video signal amplified by the amplifier And a signal line selection circuit that selects a signal line that is: Rcs <predetermined coefficient × on period of the signal line selection circuit / ( Auxiliary capacity Of the total amount / capacitance between the common electrode and the insulating substrate) / the number of simultaneous write signal lines.

Further, according to the present invention, a signal line and a scanning line which are vertically and horizontally arranged on an insulating substrate, a display element formed near each intersection of the signal line and the scanning line, and the scanning line are driven. In a display device including a scanning line drive circuit and a signal line drive circuit formed on the insulating substrate and driving the signal lines, a counter substrate that is arranged facing the insulating substrate and has a common electrode is formed. The signal line drive circuit includes a latch circuit for latching digital pixel data, a D / A converter for converting a latch output of the latch circuit into an analog video signal, and an analog converted by the D / A converter. An amplifier for amplifying a video signal, and a signal line selection circuit for selecting a signal line to which the analog video signal amplified by the amplifier is supplied are provided. It can be performed more accurately than the gain adjustment in degrees region and the low luminance region.

Further, according to the present invention, a signal line and a scanning line which are arranged in rows and columns on an insulating substrate, a display element formed near each intersection of the signal line and the scanning line, and the scanning line are driven. In a display device including a scanning line drive circuit and a signal line drive circuit formed on the insulating substrate and driving the signal line, the signal line drive circuit includes a latch circuit for latching digital pixel data, and A D / A converter for converting the latch output of the latch circuit into an analog video signal, an amplifier for amplifying the analog video signal converted by the D / A converter, and a supply destination of the analog video signal amplified by the amplifier And a signal line selection circuit for selecting a signal line, the amplifier being connected in cascade between an odd number of inverters and a first line connected between the stages of the inverters.
An analog switch and a second capacitor element connected in series between the output terminal of the inverter at the final stage and the input terminal of the inverter at the first stage, and the analog switch and the second capacitor element. Are placed in close proximity.

[0019]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, a display device according to the present invention will be specifically described with reference to the drawings. FIG. 1 is a block diagram showing a schematic configuration of a first embodiment of a liquid crystal display device. The liquid crystal display device of FIG. 1 includes a glass substrate 2 in which a pixel array section 1 and a drive circuit are integrally formed. The glass substrate 2 is disposed so as to face a counter substrate (not shown), and a liquid crystal layer is sandwiched between the glass substrate 2 and the glass substrate 2 for sealing.

Separately from the glass substrate 2 of FIG. 1, a substrate on which a controller IC 3 for sending a digital video signal and a control signal to a drive circuit and a power supply IC 4 for supplying a power supply voltage are mounted is provided, and the substrates are flexible. -Connected with a printed circuit board, etc.

Signal lines and scanning lines are provided in rows on the glass substrate 2 of FIG. 1, and pixel TFTs are provided near each intersection of the signal lines and scanning lines.
The pixel array section 1 in which is formed, the signal line driving circuit 5 that drives the signal line, and the scanning line driving circuit 6 that drives the scanning line are provided.

The signal line drive circuit 5 includes a shift register 11 for generating a shift pulse by sequentially shifting a start pulse, and a data bus 12 for supplying digital pixel data.
A sampling latch 13 that sequentially latches digital pixel data in synchronization with a shift pulse; a load latch 14 that collectively latches the latched outputs of the sampling latch 13 at the same timing; A voltage selection circuit 15 for selecting a voltage, a D / A converter (hereinafter, DAC) 16 for D / A converting the lower bit string of digital pixel data based on the selected reference voltage, and D / A converted An amplifier (hereinafter, AMP) 17 for amplifying an analog video signal, and an AM
It has a signal line selection circuit 18 for switching and controlling which signal line the output of P17 is supplied to, and a timing control circuit 19.

FIG. 2 is a block diagram showing the internal structure of the signal line drive circuit 5. The data distribution circuit 21 of FIG.
Of the shift register 11 and the data bus 12. Further, in FIG. 2, the DAC 16 and the AMP 17 are collectively represented by one block.

The voltage dividing resistor ladder 20 generates nine types of reference voltages V1 to V9 based on the three types of reference voltages REF1, Vm, and REF2 supplied from the power supply IC 4, and generates the generated reference voltages V1 to V9. It is supplied to the selection circuit 15. The voltage selection circuit 15 selects two types of reference voltages V1 to V9 based on the upper 3 bits of the digital pixel data.
Select and output r1 and Vr2.

The DAC 16 uses the reference voltages Vr1 and Vr2 output from the voltage selection circuit 15 to generate a voltage corresponding to the lower 3 bits of the digital pixel data. DAC16
The voltage generated in 1 is amplified by the AMP 17 and then supplied to the signal line selection circuit 18.

The signal line selection circuit 18 precharges the signal line before supplying the voltage from the AMP 17 to the corresponding signal line. The reference voltage Vm supplied from the power supply IC4 is used as the precharge voltage. More specifically, precharging is performed using a circuit having the configuration shown in FIG.

FIG. 3 shows the DAC 16 in the signal line drive circuit 5,
3 is a circuit diagram showing detailed configurations of an AMP 17 and a signal line selection circuit 18. FIG. As illustrated, the DAC 16 performs D / A conversion based on the reference voltages Vr1 and Vr2 supplied from the voltage selection circuit 15.

The DAC 16 includes capacitor elements C1 to C.
3, C6, analog switches S1a to S1c, S2, S3a, S3b, and S4 for redistributing charges of the capacitor element, and ON according to the logic of the lower 3 bits of the digital pixel data.
Off-controlled analog switches S5, / S5, S6
/ S6, S7, / S7. C6 is AMP and D
Shared with AC. It is used in the process of D / A conversion operation, and also has a role in the operation of the first stage inverter of the AMP.

FIG. 4 is an operation timing chart of the DAC 16. First, at time T1, the analog switches S5 to S7 are turned on / off and the analog switches S1a to S1c are turned on according to the lower 3 bits of the digital pixel data. As a result, charges corresponding to the lower 2 bits of the digital pixel data are stored in the capacitor elements C1 and C3.
For example, when the analog switch S6 is on, the charge corresponding to the voltage Vr2 is accumulated in the capacitor element C1, and when the analog switch / S6 is on, the charge corresponding to the voltage Vr1 is accumulated in the capacitor element C1. It Further, when the analog switch S7 is on, the charge corresponding to the voltage Vr2 is accumulated in the capacitor element C3, and when the analog switch / S7 is on, the charge corresponding to the voltage Vr1 is accumulated in the capacitor element C3. It On the other hand, the charge corresponding to the voltage Vr1 is always accumulated in the capacitor element C2.

After that, at time T2, the analog switch S2 is turned on, and charge is redistributed between the capacitor elements C1 and C2. Thereafter, at time T3, the analog switches S3a and S3b are turned on, and the capacitor element C
The charge is redistributed between C2 and C3, and the charge corresponding to the third bit is accumulated in the capacitor element C6. After that, at time T4, the analog switch S4 is turned on, and the charges accumulated in the capacitor elements C2 and C6 are redistributed. Thus, the D / A conversion based on the lower 3 bits is completed, and the desired analog voltage Vout is stored at the left end of the capacitor element C6. Further, after time T3, all the analog switches 18 between the AMP 17 and the signal line are turned off, the analog switches S9, S10, S11 are turned on, and the inputs and outputs of IV1 to IV3 are short-circuited. IV1 to the right end of the capacitors C6 to C8
The operation threshold voltage of IV3 is accumulated. At time T5, the analog switches S9 to S11 are turned off and one of the switch S8 and the switch 18 is turned on to perform a write operation for making the signal line voltage equal to the analog voltage Vout. The AMP 17 operates to perform voltage writing in the direction in which the voltage at the left end of the capacitor C6 becomes equal to the analog voltage Vout by the switch S8 that feeds back the signal line voltage to the signal line.

Thereafter, after time T5, times T1 to T4
The same operation of is repeated.

The AMP 17, as shown in FIG. 3, includes three inverters IV1, IV2, IV3 connected in cascade,
Capacitor elements C4 and C5 inserted between the stages of the inverters IV1 to IV3, an analog switch S8 and a capacitor element C6 connected in series between the final stage inverter IV3 and the first stage inverter IV1, and the respective inverters IV1 to IV3. Of the analog switches S9 to S11 inserted between the input and output terminals.

Three-stage inverters IV1 to IV1 in the AMP 17
The power supply voltage XAVDD and the ground voltage XAVSS are supplied to IV3, respectively, but in the present embodiment, as shown in FIG. 3, the power supply line L1 of the first-stage inverter IV1 and the power supplies of the inverters IV2 and IV3 of the second and subsequent stages. The supply line L2 is separated. Specifically, the power supply voltage XAVDD and the ground voltage XAVSS are supplied to the first-stage inverter IV1 via the resistance elements R1 and R2, respectively, while the second-stage and subsequent inverters IV2 and IV3 have a resistance R3. , R4 to supply the power supply voltage XAVDD and the ground voltage XAVSS, respectively.

The reason why the power supply lines are separated only in the first-stage inverter IV1 is that the first-stage inverter IV1 greatly affects the accuracy of the AMP 17.

The specific circuit configuration for dividing the power supply line only in the first-stage inverter IV1 is not limited to that shown in FIG. For example, FIG. 5 shows an example in which the type of power supply voltage supplied from the outside is divided into the first-stage inverter IV1 and the second-stage and subsequent inverters IV2 and IV3. In the case of FIG. 5, the power source voltage XAVD is applied to the first-stage inverter IV1.
D2 is supplied through resistor R1 and ground voltage XA
VSS1 is supplied via the resistor R2. On the other hand, the power supply voltage XAVDD1 is supplied via the resistor R3 and the ground voltage XAVSS1 is supplied via the resistor R4 to the inverters IV2, IV3 in the second and subsequent stages.

The capacitor element C7 connected to the input / output terminal of the second-stage inverter IV2 of the AMP 17 is one form of an important impedance element found by the inventor after trial and error to stabilize the operation of the AMP. Is. The capacitor element C7 is an impedance element for phase compensation and will be described in detail later. Capacitor element C
7 may be implicitly formed as a parasitic capacitance depending on the circuit layout even if it is not explicitly provided, and it is considered that it is not necessary to provide an explicit phase compensation capacitance.
If the value of 7 is set to 0, the odd-numbered inverters are cascaded in a loop to form a circuit in which oscillation is apt to occur, which makes the amplifier circuit of the display device useless.

In the case of FIG. 5 as well, as in FIG.
In order to separate the power supply line of the first-stage inverter IV1 in the inside from the power supply lines of the other inverters IV2 and IV3,
The accuracy of MP17 can be improved.

In FIG. 5, for simplification, AMP1
The analog switches between the input / output terminals of the inverters IV1 to IV3 in 7 are omitted.

The resistor element Rm and the capacitor element Cm shown in FIG. 3 are on the module (mounting substrate), and R1 to R4 are on the insulating substrate.

The capacitor element Cm is a power supply voltage XAVDD, XAVSS
The resistance elements Rm, R1 to R4 prevent a large current from flowing through the inverters IV1, IV2, IV3 forming the AMP 17, and suppress an increase in power consumption. Furthermore, prevent the oscillation of AMP17,
Suppress the occurrence of display defects.

(Second Embodiment) The signal line selection circuit 18 in the signal line drive circuit 5 is composed of analog switches made of TFTs. However, variations in the TFT characteristics cause variations in the ON resistance of the analog switches. The drive speed of the signal line due to the AMP may vary and display unevenness may occur.

When a local Vth variation occurs, the ON resistance of the specific analog switch becomes too small, the loops of the cascaded inverters in odd stages approach a no-load state, causing AMP oscillation and causing line defects. There is also a risk of being invited.

Therefore, as shown in FIG. 6A, the signal line selection circuit 18 may be constructed by connecting two analog switches S21 and S22 in parallel for each signal line. In this case, the circuit diagram of the signal line selection circuit 18 connected to a certain signal line is as shown in FIG.
The configuration is such that analog switches S21 and S22 composed of OS transistors are connected in parallel.

In this way, the analog switches S21 and S22 are
Are connected in parallel to configure the signal line selection circuit 18, so that two analog switches S21 and S22 connected in parallel are connected.
Even if one of them is not sufficiently turned on due to local Vth variation and the other is turned on, signal line writing is performed, so that the probability of causing the above-described display failure can be reduced. Therefore, it is less likely to be affected by variations in the characteristics of the analog switch. Further, even if one analog switch is defective and does not function normally, the signal line can be written by the other analog switch, so that the manufacturing yield is improved.

If there are no layout restrictions, parallelization of three or more is more effective.

(Third Embodiment) It is technically difficult to equalize the on-resistances of the analog switches constituting the signal line selection circuit 18. Therefore, as shown in FIG. 7, a method of inserting a resistance element R5 between the signal line selection circuit 18 and the signal line to make it less susceptible to the on resistance of the analog switch in the signal line selection circuit 18 is considered. To be In this case, it is desirable that the resistance value of the resistance element R5 be set to a value larger than the on resistance of the analog switch in the signal line selection circuit 18. As a result, the impedance when the signal line side is viewed from the AMP 17 side becomes dependent on the resistance value of the resistance element R5 and becomes irrelevant to the on resistance of the analog switch in the signal line selection circuit 18, and therefore the write timing of the signal line. Can be reduced.

Further, the precharge control circuit 22 may be connected to one end of the resistance element R5 as shown in FIG. The analog switch in the precharge control circuit 22 of FIG. 8 is turned on before the signal line is written based on the output of the AMP 17, and the signal line is precharged (preliminary write).
I do. In this way, by precharging the signal line before writing the signal line, the time required for writing the signal line can be shortened.

By making the size of the analog switch in the precharge control circuit 22 smaller than the size of the analog switch in the signal line selection circuit 18, the leak current from the precharge power supply can be reduced.

On the contrary, by making the size of the analog switch in the precharge control circuit 22 larger than the size of the analog switch in the signal line selection circuit 18, the time required for writing the signal line can be further shortened.

(Fourth Embodiment) The analog switch used in each part in the signal line drive circuit 5 is usually shown in FIG.
As shown in, the structure is such that an nMOS transistor and a pMOS transistor are connected in parallel. However, in the case of such a structure, when the analog switch changes from on to off, the charge accumulated in the gate-source capacitance of the analog switch flows into the load capacitance, and the output voltage of the analog switch fluctuates. There is.

Here, when the analog switch is on
Each gate of pMOS transistor and nMOS transistor
The capacitance between sources is Cgsp (ON) and Cgsn (ON) respectively, and the pMOS transistor when the analog switch is off and the
When the gate-source capacitances of the nMOS transistors are Cgsp (OFF) and Cgsn (OFF), the variation ΔV of the output voltage of the analog switch is expressed by the following equation (1).

[0052]

[Equation 1] For example, when the output voltage of the analog switch in the signal line selection circuit 18 changes, the writing voltage of the signal line also changes, which adversely affects the display quality. This is also effective for the switches connected to the capacitance such as the capacitor elements C1 to C3 of the DAC 16 shown in FIG.

Therefore, in this embodiment, at least a part of the analog switches in the signal line drive circuit 5 are
As shown in FIG. 9B, the original analog switch S23
An analog switch S24 for punch-through compensation is connected in series. This punch-through compensation analog switch S24 is pM
The OS transistor and nMOS transistor are connected in parallel, and the source and drain terminals of both transistors are short-circuited. The analog switch S24 for punch-through compensation is
On / off control is performed in the opposite direction to the original analog switch S23.

By providing an analog switch S24 for punch-through compensation as shown in FIG. 9B, when the original analog switch S23 changes from ON to OFF, the gate-source of the transistor in the original analog switch S23. The charge accumulated in the inter-capacitance is transferred to the analog switch S24 for punch-through compensation. Therefore, even if the original analog switch S23 is turned on / off, the fluctuation of the output voltage is so small that it does not affect the display.

(Fifth Embodiment) In the fifth embodiment, D
10 to 12 are provided between the input and output terminals of the second-stage inverter IV2 that constitutes the AMP 17 that amplifies the output of the AC 16.
It is characterized in that a phase compensation element as shown in FIG. By arranging such a phase compensation element, phase compensation (appropriate adjustment of signal propagation speed) is performed, and AM
It is possible to prevent oscillation and ringing of P17.

Here, the oscillation means that the output voltage of the AMP 17 oscillates around a desired potential and does not converge. This oscillation is caused by the fact that the signal propagation speed of the odd-numbered inverter loops connected in cascade is too high and the output of the AMP 17 vibrates and propagates to the signal line as it is. For example, this occurs when the absolute value of Vth becomes small and the load driving capability of each inverter becomes too high.

On the other hand, ringing means that the convergence speed to a desired value becomes too slow. This is caused by the signal propagation speed of the cascaded odd-numbered inverter loops being too slow and the feedback of the potential of the signal line being too slow. For example, this occurs when the absolute value of Vth becomes large and the load driving capability of each inverter becomes too low.

The present inventor, after trial and error, found the following means as a means for stabilizing the operation of the AMP 17, and succeeded in dramatically improving the operational stability of the AMP 17.

As shown in FIG. 10, since the phase compensating element composed of the resistance element Ra and the capacitor element C7 connected in series is provided between the input and output of the second-stage inverter IV2,
Even when the absolute value of Vth becomes small, the oscillation hardly occurs. The resistance value of Ra and the size of the capacitance of C7 may be determined in consideration of the layout so that the product of Ra and C7 is about a predetermined value. The predetermined value is preferably on the order of the value of the product of the resistance Rsig from the output of the AMP 17 to the signal line and the signal line capacitance Csig. More preferably, C
About 0.5 to 3 times sig × Rsig is preferable.

In the circuit of FIG. 10, the frequency component in which the signal line load is likely to oscillate is cut off by the impedance element Ra and the capacitor element C7 to prevent oscillation. If the capacitor element C7 is too large, the circuit area and the driving load of the first-stage inverter increase, which results in poor convergence and easy ringing.

The capacitor element C7 shown in FIG.
It may be inserted between the input and output terminals of the third-stage inverter IV3 forming the MP17.

FIG. 11 is a modification of FIG. 10, in which one end of the capacitor element C4 inserted between the first-stage inverter IV1 and the second-stage inverter IV2 and the output end of the second-stage inverter IV2. In between, a resistor element R as shown
It is characterized in that a phase compensation element including a and a capacitor element C7 is inserted. Such a capacitor element C7
By inserting, the effect of preventing oscillation is obtained as in the case of FIG. 10, and the amount of decrease in gain can be suppressed more than in FIG. Further, since the convergence speed is improved, there is an effect of preventing ringing even when the absolute value of Vth becomes large. In this case, the capacitance of the capacitor element C7 need only be 1/2 or less of that of the capacitor element C4. If it is made too large, the adverse effect of increasing the circuit area and the adverse effect of increasing the driving load of the first stage inverter are caused, the convergence is deteriorated, and ringing is likely to occur.

As a modification of FIG. 11, a resistance element R6 may be inserted between the newly inserted capacitor element C7 and the output terminal of the second-stage inverter IV2 as shown in FIG. The capacitor element C7 and the resistor element R6 may be left and right interchanged. The resistance element R6 performs phase compensation similarly to the capacitor element C7. That is, by providing the resistance element R6, the accuracy of phase compensation can be further improved. The operation and effect are similar to those in the case of FIG. It may be selected based on the ease of layout and the consistency with the process.

Alternatively, instead of the resistance element R6, as shown in FIG.
3, one electrode of the newly added capacitor element C7, more specifically, the second-stage inverter IV2
The electrode C7a connected to the output terminal of may be formed of a high resistance material. Thereby, even if the resistance element R6 is not separately connected, the same effect as when the resistance element R6 is connected can be obtained.

(Sixth Embodiment) A liquid crystal display device used in a mobile device such as a mobile phone or a notebook computer is required to have a small frame. Therefore, in the sixth embodiment, the AMP1 that amplifies the output of the DAC 16 is used.
The power supply wiring pattern P1 of No. 7 is arranged at a position overlapping the common electrode 23 on the counter substrate as shown in FIG. As a result, the outer dimensions of the glass substrate 2 can be reduced and the frame can be made smaller.

As a modification of FIG. 14, as shown in FIG. 15, the capacitor elements C4 and C5 connected between the stages of the inverters IV1 to IV3 in the AMP 17 are arranged at positions overlapping the common electrode 23 on the counter substrate. You may. Since the capacitor element requires a larger mounting area than other circuit components, the outer dimension of the glass substrate 2 can be reduced by disposing the capacitor element at a position overlapping the common electrode 23 as shown in FIG.

(Seventh Embodiment) When the combined resistance Rcom from the common potential supply end on the glass substrate is high, the voltage level of the common electrode 23 formed on the counter substrate reaches a desired value within a predetermined period. It may not happen. This combined resistance Rco
m is the resistance of the thick line portion in FIG.

Therefore, in the seventh embodiment, the resistance value of the combined resistance R7 from the common potential feeding end is lowered by thickening or shortening the voltage supply line to the common electrode 23.

Specifically, it is desirable to set the resistance value Rcom of the combined resistance R7 from the common potential feed end so as to satisfy the relationship of the following expression (2).

Rcom <predetermined coefficient × ON period of the signal line selection circuit / (total amount of auxiliary capacitance / capacitance between the common electrode and the insulating substrate) / number of simultaneously written signal lines (2) Further, glass Combined resistance Rc from the auxiliary capacity supply end on the board
If s is high, the voltage level of the auxiliary capacitance may not reach a desired value within a predetermined period. This combined resistance Rcs is the resistance indicated by the thick line in FIG.

Therefore, as a modification of the seventh embodiment,
By thickening or shortening the voltage supply line to the auxiliary capacitance line, the combined resistance R7 from the auxiliary capacitance potential supply end
The resistance value of may be lowered.

Specifically, the resistance value of the combined resistance R7 from the auxiliary capacitance potential supply terminal is set so as to satisfy the following expression (3).
It is desirable to set Rcs.

Rcs <predetermined coefficient × ON period of the signal line selection circuit / (total amount of auxiliary capacitance / capacitance between the common electrode and the insulating substrate) / number of simultaneously written signal lines (3) (8th) Embodiment) FIG. 18A is a voltage-luminance curve of the liquid crystal portion of the liquid crystal display device of this embodiment. The luminance change with respect to the voltage change is large near the intermediate voltage, and is small at other voltages as compared with the vicinity of the intermediate voltage. That is, the error voltage of the output of the AMP 17 near the intermediate voltage is directly connected to the display unevenness, but at other voltages, the error voltage is not visually recognized unless it is very large. Therefore, AMP
The output error voltage of 17 is preferably minimized near the intermediate voltage.

The output error voltage of the AMP 17 of the present invention is inversely proportional to the product of the gains of the inverting amplifier circuits (inverters) when writing the signal line. Here, the gain refers to the slope (steepness) of the input / output characteristic polarity of the inverting amplifier circuit, and the gain changes depending on the input voltage. The present inventor has found that a complementary inverter in which a p-channel TFT and an n-channel TFT are connected in series between power supply voltages is optimal as an inverting amplifier circuit used in the AMP 17 that drives a signal line of a liquid crystal display device.

In this way, when writing the intermediate voltage, each inverter operates in the vicinity of each inverter threshold. As shown in FIG. 18B, the complementary inverter has a maximum gain near its threshold value. Although an inverting amplifier circuit can be formed by using other sources such as a source follower, it is difficult to minimize the error voltage when outputting a voltage near the halftone.

Therefore, in this embodiment, the p-channel TF is used.
A complementary inverter in which T and an n-channel TFT were connected in series between power sources was used as the inverter of AMP17.

When a display element other than the liquid crystal display device is used, the following is done. That is, the voltage range where the slope is the steepest is examined from the voltage-luminance characteristic diagram of the display element as shown in FIG. The type of amplification stage may be selected.

(Ninth Embodiment) As shown in FIG.
The AMP 17 is configured by cascade-connecting odd-numbered stages of inverters, and an analog switch S8 and a capacitor element C6 are inserted between the input terminal of the first-stage inverter IV1 and the output terminal of the last-stage inverter IV3.

It is the first stage inverter IV1 that has the greatest effect on the gain accuracy of the AMP17. Analog switch S8 on the feedback path from the final stage inverter IV3
When the input capacitor C6 of the first-stage inverter IV1 and the input capacitor C6 are separated from each other, the analog switch S8 is turned on.
The influence of turning off on the input capacitance of the first-stage inverter IV1 increases.

Therefore, the ninth embodiment is characterized in that the analog switch S8 on the feedback path and the input capacitor C6 of the first-stage inverter IV1 are arranged close to each other.
As a result, by turning on / off the analog switch S8, the input capacitance of the first-stage inverter IV1 is not affected, and highly accurate gain adjustment can be performed.

(Tenth Embodiment) In the tenth embodiment, the resistance value of the resistor connected to the power supply line of the AMP 17 and the resistance value of the resistor connected to the ground line are unbalanced. .

FIG. 20 is a circuit diagram of the tenth embodiment of the signal line drive circuit. The signal line drive circuit of FIG. 20 is the same as the signal line drive circuit of FIG.
A resistor R1 connected to a power supply line L11 (including the power supply lines L1 and L2) connected to the inverter in 17
The sum of the resistance values of R3 and Rd is calculated as ground line L12 (ground line L
(Including 3, L4) resistors R2, R4, Rs connected on
It is larger than the sum of resistance values. Where resistance R
d and Rs are resistors externally attached to the glass substrate, and resistors R1 to R4 are resistors formed inside the glass substrate.

The voltage selection circuit 15, the DAC 16 of FIG.
The AMP 17 and the signal line selection circuit 18 are a set of circuits. A plurality of these circuits are integrally formed on the same glass substrate.

FIG. 21 is a diagram showing the voltage level of each part in the liquid crystal display device of this embodiment. Power supply voltage XVDD (= 5
V) is the shift register 11, the data bus 12, and the
The power supply voltage is supplied to the sampling latch 13, the load latch 14, the voltage selection circuit 15, the DAC 16, and the signal line selection circuit 18. Power supply voltage XAVDD (= 5.5V)
Are inverters IV1, IV2, I of the AMP 17 of FIG.
It is a power supply voltage supplied to V3. The voltage Gate is the gate voltage of the pixel driving TFT. Common voltage VCOM is 0V
Alternatively, it is a voltage of 5.3 V and takes alternate values in a predetermined cycle. The signal voltages VsigH and VsigL are signal voltages output from the AMP 17, and the maximum voltage is VsigH (= 4.5.
V), and its minimum voltage is VsigL (= 0.5V). The voltages REF1 and REF2 are reference voltages supplied to the voltage dividing resistor ladder 20 of FIG. 2, and REF1 is linked with the driving cycle of VCOM.
The values of and REF2 alternate between 0V and 5V, or 5V and 0V.

As can be seen from FIG. 21, the power supply voltage XAVDD
And the maximum value VsigH of the signal voltage is 1.0V, whereas the potential difference between the ground voltage 0V and the minimum value VsigL of the signal voltage is 0.5V. That is, as shown in FIG.
The power supply voltage side has a margin of 1.0 V, while the ground voltage side has a margin of only 0.5 V. In FIG. 22, the voltage fluctuation amount of the signal voltages VsigH and VsigL is represented by Δ.
In this case, the margin ΔV1 on the power supply voltage side is ΔV1 = XA
VDD− (VsigH + Δ), ground voltage side margin ΔV2
Becomes ΔV2 = (VsigL−Δ) −XAVSS.

When resistors are respectively connected to the power supply line L11 and the ground line L12, a voltage drop occurs at both ends of these resistors, so that the voltage of the power supply terminal of the AMP 17 lowers and the voltage of the ground terminal rises accordingly. Even so, if the voltage drop is within the above-mentioned margin, the AMP 17 operates normally.

For example, the power supply line L11 and the ground line L12
Let us consider a case where the resistance values of the resistors connected to each other are made equal to each other and the resistance values of these resistors are gradually increased. As the resistance value increases, the voltage drop across the resistance increases. As described above, the margin on the ground voltage side is smaller, so that the ground voltage side first comes out of the margin. In order to prevent the ground voltage side from coming out of the margin first, the resistance value of the resistance on the ground voltage side may be made smaller than the resistance value of the resistance on the power supply voltage side.

Therefore, in the present embodiment, the power supply line L1
The sum of the resistance values of the resistors connected to 1 is larger than the sum of the resistance values of the resistors connected to the ground line L12. As a result, the same margin can be secured on the power supply line side and the ground line side, and by increasing the resistance value on the power supply line L11 side, the current flowing through the power supply line L11 is reduced and the power consumption is reduced. Can be achieved.

The effect of reducing power consumption is that the AMP17
Is particularly effective when the absolute value of Vth of each TFT element forming the inverter is small. Since the voltage applied to the gate of each inverter of the AMP 17 is always 0.5 to 4.5V, a through current flows through each inverter. This through current increases when the absolute value of Vth is small.

In this embodiment, since the resistance is provided in the power supply line, the effective voltage applied to the inverter is reduced by the product of the current and the resistance, and the through current is suppressed. On the other hand, when the absolute value of Vth is large, the through current is relatively small, the product of current and resistance is small, and the effective voltage applied to the inverter is almost the same as the power supply voltage. Driving capacity can be secured.

For this reason, the technique of this embodiment is particularly suitable for the case where a polysilicon TFT having a large Vth variation is formed on a glass substrate to integrally form a pixel portion and a drive circuit of a display device.

In FIG. 20 described above, the resistors R1 and R2 are connected to the power supply lines L1 and L2 in the glass substrate, and the ground lines L3 and L3.
Resistors R3 and R4 on L4, and resistors Rd and Rd on the outside of the glass substrate.
Although the example in which Rs is provided is shown, the number of resistors provided on each line is not particularly limited, and all resistors may be formed inside the glass substrate, or conversely, all resistors may be provided outside the glass substrate. Good.

(Eleventh Embodiment) In the eleventh embodiment, a power supply voltage is supplied to each inverter in the AMP 17 through separate resistors.

FIG. 23 is a circuit diagram of the eleventh embodiment of the signal line drive circuit. The signal line driver circuit of FIG.
The circuit configuration is the same as that of the signal line drive circuit shown in the figure, except that the arrangement of power supply lines connected to the respective inverters in 17 is different.

Between the power supply terminals of three cascade-connected inverters IV1, IV2, IV3 in the AMP 17 and the reference power supply terminal T1 which supplies the power supply voltage XAVDD from the outside,
The resistors R11, R12, and R13 are connected to each other. These resistors R11 to R13 may be formed inside the glass substrate or may be externally attached to the glass substrate.

The resistance value Rd1 of the resistor R11 connected to the first-stage inverter IV1, the resistance value Rd2 of the resistor R12 connected to the second-stage inverter IV2, and the resistance value of the resistor R13 connected to the last-stage inverter IV3. Rd3 is set so that, for example, Rd2 <Rd3 <Rd1. More specifically, for example, Rd1 = 2 kΩ, Rd2 = 200Ω, Rd
It is set to d3 = 700Ω.

The reason why the resistance value Rd1 of the resistor R11 in the first stage is set to be the largest is that the inverter IV1 in the first stage needs to operate only near the threshold voltage, so that the resistance value is increased for the purpose of reducing power consumption. Then, the power supply voltage supplied to the inverter IV1 is lowered.

The resistance value Rd3 of the resistor at the final stage is set to such a value that a voltage having a desired voltage amplitude is output from the inverter IV3. If the resistance value Rd2 of the second-stage resistor is increased, the AMP 17 may oscillate, so the resistance value Rd2 is set to a small value.

Thus, in the present embodiment, the AMP17
A resistor on a power supply line that supplies a power supply voltage to each of the inverters IV1 to IV3 in
The resistance value of each of the resistors R11 to R13 is set to the inverter IV1
To set the optimum value according to the role of IV3, AMP
The power consumption can be reduced while improving the performance of 17.

(Twelfth Embodiment) In the twelfth embodiment, the size of the inverter in the AMP 17 is adjusted.

FIG. 24 is a circuit diagram of the AMP 17 in the signal line drive circuit of the twelfth embodiment. AM as shown
P17 denotes three inverters IV1 to IV connected in cascade.
V3, capacitor elements C4 and C5 connected between the stages of the respective inverters IV1 to IV3, and the final stage inverter I
It has an analog switch S8 and a capacitor element C6 connected in series between the output terminal of V3 and the input terminal of the first-stage inverter IV1, and a capacitor element C7 for phase compensation connected between the input and output terminals of the inverter IV2. .

In this embodiment, the second stage inverter IV
The size of 2 is set to be equal to or larger than the size of the final-stage inverter IV3, and the size of the first-stage inverter IV1 is set to be equal to or smaller than the size of the second-stage inverter IV2.

In FIG. 24, the number of inverter stages in the AMP 17 is three, but the number of stages is not particularly limited as long as it is an odd number of three or more. For example, (2n +
1) When the stage inverters (n is an integer of 1 or more) are connected in cascade, the gate widths W1 to W2n + 1 and the gate lengths L1 to L2n + 1 of the transistors forming the inverters of each stage are as follows. To meet.

W2n / L2n ≧ W2n + 1 / L2n + 1 W2n-1 / L2n-1 ≧ W2n + 1 / L2n + 1 ... W2 / L2 ≧ W2n + 1 / L2n + 1 W1 / L1 ≦ W2 / L2 The reason for satisfying the above equation is as follows.

Since the first stage inverter IV1 is also an input signal stage, if the size of this inverter is increased, the parasitic capacitance increases and the accuracy of the AMP 17 is affected. Therefore, the inverter IV1 cannot be increased unnecessarily.

Further, the size of the final stage inverter IV3 must be determined by the signal line load of the latter stage. If the size of this inverter is increased, the driving capability with respect to the signal line load becomes too large, and the stability of the AMP 17 is impaired.

On the other hand, if the size of the inverter IV2 of the second stage is made larger than that of the inverter IV3 of the final stage, the response speed of the inverter IV2 of the second stage becomes faster, and the AMP
The operation speed of 17 is improved.

The number of inverter stages in the AMP 17 may be an odd number of stages of 3 or more.

As described above, by setting the size of the inverter in the AMP 17 so as to satisfy the relation of the expression (1), the accuracy of the AMP 17 becomes high and the operating speed becomes high.

(Thirteenth Embodiment) In the thirteenth embodiment, the size of the final stage inverter in the AMP 17 is set to be equal to or smaller than the size of the signal line selection circuit.

FIG. 25 is a circuit diagram of the AMP 17 and the signal line selection circuit 18 in the signal line drive circuit of the thirteenth embodiment.

The structure of the AMP 17 is the same as that of FIG.
It has three inverters IV1 to IV3 connected in cascade. In the present embodiment, the size of the final stage inverter IV3 is set to be equal to or smaller than the size of the signal line selection circuit 18. More specifically, when the gate width of the transistor forming the final stage inverter IV3 is W3 and the gate length is L3, and the gate width of the transistor in the signal line selection circuit 18 is W4 and the gate length is L4, Make sure that the following relationships are satisfied.

W4 / L4 ≧ W3 / L3 The reason for satisfying the above equation is that the feedback of AMP17 becomes too fast and the AMP17 may oscillate when the ON resistance of the signal line selection circuit 18 becomes high. is there. At this time, the cascade-connected IV1 to IV3 act similarly to the ring oscillator circuit (oscillation circuit), and thus violently oscillate.

FIG. 26 shows an inverter IV in the AMP 17.
FIG. 6 is a diagram showing how the phase margin indicating the likelihood of oscillation changes when the sizes of 1 to IV3 and the size of the signal line selection circuit 18 are variously changed. The graph g1 in FIG. 26 has a size ratio of 2: 1: 2: 5, and the graph g2 has a size ratio of 1: 2 :.
In the case of 2: 5, the graph g3 shows the case where the size ratio is 2: 2: 1: 5.

From FIG. 26, it is understood that the phase margin is largest in the case of the graph g3, that is, when the size of the final stage inverter IV3 is smaller than the sizes of the other inverters IV1 and IV2 and the signal line selection circuit 18.
From this, too, it is understood that oscillation is less likely to occur when the condition of (2) is satisfied.

As described above, in the present embodiment, the size of the final stage inverter IV3 in the AMP 17 is set to be equal to or smaller than the size of the signal line selection circuit 18, so that the oscillation of the AMP 17 can be reliably prevented.

In this embodiment, as shown in FIG. 24, the number of inverter stages in the AMP 17 is three, but the same applies to an odd number of stages of three or more.

(Fourteenth Embodiment) In the fourteenth embodiment, the resistance value of the resistance element connected to the power supply terminal of the inverter of each stage in the AMP 17 is adjusted.

FIG. 27 is a circuit diagram of the AMP 17 in the signal line drive circuit of the 14th embodiment. AMP17 of FIG.
24 has three inverters IV1 to IV3 connected in cascade, as in the AMP 17 of FIG. Each inverter I
V1 to IV3 have a power supply terminal Vdd and a ground terminal Vss, and the power supply terminal Vdd and the reference voltage terminal XAVD of each inverter.
Resistance elements Rv (1), Rv (2), and
Rv (3) is connected. Similarly, each inverter IV1
Resistors Rs (1), Rs (2), and Rs (3) are separately connected between the ground terminal Vss and the ground voltage terminal XAVSS of IV3 to IV3.

The resistance value of the resistance element Rv (2) of the second stage is equal to or lower than the resistance value of the resistance element Rv (3) of the third stage, and the resistance element Rv of the first stage is
The resistance value of (1) is set to be equal to or higher than the resistance value of the second-stage resistance element Rv (2).

Similarly, the resistance value of the second-stage resistance element Rs (2) is less than or equal to the resistance value of the third-stage resistance element Rs (3), and the resistance value of the first-stage resistance element Rs (1) is two-step. It is set to be equal to or higher than the resistance value of the resistance element Rs (2) of the eye.

In FIG. 27, the number of stages of the inverters in the AMP 17 is three, but the number of stages is not particularly limited as long as it is an odd number of three or more. For example, (2n +
When 1) -stage inverters (n is an integer of 1 or more) are cascade-connected, the resistance elements Rv (1) to Rv (2n + 1) respectively connected to the power supply terminals of the inverters of each stage are as follows. Try to satisfy the relationship.

Rv (2n) ≦ Rv (2n + 1) Rv (2n−1) ≦ Rv (2n + 1) ・ ・ ・ Rv (2) ≦ Rv (2n + 1) Rv (1) ≧ Rv (2) Alternatively, the resistance elements Rs (1) to Rs (2n + 1) connected to the ground terminals of the inverters of the respective stages satisfy the following relationships.

Rs (2n) ≦ Rs (2n + 1) Rs (2n-1) ≦ Rs (2n + 1) ... Rs (2) ≦ Rs (2n + 1) Rs (1) ≧ Rs (2) As described above, in the present embodiment, the resistance value of the resistance element connected to the power supply terminal or the ground terminal of the inverter in each stage in the AMP 17 satisfies the above equation,
The same effect as that of the second embodiment can be obtained. That is,
By adjusting the resistance value of each resistance element, the driving capability of the inverter in each stage can be optimally adjusted, and the accuracy and operating speed of the AMP 17 can be improved.

(Fifteenth Embodiment) In the fifteenth embodiment, separate power supply voltages are supplied to the inverters of the respective stages in the AMP 17.

FIG. 28 is a circuit diagram of the AMP 17 in the signal line drive circuit of the 15th embodiment. 28 AMP17
24 has three inverters IV1 to IV3 connected in cascade, as in the AMP 17 of FIG. Each inverter I
V1 to IV3 are respectively the first and second power supply terminals Vd
I have d and Vss. Inverters IV1 to IV of each stage
The first power supply terminal Vdd of 3 has a different power supply voltage for each.
XAVDD (1), XAVDD (2), XAVDD (3) are supplied. Similarly, different types of power supply voltages XAVSS (1), XAVSS (2), XAVSS are applied to the second power supply terminals Vss of the inverters IV1 to IV3 of the respective stages.
(3) is supplied.

The power supply voltage XAVDD (2) supplied to the second-stage inverter IV2 is set to be equal to or higher than the power supply voltage XAVDD (3) supplied to the last-stage inverter IV3, and the power supply voltage supplied to the first-stage inverter IV1. XAVDD (1) is set below the power supply voltage XAVDD (2) supplied to the second-stage inverter IV2.

Alternatively, the power supply voltage XAVSS (2) supplied to the second-stage inverter IV2 is the final-stage inverter IV3.
Is set to be equal to or lower than the power supply voltage XAVSS (3) supplied to the first stage inverter IV1, and is set to be equal to or higher than the power supply voltage XAVSS (2) supplied to the second stage inverter IV2. It

In FIG. 28, the number of stages of the inverters in the AMP 17 is three, but the number of stages is not particularly limited as long as it is an odd number of stages of three or more. For example, (2n +
When the 1) -stage inverters (n is an integer of 1 or more) are cascade-connected, the first power supply terminal Vdd of each-stage inverter
Supply voltage XAVDD (1) to XAVDD (2N + 1)
Is set to satisfy the following relationship.

XAVDD (2n) ≧ XAVDD (2n + 1) XAVDD (2n-1) ≧ XAVDD (2n + 1) ・ ・ ・ XAVDD (2) ≧ XAVDD (2n + 1) XAVDD (1) ≦ XAVDD (2) Alternatively, the power supply voltages XAVSS (1) to XAVSS (2N + 1) supplied to the second power supply terminal Vss of each stage inverter are set so as to satisfy the following relationship.

XAVSS (2n) ≤ XAVSS (2n + 1) XAVSS (2n-1) ≤ XAVSS (2n + 1) ... XAVSS (2) ≤ XAVSS (2n + 1) XAVSS (1) ≥ XAVSS (2) As described above, in the present embodiment, since the power supply voltage supplied to the inverters of each stage in the AMP 17 is individually adjusted,
The drive capacity of each stage inverter can be adjusted optimally and the AMP
The accuracy of 17 and the operation speed can be improved.

Also, by using (Twelfth embodiment), (13th embodiment), (14th embodiment), (15th embodiment) together, the same operational effect can be obtained. Therefore, the driving capability of the inverters in each stage can be optimally adjusted, and the accuracy and operating speed of the AMP 17 can be improved.

(Sixteenth Embodiment) In the sixteenth embodiment, sampling of an analog video signal and writing to a signal line are executed in parallel.

FIG. 29A is a circuit diagram of the AMP 17 in the signal line drive circuit of the 16th embodiment. FIG. 29 (a)
In the AMP 17, the first-stage inverter is composed of two first amplification units 31 connected in parallel. Each of these first amplifying units 31 has a switch S21, a capacitor element C6a, an inverter IV1a and a switch S22 connected in series, and a switch S23 connected in parallel between the input and output terminals of the inverter IV1a. The first amplification section 31 is connected to the second amplification section 32. The second amplification section 32 includes a capacitor element C4, an inverter IV2, a capacitor element C5, and an inverter IV3 that are connected in series. Although not shown, the second-stage inverter is provided with the phase compensation element shown in FIG.

The AMP 17 shown in FIG.
As shown in (b), one signal line is provided for every six signal lines, whereas the AMP 17 of this embodiment is provided for every twelve signal lines. Therefore, AMP
17 Two inverters can be reduced for each one.

FIG. 30 (a) is an operation timing chart of the AMP 17 of this embodiment, and FIG. 30 (b) is an operation timing chart of the AMP 17 of FIG. 25 shown for comparison.

The AMP 17 of FIG. 25 alternately performs sampling of an analog video signal and writing of a signal line, but the AMP 17 of this embodiment performs sampling and writing of a signal line in parallel. Therefore, twice as many signal lines as those in FIG. 25 can be driven without shortening the sampling period and the signal line writing period.

FIG. 31 is a peripheral circuit diagram of the AMP 17,
The circuit diagrams of the DAC 16, the AMP 17, and the signal line selection circuit 18 are shown. The DAC 16 has analog switches S30, S31, S32a, and S32b that are switch-controlled according to the values of the lower three bits b2 to b0 of the digital pixel data.
A capacitor element C11 for accumulating charges according to bit b0, a capacitor element C12 for accumulating charges according to bits b0 to b2, and capacitor elements C11, C12.
Switches S33a and S33 for controlling charge accumulation in
b, S33c, S33d, S34a, S34b, S34
with c and.

FIG. 32 is an operation timing chart of the circuit shown in FIG. First, at time T1, the switches S33a and S33 are
b, S33c is turned on. As a result, charges corresponding to the bits b0 and b1 are stored in the capacitor elements C11 and C12, respectively. Then, at time T2, the switch S9a
Is turned on, and the charge corresponding to the bit b2 is generated in the capacitor element C.
6a is accumulated.

Then, at time T3, the switches S33a, S33
After 33b and S33c are turned off, the switches S34a and S34b are turned on between times T4 and T5. This allows
The charge is redistributed among the capacitor elements C11, C12, and C6a.

Then, at time T6, the switches S10 and S1 are
1 is turned on, and sampling of the AMP 17 is performed until time T8. After that, from time T9 to T12,
Writing of the signal line is performed.

In addition, from time T7 to T15, time T1 to
Similar to T8, the data to be written to the signal line next is sampled.

As described above, in this embodiment, the first-stage inverters are parallelized and the respective inverters IV1a and IV1b are alternately switched and driven, so that data sampling and signal line writing are performed in parallel.

Here, the power consumption of the AMP 17 is AMP
17 power supply voltage x AMP17 current per unit x AM
It is represented by the number of P17. Therefore, if the number of inverters forming the AMP 17 is reduced as in this embodiment,
Power consumption can be reduced.

(Seventeenth Embodiment) In a seventeenth embodiment, the power supply voltage XAVDD for driving the AMP 17 is an integral multiple (for example, double) of the power supply voltage VDD supplied from the outside.
To be set to. The power supply voltage of an LSI such as a power supply IC is generally 3 V or less. In the drive circuit of a liquid crystal display device, 1) to drive the liquid crystal material,
2) It is necessary to boost the voltage to an appropriate value for driving polysilicon having a larger Vth than that of an LSI and to supply it to the signal line driving circuit. For example, the most popular twisted nematic liquid crystal needs to be driven in a voltage range of about 4V. The voltage value required to drive polysilicon is V of P-channel TFT and N-channel TFT.
The maximum sum of th (absolute value) is required.

FIG. 33 is a circuit diagram showing an example of a booster circuit included in the power supply IC of FIG. This booster circuit is a power supply voltage XAV that doubles the power supply voltage VDD supplied from the outside.
Generate DD. The generated power supply voltage XAVDD is AMP17.
Used to drive the.

The booster circuit shown in FIG. 33 has an IN (+) terminal and an OUT (+) terminal.
Switches SW1a and SW2 connected in series with the terminals
a and a connection path between the switches SW1a and SW2a and IN
Capacitor element C13 connected in series with the (-) terminal
And a switch SW1b, a capacitor element C14 connected between the IN (+) terminal and the IN (-) terminal, and a capacitor element C.
Switches SW1b, S connected in series between both terminals of 14
W2b and a capacitor element C15 connected between the OUT (+) terminal and the OUT (-) terminal are provided.

First, the switches SW1a and SW1b are turned on. As a result, electric charges according to the input voltage Vin are accumulated in the capacitor element C13. Next, the switches 1a, 1
b is turned off and the switches SW2a and SW2b are turned on.
As a result, the capacitor element C13 is connected in series to the input voltage Vin, and the capacitor element C13 accumulates electric charges corresponding to a voltage twice the input voltage Vin, so that the output voltage V0 is 2
X Vin.

By connecting a resistor in the booster circuit shown in FIG. 33, a boosted voltage having an arbitrary multiplication factor can be generated. However, considering power supply efficiency, a voltage which is an integral multiple of the input voltage is generated as shown in FIG. Is desirable. Therefore, in the present embodiment, the power supply IC 4 generates the voltage XAVDD that is an integral multiple of the power supply voltage VDD.

The power supply IC 4 is mounted on a display device formed on the glass substrate 2, is formed on the glass substrate 2 using a polysilicon TFT or the like like the display device, or is different from the glass substrate 2. It is mounted or formed on another substrate. In any case, since the booster circuit of FIG. 33 does not need an inductance element, it can be easily integrated on an LSI or on a glass substrate.

As shown in FIG. 34, the power supply IC 4 is AM
In addition to the power supply voltage XAVDD for driving P17, the power supply voltage XVDD for driving digital circuit components in the display device, and D /
The reference voltages REFH and REFL for A conversion are also generated. Since the digital circuit components consume less power, the demand for the power supply voltage XVDD is small. Therefore, in the present embodiment, the voltage level of the power supply voltage XVDD is set to be the same as the power supply voltage XAVDD in order to improve the efficiency of circuit design and ease of manufacturing.

As described above, in the seventeenth embodiment, the AM
Since the power supply voltage XAVDD for driving P17 is set to an integral multiple of the power supply voltage VDD supplied from the outside, AMP
It is possible to improve the power supply efficiency while increasing the drive capacity of 17.

Since the power supply voltage XVDD for driving the digital circuit components in the display device is set to the same voltage level as the power supply voltage XAVDD, the internal structure of the power supply IC4 can be simplified.

(Eighteenth Embodiment) The eighteenth embodiment is an improvement of the seventeenth embodiment, and it is sufficient even if the characteristics such as Vth of the TFTs constituting the AMP vary due to manufacturing variations or the like. Secure an operating margin, and
Each power supply voltage is set so that the power consumption is minimized.

The power consumption of the liquid crystal display device in which the DAC 16 and the AMP 17 are integrally formed on the glass substrate by using the polysilicon TFT is large in the power consumption of the AMP 17 and the voltage dividing resistor ladder 20. Since the AMP 17 operates while passing a through current through the inverter, it consumes a large amount of current. Due to the configuration of the power supply IC 4, maximizing the boosting efficiency of the power supply of the AMP 17 should be given the highest priority. Therefore, XA
VDD is 5.5V, which is twice VDD (2.75V).

On the other hand, the power consumption of the voltage dividing resistor ladder 20 is
Since it can be expressed as the square of the applied voltage / resistance value,
The voltage applied to the voltage dividing resistor ladder 20 should not be unnecessarily high. Moreover, the voltage variation should be 5% or less. If the variation in voltage is large, the applied voltage range required for driving the liquid crystal cannot be secured, resulting in insufficient contrast, or the voltage applied to the liquid crystal deviates from a predetermined value, thereby hindering halftone display. Therefore, the voltage applied to both ends of the voltage dividing resistor ladder 20 is set to 0V (GND) and 5V to the other.

The external power supply voltage VDD, the power supply voltage XAVDD, the reference voltage maximum value REFH supplied to the voltage dividing resistor ladder 20, and the reference voltage minimum value REFL have the voltage levels shown in FIG. The reference voltage maximum value REFH and the reference voltage minimum value REFL are the reference voltages REF1, REF2 whose voltage level is inverted each time the polarity is inverted.
Is supplied to the voltage dividing resistance ladder 20.

When the voltage is set from the viewpoint of reducing the power consumption, the signal line drive voltage is as shown in FIG.
The voltage is in the range of 0.5V to 4.5V, and is inevitably biased to the 0V side from the power supply voltage XAVDD. In order to secure the output voltage of the AMP17 in a range that is biased with respect to the power supply voltage of the AMP17, the value of the resistance inserted in the power supply line and the ground line of the inverter in the AMP17 is asymmetrical between the power supply line side and the ground line side. It is desirable to do. The reason is as described in the tenth embodiment, and the resistors Ra and R as shown in FIG. 36 are used.
By connecting b, the same effect as the tenth embodiment can be obtained.

In FIG. 36, a resistor Ra connected between the power supply terminal of each inverter in the AMP 17 and the power supply voltage line XAVDD, and a resistor Rb connected between the ground terminal of each inverter and the ground line GND. The resistance ratio of is set asymmetrical (for example, Ra: Rb = 2: 1). As a result, TF can be changed by the manufacturing process of the polysilicon TFT substrate.
Even if Vth of T varies, it is possible to stably operate while suppressing power consumption to the minimum.

(Nineteenth Embodiment) In the nineteenth embodiment, two out of three inverters forming the AMP 17 are used.
The gate width W of the third stage inverter is made larger than the gate width W of the third stage inverter. In the AMP 17 of the TAB-IC, which is generally used to drive the signal line of the display device, the gate width of the element of the comparison circuit section including the differential circuit is designed to be as small as possible and the gate width of the element of the output stage is designed to be large. The concept of the AMP 17 of this embodiment is significantly different from that of a general one.

As a result of trial and error, the inventor has found a non-trivial relative relationship of gate widths of respective stages of inverters, which is particularly suitable for a relatively small display device such as a liquid crystal display device for mobile phones and a liquid crystal display device for PDAs. Here, the relatively small size means A
The drive load capacitance (capacity per signal line) viewed from the MP17 is about 20 pF or less.

When the AMP 17 for driving the signal line is formed by using an element such as a polysilicon TFT element having a relatively large variation in characteristics such as Vth, it is not always necessary to increase the output stage in order to secure operational stability. Not valid,
Rather, there is a problem that oscillation and ringing are likely to occur. The inventor found this fact as a result of trial and error, and found that it is better to make the gate width of the TFT constituting the final stage inverter rather small and to increase the gate width of the second stage.

The AMP 17, as shown in FIG.
Two inverters are connected in series with a capacitor element in between. Therefore, the output of the AMP 17 easily causes oscillation and ringing, and as shown in FIG. 37, it takes a certain time (hereinafter, this time is referred to as a convergence time) until the output is stabilized.

FIG. 38 shows the gate width W1 of the first stage inverter.
And the gate width W2 of the second-stage inverter are made equal to each other.
When the ratio W2 / W3 between the gate width W2 of the third-stage inverter and the gate width W3 of the third-stage inverter is changed, AM
It is a figure which shows how the convergence time of the output of P17 changes.

As shown in the figure, in the range of W2 / W3 of 0.5 to 1.5, the convergence time is shorter as the gate width W2 of the second-stage inverter is larger than the gate width W3 of the third-stage inverter. . Therefore, by making the gate width W2 of the second-stage inverter larger than the gate width W3 of the third-stage inverter, the operation of the AMP 17 can be further stabilized.

(Twentieth Embodiment) Two-inch diagonal 17
A suitable for use in 6 × 180 dot liquid crystal display devices
A specific layout form of the MP circuit will be described.

FIG. 39 is a layout diagram of a portion of the AMP 17 shown in FIG. The symbols of switches and elements are shown in correspondence with FIG.

In order to prevent oscillation and ringing, the one shown in FIG. 11 is used as the phase compensation element provided before and after the second-stage inverter. N ⁺ doped polysilicon is used as the resistance element. The capacitive element is formed by the intersection of N ⁺ doped polysilicon and the gate line layer. In this display device, the signal line capacitance is 12 pF.
The signal line resistance is 0.4 kΩ. The time constant of the driving load is
12 pF × 0.8 kΩ = 9.6 nsec. The resistance value of the phase compensation element is 100 kΩ, and the capacitance is 0.1 pF.
And The driving time per signal line was 4 us.

In order to suppress the output voltage error due to the punch-through voltage of the analog switch, punch-through compensation switches are arranged at various places as in FIG.

All analog switches and inverters use P-channel TFTs and N-channel TFTs complementarily. The undesired parasitic capacitances are P-channel TFT and N
The circuit is symmetrically arranged so as to uniformly parasitize the channel TFT and minimize the influence.

Capacitance elements C1, C2 used for D / A conversion
C3 and C6 are formed at the intersection of the N ⁺ -doped polysilicon layer and the gate line layer. It is desirable that these capacitors have the same capacitance. This is because the variation in electrostatic capacitance is directly connected to the error voltage of D / A conversion.
For example, in C3, the cross section of a part of the signal line layer and the gate line layer is also used so as to have the same capacitance as C2 as much as possible.

The resistance between each inverter constituting the AMP 17 and the power supply has the symbol Rm = 360Ω using the symbol of FIG.
(XAVDD side) / 220Ω (XAVSS side), R1 = 70
Ω, R3 = 50Ω, R2 = 35Ω, and R4 = 25Ω.

The gate width ratio of each inverter of the AMP 17 was set to IV1: IV2: IV3 = 6: 6: 5.

One of the two glass substrates constituting the liquid crystal cell is a color filter substrate on which a common electrode is formed. The common electrode is driven to invert the polarity with one horizontal period as a cycle. As shown in FIG. 40, the other substrate is a low temperature polysilicon TFT array substrate in which the pixel array section 1, the signal line driving circuit 5, the scanning line (gate line) driving circuit 6 and the timing circuit 7 are integrally formed. .

The signal line drive circuit 5 includes AMPs 17 and D.
44 sets of AC16 are arranged, and D / A conversion and signal line driving by AMP17 (operation shown in FIG. 4) are performed in one horizontal period.
The operation is performed while selecting 12 signal lines sequentially.

A schematic configuration diagram of the signal line drive circuit 5 is shown in FIG. Further, the liquid crystal display device of the present embodiment includes the power supply IC 4 and the LCD controller shown in FIG. 34, and operates with the power supply setting shown in FIGS. 35 and 21.

With such a configuration, low power consumption and AM
The stability of P17 was excellent, there was no problem in the accuracy of D / A conversion, and good display could be performed. In addition, it was possible to secure a sufficient yield with respect to the Vth variation due to the variation in the manufacturing process. Further, the N-channel TFT and the P-channel TFT operated without any problem in a wide range of the absolute values of Vth from 0.5 V to 2.5 V at the minimum.

[0178]

As described in detail above, according to the present invention, it is possible to improve the accuracy of the odd number of cascaded inverters in the amplifier for amplifying the analog video signal output from the D / A converter. Since the power supply line is divided only in the first-stage inverter that is most affected, highly accurate gain adjustment can be performed.

Since a plurality of analog switches connected in parallel are provided for each signal line as a signal line selection circuit for selecting a signal line, the influence of variations in the characteristics of the analog switch is less likely to occur, and the write timing of the signal line is reduced. You can eliminate the gap.

Since the analog switch for punch-through compensation is connected in series to the analog switch on the insulating substrate,
The charges accumulated in the gate-source capacitance can be transferred to the analog switch for punch-through compensation, and even if the analog switch changes from on to off, the output voltage of the analog switch can be prevented from fluctuating.

Further, since the second capacitor element is inserted between the input and output terminals of the second and subsequent inverters in the amplifier,
Phase compensation can be performed and oscillation of the amplifier can be prevented.

Further, since the power supply line of the amplifier is arranged so as to overlap the common electrode, the frame of the display device can be made small.

Further, since the counter electrode resistance is reduced, the voltage of the common electrode can be set to a desired value.

Further, when the gain of the write voltage of the signal line is adjusted by the amplifier, it is possible to finely adjust the gain in the medium luminance region, so that the display quality can be improved.

Further, since the input capacitance of the first-stage inverter in the amplifier and the analog switch on the feedback path are arranged close to each other, the input capacitance of the first-stage inverter will be the same even if this analog switch is turned on / off. Not affected.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of a first embodiment of a liquid crystal display device.

FIG. 2 is a block diagram showing an internal configuration of a signal line drive circuit.

FIG. 3 is a circuit diagram showing a detailed configuration of a DAC, an AMP 17 and a signal line selection circuit 18 in the signal line drive circuit.

FIG. 4 is an operation timing chart of the DAC.

FIG. 5 is a diagram showing an example in which the type of power supply voltage supplied from the outside is divided into a first-stage inverter and a second-stage and subsequent inverters.

FIG. 6 is a circuit diagram showing a specific configuration of a signal line selection circuit 18.

FIG. 7 is a circuit diagram showing a modification of the signal line selection circuit 18.

FIG. 8 is a circuit diagram showing a configuration of a precharge control circuit.

FIG. 9 is a circuit diagram showing an example in which an analog switch for punch-through compensation is connected in series to the analog switch.

FIG. 10 is a circuit diagram showing an example in which a capacitor element for phase compensation is provided in the AMP 17.

11 is a circuit diagram showing a modified example of FIG.

FIG. 12 is a circuit diagram showing another modification of FIG.

FIG. 13 is a circuit diagram showing a modified example of FIG.

FIG. 14 is a diagram showing an example in which a power supply wiring pattern of an AMP 17 is arranged so as to overlap a common electrode.

FIG. 15 is a diagram showing an example in which a capacitor element in an AMP 17 is arranged so as to overlap a common electrode.

16 is a diagram showing a combined resistance from the common potential supply end on the glass substrate 2. FIG.

FIG. 17 is a diagram showing a combined resistance from the auxiliary capacitance potential supply terminal.

FIG. 18A is a diagram showing a gain characteristic of AMP;
(B) is a figure which shows the gain characteristic of AMP using a complementary inverter.

FIG. 19 is a diagram showing an example in which an analog switch on the feedback path is arranged near the input capacitance of the first-stage inverter.

FIG. 20 is a circuit diagram of a tenth embodiment of a signal line drive circuit.

FIG. 21 is a diagram showing voltage levels of respective parts in the liquid crystal display device of the present embodiment.

FIG. 22 is a diagram showing margins on the power supply voltage side and the ground voltage side.

FIG. 23 is a circuit diagram of an eleventh embodiment of a signal line drive circuit.

FIG. 24 is an AM in the signal line drive circuit of the twelfth embodiment.
Circuit diagram of P.

FIG. 25 is an AM in the signal line drive circuit of the thirteenth embodiment.
The circuit diagram of P and a signal line selection circuit.

FIG. 26 is a diagram showing how the phase margin changes.

FIG. 27 is an AM in the signal line drive circuit of the fourteenth embodiment.
Circuit diagram of P.

FIG. 28 is an AM in the signal line drive circuit of the fifteenth embodiment.
Circuit diagram of P.

29A is a circuit diagram of an AMP in the signal line drive circuit of the sixteenth embodiment, and FIG. 29B is a circuit diagram of a conventional AMP.

30A is an operation timing chart of the AMP 17 of the present embodiment, and FIG. 30B is an AMP of FIG. 25 shown for comparison.
17 is an operation timing chart of 17.

FIG. 31 is a peripheral circuit diagram of the AMP 17.

32 is an operation timing chart of the circuit of FIG. 31.

FIG. 33 is a circuit diagram showing an example of a booster circuit included in the power supply IC of FIG.

FIG. 34 is a diagram illustrating a function of a power supply IC.

FIG. 35 is a diagram showing the relationship among the voltage levels of the external power supply voltage VDD, the power supply voltage XAVDD, the reference voltage maximum value REFH and the reference voltage minimum value REVL generated by the voltage dividing resistor ladder.

FIG. 36 is a diagram illustrating resistors connected to a power supply line and a ground line of an inverter in an AMP.

FIG. 37 is a view for explaining the convergence time of AMP output.

FIG. 38 shows that the gate width W1 of the first-stage inverter and the gate width W2 of the second-stage inverter are made equal, and the ratio W2 / of the gate width W2 of the second-stage inverter and the gate width W3 of the third-stage inverter. The figure which shows how the convergence time of the output of AMP17 changes when W3 is changed.

FIG. 39 is a layout diagram of the AMP portion of FIG. 3.

FIG. 40 is a layout diagram of a low temperature polysilicon TFT array substrate in the twentieth embodiment.

FIG. 41 is a schematic configuration diagram of a signal line drive circuit.

[Explanation of symbols]

1 Pixel array section 2 glass substrates 3 Controller IC 4 power supply IC 5 Signal line drive circuit 6 Scan line drive circuit 11 shift register 12 data bus 13 Sampling latch 14 load latch 15 Voltage selection circuit 16 DAC 17 AMP 18 Signal line selection circuit 20 division resistor ladder

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) G09G 3/20 621 G09G 3/20 621M 623 623B 623F 623G 641 641C 680 680G (72) Inventor Fujiwara Hisao 1-9-2, Harara-cho, Fukaya-shi, Saitama, Ltd. Toshiba Fukaya Plant, Ltd. (72) Inventor Masao Kanabe 1-9-2, Harara-cho, Fukaya-shi, Saitama Ltd., Fukaya, Toshiba Corporation (72) Inventor Nakamura Kazuo, 1-9-2, Harara-cho, Fukaya-shi, Saitama, Ltd., Toshiba Fukaya Factory, Ltd. (72) Inventor, Masakatsu Kitani, 1-chome, 2-2, Harara-cho, Fukaya, Saitama, F-term, Toshiba Corporation, Fukaya Factory (reference) 2H092 GA59 JA24 KA04 NA01 PA06 2H093 NA16 NC02 NC13 NC24 NC26 NC34 NC68 ND05 ND06 ND42 5C006 AA16 AC11 AF46 AF50 AF 52 AF54 AF72 AF83 BB16 BC06 BC12 BC16 BC20 BF03 BF04 BF11 BF24 BF25 BF26 BF27 BF34 BF37 BF43 BF46 EB05 EB06 FA12 FA15 FA16 FA18 FA20 FA25 FA26 FA37 FA41 FA43 FA47 FA56 5C080 AA10 BB05 DD05 DD08 DD23 DD25 DD26 DD28 EE17 EE29 FF03 FF11 JJ02 JJ03 JJ04 JJ05 JJ06 KK04 KK07

Claims (21)

[Claims] 1. A signal line and a scanning line vertically and horizontally arranged on an insulating substrate, a display element formed near each intersection of the signal line and the scanning line, and a scanning line driving circuit for driving the scanning line. And a signal line driving circuit formed on the insulating substrate and driving the signal line, wherein the signal line driving circuit includes an amplifier for amplifying an analog video signal, and an amplifier for amplifying an analog video signal. A signal line selection circuit for selecting a signal line to which an analog video signal is supplied, wherein the amplifier has an odd number of inverters connected in cascade, a stage between the inverters, and an input of the first stage inverter. A first capacitor element connected between the terminal and the output terminal of the final stage inverter; a first power supply line for supplying a power supply voltage to the first stage inverter; Display device characterized by having, a second power supply line for supplying a power supply voltage to the inverter. 2. The display device according to claim 1, further comprising impedance elements respectively inserted into the first and second power supply lines. 3. A signal line and a scanning line vertically and horizontally arranged on an insulating substrate, a display element formed near each intersection of the signal line and the scanning line, and a scanning line driving circuit for driving the scanning line. And a signal line driving circuit formed on the insulating substrate and driving the signal line, wherein the signal line driving circuit includes an amplifier for amplifying an analog video signal, and an amplifier for amplifying an analog video signal. A signal line selection circuit that selects a signal line that is a supply destination of an analog video signal, and the signal line selection circuit has, for each signal line, a plurality of analog switches connected in parallel, The analog switches corresponding to the signal lines are turned on in the same direction.
A display device characterized by being turned off. 4. The display device according to claim 3, further comprising an impedance element inserted between each of the signal lines and each of the plurality of analog switches corresponding to the signal line. 5. A signal line and a scanning line vertically and horizontally arranged on an insulating substrate, a display element formed near each intersection of the signal line and the scanning line, and a scanning line driving circuit for driving the scanning line. And a signal line driving circuit which is formed on the insulating substrate and drives the signal line, in which at least a part of the analog switches on the insulating substrate are connected in series, respectively, and a corresponding analog switch is provided. And an analog switch for punch-through compensation that is on / off controlled in the opposite direction to that of the punch-through compensation analog switch.The punch-through compensation analog switch has a pMOS transistor and an nMOS transistor connected in parallel, and the source and drain of both transistors are short-circuited. And a display device. 6. A signal line and a scanning line vertically and horizontally arranged on an insulating substrate, a display element formed near each intersection of the signal line and the scanning line, and a scanning line driving circuit for driving the scanning line. And a signal line driving circuit formed on the insulating substrate and driving the signal line, wherein the signal line driving circuit includes an amplifier for amplifying an analog video signal, and an amplifier for amplifying an analog video signal. A signal line selection circuit for selecting a signal line to which an analog video signal is supplied, the amplifier includes a power supply line and a ground line, three inverters connected in cascade, the inverter and the power supply line Connected between the input terminal of the first stage inverter and the output terminal of the final stage inverter, and a resistance element provided between the inverter and the ground line. One capacitor element, a switching circuit provided in the first-stage inverter and capable of switching whether to short-circuit between the input / output terminals of the first-stage inverter, and inserted between the input / output terminals of the second-stage inverter. A display device having a phase compensation impedance element. 7. The amplifier includes a capacitor element connected between stages of three cascaded inverters, and a capacitor element provided for each of the three inverters and connected between input / output terminals of a corresponding inverter. 7. A switching circuit capable of switching whether to short-circuit or not.
Display device according to. 8. The display device according to claim 6, wherein the product of the resistance value and the capacitance value of the phase compensation impedance element is approximately the product value of the signal line load capacitance and the signal line resistance. 9. The display device according to claim 6, wherein (gate width / gate length) of the second-stage inverter is larger than the value of the third-stage inverter. 10. A signal line and a scanning line vertically and horizontally arranged on an insulating substrate, a display element formed near each intersection of the signal line and the scanning line, and a scanning line driving circuit for driving the scanning line. And a signal line driving circuit which is formed on the insulating substrate and drives the signal line, and a counter substrate which is arranged facing the insulating substrate and has a common electrode formed thereon, The line drive circuit includes an amplifier that amplifies the analog video signal, and a signal line selection circuit that selects a signal line to which the analog video signal amplified by the amplifier is supplied, and the amplifiers are connected in cascade. A display device comprising an odd number of inverters, and the gain of each inverter is maximized in the vicinity of a voltage where the slope of the voltage-luminance characteristic curve of the display element is maximized. 11. The amplifier is configured by connecting an odd number of inverters in cascade, each of the inverters having a pMOS transistor and an nMOS transistor connected in series between a first power supply voltage and a second power supply voltage. The display device according to claim 10, wherein the display device is an inverter. 12. A signal line and a scanning line vertically and horizontally arranged on an insulating substrate, a display element formed near each intersection of the signal line and the scanning line, and a scanning line driving circuit for driving the scanning line. And a signal line driving circuit formed on the insulating substrate and driving the signal line, wherein the signal line driving circuit includes an amplifier for amplifying an analog video signal, and an amplifier for amplifying an analog video signal. A signal line selection circuit for selecting a signal line to which an analog video signal is supplied, wherein the amplifier is a cascade-connected (2n + 1) -stage (where n is an integer of 1 or more) inverter; A capacitor element connected between each of the (2n + 1) -th stage inverters and between the input terminal of the first-stage inverter and the output terminal of the last-stage inverter, The size of each transistor forming the inverter up to the n-th stage is equal to or larger than the size of the transistor forming the final inverter, and the size of each transistor forming the first-stage inverter forms the second-stage inverter. A display device characterized in that the size is equal to or smaller than the size of a transistor to be formed. 13. The display device according to claim 12, wherein the size of the transistor is a ratio of a gate width to a gate length of the transistor. 14. A signal line and a scanning line vertically and horizontally arranged on an insulating substrate, a display element formed near each intersection of the signal line and the scanning line, and a scanning line driving circuit for driving the scanning line. And a signal line driving circuit formed on the insulating substrate and driving the signal line, wherein the signal line driving circuit includes an amplifier for amplifying an analog video signal, and an amplifier for amplifying an analog video signal. A signal line selection circuit for selecting a signal line to which an analog video signal is supplied, wherein the amplifier is connected to a power supply line and a ground line in (2n + 1) stages (where n is 1 or more). (Integer) inverter, a capacitor element connected between the stages of the (2n + 1) th stage inverter, and between the input terminal of the first stage inverter and the output terminal of the final stage inverter, respectively. A power supply line and a plurality of impedance elements connected to each of the odd number of inverters, and the impedance value of each of the impedance elements connected to the second to 2nth inverters is the final stage. Is less than or equal to the impedance value of the impedance element connected to the inverter, and the impedance value of the impedance element connected to the first stage inverter is greater than or equal to the impedance value of the impedance element connected to the second stage inverter. A display device characterized by being. 15. A signal line and a scanning line vertically and horizontally arranged on an insulating substrate, a display element formed near each intersection of the signal line and the scanning line, and a scanning line driving circuit for driving the scanning line. And a signal line drive circuit formed on the insulating substrate and driving the signal line, wherein the signal line drive circuit includes a latch circuit for latching digital pixel data, and a latch for the latch circuit. A D / A converter that converts the output into an analog video signal, an amplifier that amplifies the analog video signal converted by the D / A converter, and a signal line to which the analog video signal amplified by the amplifier is supplied And a signal line selection circuit for selecting the signal line selection circuit, wherein the amplifier is composed of (2n + 1) -stage (where n is an integer of 1 or more) inverters connected in cascade, A capacitor element connected between each stage and between an input terminal of the first-stage inverter and an output terminal of the last-stage inverter, and each of the (2n + 1) -stage inverters has a first And a second power supply terminal, and at least one of the first and second power supply terminals,
A different reference voltage is supplied to each of the (2n + 1) th inverters, and the reference voltage supplied to at least one of the first and second power supply terminals of each of the second to 2nth inverters is the final reference voltage. Reference voltage supplied to at least one of the first and second power supply terminals of the first-stage inverter and at least one of the first and second power supply terminals of the first-stage inverter Is less than or equal to a reference voltage supplied to at least one of the first and second power supply terminals of the second-stage inverter. 16. A signal line and a scanning line vertically and horizontally arranged on an insulating substrate, a display element formed near each intersection of the signal line and the scanning line, and a scanning line driving circuit for driving the scanning line. And a signal line driving circuit formed on the insulating substrate and driving the signal line, wherein the signal line driving circuit includes an amplifier for amplifying an analog video signal, and an amplifier for amplifying an analog video signal. And a signal line selection circuit that performs signal line writing by selecting a signal line to which an analog video signal is supplied, each of the amplifiers being composed of one or more inverters and connected in parallel with each other. A first amplifying section, a second amplifying section including a plurality of cascade-connected inverters, and one of the plurality of first amplifying sections in order,
The output of the selected first amplification unit is supplied to the first stage inverter of the second amplification unit, and the output of the second amplification unit is returned to the input side of the first stage inverter of the selected first amplification unit and closed. A selection unit that forms a loop, and a plurality of capacitor elements that are respectively connected between the stages of the respective inverters in the closed loop, and the amplifier is provided while the signal line selection circuit is performing signal line writing. And a display device which amplifies an analog video signal corresponding to a signal line to be written next. 17. The plurality of first amplification units include first and second inverters connected in parallel, and the selection unit includes an output terminal of the first inverter and an input of the second amplification unit. A first switching unit that switches whether to connect a terminal with the capacitor element in between, and an input terminal of the first inverter and an output terminal of the second amplification unit with the capacitor element in between. A second switching unit that switches whether to connect or not, and a third switching unit that switches whether to connect the output terminal of the second inverter and the input terminal of the second amplifying unit with the capacitor element in between. The amplifier includes: a switching unit; and a fourth switching unit that switches whether to connect the input terminal of the second inverter and the output terminal of the second amplification unit with the capacitor element in between. , The signal line selection circuit is a signal Each time of writing, the formation of a closed loop including a first inverter, a display device according to claim 16, characterized in that alternately the formation of a closed loop including the second inverter. 18. The output of one of the first and second inverters is set to the second by turning on the second or fourth switching unit.
17. The analog video signal to be written next is supplied to the other of the first and second inverters by turning on the first or third switching unit immediately after the supply to the amplification unit. The display device according to item 17. 19. A signal line and a scanning line vertically and horizontally arranged on an insulating substrate, a display element formed near each intersection of the signal line and the scanning line, and a scanning line driving circuit for driving the scanning line. And a signal line drive circuit which is formed on the insulating substrate and drives the signal line, in a display device including: a first power supply voltage based on a first power supply voltage supplied from the outside; A power supply voltage generation circuit that generates a second power supply voltage having an integer multiple voltage level, the signal line drive circuit includes an amplifier that amplifies an analog video signal, and a supply destination of the analog video signal amplified by the amplifier. And a signal line selection circuit that performs signal line writing by selecting a signal line of the display device, wherein the amplifier is driven by the second power supply voltage. 20. The display device according to claim 19, wherein the digital circuit components in the signal line drive circuit are driven by the second power supply voltage. 21. The amplifier includes a capacitor element connected between stages of three cascaded inverters, and a capacitor element provided for each of the three inverters. A switching circuit capable of switching whether to short-circuit, a first impedance element connected between the second power supply line and first power supply terminals of each of the odd number of inverters, and a ground potential line The second impedance element connected between the second power supply terminal of each of the odd number of inverters and having a smaller impedance than the first impedance element.
The display device according to item 0.