JP2003255889A - Display device and its driving method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display device and its driving method in which discharging cells are controlled with a timing so that efficiency in light emission of the cells is maximized even though the characteristic of a driving circuit is fluctuated due to the temperature variation of the circuit or the difference in a production lot of the circuit. <P>SOLUTION: An output detector 16 outputs a detection signal DET indicating the rising of first and second peaks of a sustaining pulse Psu. A control timing comparator 183 compares a delay time detecting signal DE1 and a time difference detecting signal DE2 and outputs a correction time detecting signal DE3. A correction time adder 182 holds the signal DE3, adds the signal DE3 being held and a correction signal DE4 and outputs the adding result as a new correction signal DE4. A control timing corrector 181 corrects a control signal US1 using the signal DE4 and outputs a control signal US1a. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device for displaying an image by selectively discharging a plurality of discharge cells and a driving method thereof.

[0002]

2. Description of the Related Art PDP (plasma display panel)
The plasma display device using is advantageous in that it can be thin and have a large screen. In this plasma display device, an image is displayed by utilizing the light emission at the time of discharge of the discharge cells forming the pixels.

FIG. 26 is a diagram for explaining a method of driving a discharge cell in an AC type PDP. As shown in FIG. 26, in the AC-type PDP discharge cell, the surfaces of the electrodes 301 and 302 facing each other are dielectric layers 303 and 3, respectively.
It is covered with 04.

As shown in FIG. 26A, the electrode 30
When a voltage lower than the discharge start voltage is applied between 1 and 302, no discharge occurs. As shown in (b) of FIG. 26, when a pulsed voltage (writing pulse) higher than the discharge start voltage is applied between the electrodes 301 and 302, discharge is generated. When a discharge is generated, negative charges proceed in the direction of the electrode 301 and are accumulated on the wall surface of the dielectric layer 303, and positive charges proceed in the direction of the electrode 302 and are accumulated on the wall surface of the dielectric layer 304. The charges accumulated on the wall surfaces of the dielectric layers 303 and 304 are called wall charges. The voltage induced by this wall charge is called the wall voltage.

As shown in FIG. 26C, the dielectric layer 3
Negative wall charges are accumulated on the wall surface of 03, and the dielectric layer 304
A positive wall charge is accumulated on the wall surface of. In this case, since the polarity of the wall voltage is opposite to the polarity of the externally applied voltage, the effective voltage in the discharge space decreases as the discharge progresses,
The discharge will stop automatically.

As shown in FIG. 26D, when the polarity of the externally applied voltage is reversed, the polarity of the wall voltage becomes the same as the polarity of the externally applied voltage, so that the effective voltage in the discharge space becomes high. . When the effective voltage at this time exceeds the discharge start voltage, discharge of reverse polarity occurs. As a result, the positive charges travel toward the electrode 301, neutralize the negative wall charges already accumulated in the dielectric layer 303, and the negative charges are transferred to the electrode 30.
Going in the direction of 2, the positive wall charges already accumulated in the dielectric layer 304 are neutralized.

Then, as shown in FIG. 26E, positive and negative wall charges are accumulated on the wall surfaces of the dielectric layers 303 and 304, respectively. In this case, since the polarity of the wall voltage is opposite to the polarity of the externally applied voltage, the effective voltage in the discharge space decreases as the discharge progresses, and the discharge stops.

Further, as shown in (f) of FIG. 26, when the polarity of the externally applied voltage is reversed, discharge of the opposite polarity is generated, the negative charge advances toward the electrode 301, and the positive charge becomes the electrode 3.
In the direction of 02, the state returns to the state of FIG.

As described above, after the discharge is once started by applying the high write pulse, the wall charges work to invert the polarity of the externally applied voltage (sustain pulse) lower than the write pulse to cause the discharge. Can be maintained. Starting the discharge by applying the write pulse is called address discharge, and maintaining the discharge by applying the sustain pulse that is alternately inverted is called sustain discharge.

Next, a sustain driver of a conventional plasma display device for driving a discharge cell by the above driving method will be described. FIG. 27 is a circuit diagram showing a structure of a sustain driver of a conventional plasma display device.

As shown in FIG. 27, the sustain driver 600 includes a recovery capacitor C11, a recovery coil L11,
It includes switches SW11, SW12, SW21, SW22 and diodes D11, D12.

The switch SW11 is connected between the power supply terminal V11 and the node N11, and the switch SW12 is connected between the node N11 and the ground terminal. The voltage Vsus is applied to the power supply terminal V11. Node N1
1 is connected to, for example, 480 sustain electrodes, and FIG. 27 shows a panel capacitance Cp corresponding to the total capacitance between the plurality of sustain electrodes and the ground terminal.

The recovery capacitor C11 is connected between the node N13 and the ground terminal. A switch SW21 and a diode D are provided between the node N13 and the node N12.
11 is connected in series, and the diode D12 and the switch SW22 are connected in series between the node N12 and the node N13. The recovery coil L11 is a node N12.
And the node N11.

FIG. 28 shows the sustain driver 6 of FIG.
It is a timing chart which shows operation | movement of the sustain period of 00. Figure 2
8 includes the voltage of the node N11 and the switch S of FIG.
The operation of W21, SW11, SW22, SW12 is shown.

First, in the period Ta, the switch SW2
1 is turned on and the switch SW12 is turned off. At this time,
The switches SW11 and SW22 are off. Thereby, LC by the recovery coil L11 and the panel capacitance Cp
Due to the resonance, the voltage of the node N11 gradually rises.
Next, in the period Tb, the switch SW21 is turned off,
The switch SW11 is turned on. As a result, the node N1
The voltage of 1 rapidly increases, the voltage of the node N11 is fixed to Vsus in the period Tc, and the sustain discharge is generated once by the discharge current supplied from the power supply terminal V11.

Next, in the period Td, the switch SW11 is turned off and the switch SW22 is turned on. As a result, the voltage at the node N11 gradually drops due to LC resonance caused by the recovery coil L11 and the panel capacitance Cp. After that, in the period Te, the switch SW22 is turned off and the switch SW12 is turned on. Accordingly, the node N11
The voltage of drops sharply and is fixed to the ground potential.

By repeating the above operation in the sustain period, the periodic sustain pulse Psu is applied to the plurality of sustain electrodes, the discharge cells are discharged at the rising of the sustain pulse Psu, and the sustain discharge is performed.

As described above, in the conventional plasma display device, the sustain driver or the like is used to discharge the discharge cell only once at the rising of the sustain pulse and stop the discharge until the next sustain pulse is applied. . In this one-time discharge, the discharge current is supplied from the power supply, and the current necessary for the discharge is sufficiently supplied, but the ultraviolet rays are saturated with respect to the discharge current, and the visible light intensity is also saturated with respect to the ultraviolet rays. Therefore, the brightness hardly increases even when the discharge current increases.

As described above, in the conventional plasma display device, since the discharge current is supplied from the power source to discharge the light only once, the light emission efficiency becomes low with respect to the input power. Further, if the discharge cell is driven at a low current level so that saturation of brightness does not occur, the discharge itself becomes unstable, and stable discharge cannot be performed repeatedly.

On the other hand, in Patent Document 1, the second voltage Vk and the first voltage Vs (> Vk) are applied to all the discharge cells to be lit during the sustain period, and the discharge cells having a low discharge voltage are first It is disclosed that discharging is performed at a voltage Vk of 2 and discharging cells having a high discharging voltage are discharged at a first voltage Vs to disperse the discharging current. In this case, each discharge cell discharges once during the half cycle of the sustain cycle, but after the discharge cell having a low discharge voltage is discharged at the second voltage Vk, the discharge cell having a high discharge voltage is discharged at the first voltage Vs. Therefore, it seems that the battery is discharged twice during the half cycle of the sustain cycle.
However, in such a discharge, each discharge cell is discharged only once, and the discharge current for the entire PDP is simply dispersed to improve the luminous efficiency for all the discharge cells to be lit. Can not.

Further, Patent Document 1 discloses that the second voltage Vk (≤Vs / 10) and the first voltage Vs are applied to all the discharge cells to be lit during the sustain period. In this case, the discharge cell having a low discharge voltage is the first voltage V
s, then again at the second voltage Vk in the next cycle, whether the discharge cell with the higher discharge voltage is discharged at the first voltage Vs, and again weakly at the second voltage Vk in the next cycle. Or do not discharge. Therefore, in this case as well, not all discharge cells to be lit are discharged twice during the half cycle of the sustain cycle, and there are discharge cells that are discharged only once. On the other hand, the luminous efficiency cannot be improved.

[0022]

[Patent Document 1] Japanese Unexamined Patent Publication No. 11-228416

[0023]

Therefore, the present inventors have made it possible to reduce the discharge current, raise the brightness, and improve the luminous efficiency by continuously generating the first and second discharges. Proposing a method.

However, if the characteristics of the driving circuit change due to the temperature change of the driving circuit, the luminous efficiency of the discharge cell may decrease. In addition, the emission efficiency of the discharge cells may decrease due to variations in the characteristics of the drive circuit due to differences in the production lot of the display panel or the drive circuit.

An object of the present invention is to control the discharge cells so as to emit light with good luminous efficiency even when the characteristics of the drive circuit vary due to temperature changes of the display panel or the drive circuit or differences in production lots. It is an object of the present invention to provide a display device and a method of driving the display device.

[0026]

(1) First invention A display device according to a first invention is a display device which selectively discharges a plurality of discharge cells to display an image. Generating a drive waveform having a display panel including cells and a series of first and second pulses to generate a second discharge after generating a first discharge in a selected discharge cell in the display panel. Driving means, a control means for controlling the driving means at first and second timings for generating the first and second pulses of the driving waveform, and a first pulse of the driving waveform generated by the driving means. And a second pulse, and a correction means for correcting at least one of the first and second timings by the control means based on the time difference detected by the detection means. .

In the display device according to the present invention, the drive means is controlled by the control means at the first and second timings to generate a drive waveform having continuous first and second pulses. To be done. Thereby, after the first discharge is generated in the selected discharge cell in the display panel, the second discharge is generated.

In this case, the voltage of the drive waveform (first pulse) is reduced by the first discharge, and the voltage of the drive waveform is increased again after the first discharge is at least weakened (second pulse).
Pulse), it is possible to generate the second discharge subsequent to the first discharge. As a result, since only the minimum electric power required for the discharge is applied in the first discharge, the saturation of the ultraviolet rays is relaxed by the current limitation from the moment the first discharge begins to weaken, and the luminous efficiency of the first discharge is reduced. Is improved.
As a result, the first discharge having a high luminous efficiency is performed in all the discharge cells to be lit, and the second discharge is further performed. Therefore, the luminous efficiency of all the discharge cells to be lit can be improved.

Further, the time difference between the first pulse and the second pulse of the drive waveform generated by the drive means is detected by the detection means, and the first and second timings by the control means are based on the detected time difference. At least one of the two is corrected by the correction means. Therefore, even if the characteristics of the driving means vary due to the temperature change of the display panel or the driving means or the difference in the production lot, etc.
It is possible to accurately control the time difference of the discharge. As a result, it becomes possible to drive the discharge cells so as to emit light in a state of good light emission efficiency.

(2) Second Invention In the display device according to the second invention, in the configuration of the display device according to the first invention, the correction means is such that the time difference detected by the detection means is equal to a predetermined reference value. The control means corrects at least one of the first and second timings.

In this case, the first pulse and the second pulse of the drive waveform
The time difference from the pulse is equal to the predetermined reference value. As a result, even when the characteristics of the driving means vary due to the temperature change of the display panel or the driving means or the difference in the production lot, the time difference between the first and second discharges is controlled to be constant.

(3) Third Invention In the display device according to the third invention, in the configuration of the display device according to the second invention, the correction means compares the time difference detected by the detection means with a reference value. Comparing means for outputting the difference between the time difference and the reference value as the correction time, and the first and second
And timing shift means for shifting at least one of the timings of (1) and (2) by the correction time output by the comparison means.

In this case, the time difference detected by the detection means and the reference value are compared by the comparison means, the difference between the time difference and the reference value is output as the correction time, and at least one of the first and second timings is corrected. Only the time is shifted. As a result, the time difference between the first pulse and the second pulse of the drive waveform becomes equal to the predetermined reference value.

(4) Fourth Invention In the display device according to the fourth invention, in the configuration of the display device according to the third invention, the correction means holds the correction time previously detected by the comparison means, and holds the correction time. It further includes adding means for adding the corrected time thus calculated to the correction time currently detected by the comparing means and outputting the corrected time as the current correction time to the timing shift means.

In this case, since the correction time previously detected by the comparison means is held, at least one of the first timing and the second timing is a fixed correction time when the characteristic of the driving means is constant and does not change. Will be corrected.

(5) Fifth Invention In the display device according to the fifth invention, in the configuration of the display device according to any one of the second to fourth inventions, the detection means is a drive waveform generated by the drive means. The time difference between the timing of the front edge of the first pulse and the timing of the front edge of the second pulse is detected as the time difference between the first pulse and the second pulse of the drive waveform.

In this case, the first pulse and the second pulse of the drive waveform
It is possible to accurately detect the time difference from the pulse.

(6) Sixth Invention In the display device according to the sixth invention, in the configuration of the display device according to the fifth invention, the detecting means is a differentiating circuit for differentiating the drive waveform generated by the driving means. , And a rectangular wave signal generation circuit for generating a rectangular wave signal from the output signal of the differentiating circuit.

In this case, the time difference between the first pulse and the second pulse of the drive waveform can be easily and accurately detected by differentiating the drive waveform generated by the drive means.

(7) Seventh Invention A display device according to a seventh invention is the display device according to any one of the second to fourth inventions, wherein the control means is the first device.
A control signal generating circuit that generates a first control signal at a second timing and a second control signal at a second timing, and the driving unit changes the first control signal generated by the control signal generating circuit. A first drive circuit that responds to generate a first pulse, and a second drive circuit that responds to a second control signal generated by the control signal generation circuit to generate a second pulse are included. .

In this case, the first drive signal drives the first drive circuit at the first timing, and the second control signal drives the second drive circuit at the second timing. As a result, a drive waveform having continuous first and second pulses is generated.

(8) Eighth Invention A display device according to an eighth invention is the display device according to the seventh invention, wherein the first drive circuit is the first drive circuit generated by the control signal generation circuit. A second driver circuit including a first driver that outputs a first drive signal in response to a control signal, and a first transistor that is driven by the first drive signal output from the first driver; Are driven by a second driver that outputs a second drive signal in response to a second control signal generated by the control signal generation circuit, and a second drive signal that is output from the second driver. A second transistor, and the detection means determines the time difference between the timing of the first drive signal output from the first driver and the timing of the second drive signal output from the second driver as a drive waveform. The first pulse and the second pulse It is detected as the time difference between the scan.

In this case, by detecting the timings of the first drive signal and the second drive signal, it is possible to easily detect the time difference between the first pulse and the second pulse of the drive waveform.

(9) Ninth Invention A display device according to a ninth invention is the display device according to any one of the second to fourth inventions, wherein the detection means is a drive waveform generated by the drive means. Detecting the time difference from the timing of the maximum point of the first pulse to the timing of the minimum point between the first pulse and the second pulse as the time difference between the first pulse and the second pulse of the driving waveform. Is.

In this case, the time difference between the maximum point of the first pulse of the drive waveform and the minimum point between the first pulse and the second pulse can be accurately detected.

(10) Tenth Invention In the display device according to the tenth invention, in the configuration of the display device according to the ninth invention, the detection means performs analog-digital conversion of the drive waveform generated by the drive means. It includes an analog-digital conversion circuit and a maximum / minimum detection means for obtaining the maximum point of the first pulse and the minimum point between the first pulse and the second pulse in the output signal of the analog-digital conversion circuit.

In this case, the driving waveform is analog-digital converted by the analog-digital conversion circuit, and the maximum point of the first pulse and the first pulse and the first pulse of the output signal analog-digital converted by the maximum / minimum detecting means. Two
The minimum point between the pulse and the pulse is detected. As a result, the first
It is possible to easily and accurately detect the time difference from the maximum point of the pulse to the minimum point between the first pulse and the second pulse.

(11) Eleventh Invention A display device according to an eleventh invention is the same as the display device according to any one of the second through tenth inventions, except that among the plurality of discharge cells, discharge cells to be turned on at the same time are selected. It further comprises a lighting rate detecting means for detecting a lighting rate, and a reference value control means for controlling a reference value according to the lighting rate detected by the lighting rate detecting means.

In this case, since the lighting rate of the discharge cells to be lit at the same time among the plurality of discharge cells is detected and the reference value is controlled according to the detected lighting rate, the first value is set in the optimum state according to the lighting rate. The first and second discharges can be generated to improve the luminous efficiency, and the first and second discharges can be repeatedly and stably generated. Therefore, even if the lighting rate changes, the discharge can be stably repeated, and the luminous efficiency with respect to the input power can be improved to reduce the power consumption.

(12) Twelfth Invention A display device according to a twelfth invention is the display device according to the eleventh invention, wherein the reference value control means stores in advance a reference value corresponding to the lighting rate. It includes means.

In this case, the circuit configuration and the calculation time for calculating the reference value according to the lighting rate can be deleted.

(13) Thirteenth Invention A display device according to a thirteenth invention is the display device according to the eleventh or twelfth invention, wherein one field is divided into a plurality of subfields, and each subfield is divided. In order to discharge the selected discharge cell and perform gradation display,
The lighting rate detecting means further includes a subfield lighting rate detecting means for detecting a lighting rate of each subfield, and the reference value control means is provided with the converting means for converting the image data of one field into the image data of each subfield. The reference value is controlled according to the lighting rate detected by the subfield lighting rate detection means.

In this case, since the reference value can be controlled according to the lighting rate detected for each subfield,
Even when gradation display is performed, the first and second discharges can be performed in an optimum state according to the lighting rate.

(14) Fourteenth Invention A display device according to a fourteenth invention is the display device according to any one of the first to thirteenth invention, wherein the driving means is
The voltage of the drive waveform is reduced by the first discharge, and the voltage of the drive waveform is increased again after the first discharge is at least weakened, so that the second discharge is generated following the first discharge. is there.

In this case, in the first discharge, since only the minimum electric power required for the discharge is applied, the saturation of the ultraviolet rays is relaxed by the current limitation from the moment the first discharge begins to weaken, and the first discharge is discharged. Luminous efficiency is improved. As a result, the first discharge having a high luminous efficiency is performed in all the discharge cells to be lit, and the second discharge is further performed. As a result, the luminous efficiency of all the discharge cells to be lit can be improved.

(15) Fifteenth Invention A driving method of a display device according to a fifteenth invention is a driving method of a display device which selectively discharges a plurality of discharge cells to display an image. Generating a drive waveform having continuous first and second pulses to generate a second discharge after generating the first discharge in the discharge cell, and the first and the second of the drive waveforms. Controlling the driving means at the first and second timings to generate the second pulse; and detecting a time difference between the first pulse and the second pulse of the driving waveform generated by the driving means. And a step of correcting at least one of the first and second timings based on the detected time difference.

In the method of driving the display device according to the present invention, the driving means is controlled at the first and second timings so that the first and second continuous driving means are provided.
A drive waveform having pulses of is generated. Thereby,
After the first discharge is generated in the selected discharge cell in the display panel, the second discharge is generated.

In this case, the voltage of the drive waveform (first pulse) is reduced by the first discharge, and the voltage of the drive waveform is increased again after the first discharge is at least weakened (second pulse).
Pulse), it is possible to generate the second discharge subsequent to the first discharge. As a result, since only the minimum electric power required for the discharge is applied in the first discharge, the saturation of the ultraviolet rays is relaxed by the current limitation from the moment the first discharge begins to weaken, and the luminous efficiency of the first discharge is reduced. Is improved.
As a result, the first discharge having a high luminous efficiency is performed in all the discharge cells to be lit, and the second discharge is further performed. Therefore, the luminous efficiency of all the discharge cells to be lit can be improved.

Further, the time difference between the first pulse and the second pulse of the driving waveform generated by the driving means is detected,
At least one of the first and second timings is corrected based on the detected time difference. Therefore, even when the characteristics of the driving means vary due to the temperature change of the display panel or the driving means or the difference in the production lot, the time difference between the first and second discharges can be accurately controlled. As a result, it becomes possible to drive the discharge cells so as to emit light in a state of good light emission efficiency.

[0060]

BEST MODE FOR CARRYING OUT THE INVENTION An AC type plasma display device will be described below as an example of a display device according to the present invention.

(First Embodiment) FIG. 1 shows a first embodiment of the present invention.
FIG. 3 is a block diagram showing a configuration of a plasma display device according to the embodiment of FIG.

The plasma display device shown in FIG.
D converter (analog / digital converter) 1, video signal-subfield correlator 2, subfield processor (basic control signal generator) 3, data driver 4, scan driver 5, sustain driver 6, PDP (plasma display) Panel) 7, a subfield lighting rate measuring device 8, output detectors 15 and 16, and drive circuit transmission delay time correcting devices 17 and 18.

The video signal VD is input to the A / D converter 1. The A / D converter 1 converts the analog video signal VD into digital image data and outputs the digital image data to the video signal-subfield correlator 2. Since the video signal-subfield correlator 2 divides one field into a plurality of subfields for display, it creates image data SP of each subfield from the image data of one field and outputs it to the subfield processor 3. To do.

The subfield processor 3 creates a data driver drive control signal DS from the image data SP for each subfield and outputs it to the data driver 4. Further, the subfield processor 3 creates a scan driver drive control signal from the image data SP for each subfield, the subfield lighting rate signal SL, etc., and outputs it to the scan driver 5 and the drive circuit transmission delay time corrector 17. In addition, a sustain driver drive control signal is created and output to the sustain driver 6 and the drive circuit transmission delay time corrector 18. Note that FIG. 1 shows control signals CS1 to CS4 included in the scan driver drive control signal and control signals US1 to US4 included in the sustain driver drive control signal.

The PDP 7 includes a plurality of address electrodes (data electrodes) 11, a plurality of scan electrodes (scan electrodes) 12 and a plurality of sustain electrodes (sustain electrodes) 13. The plurality of address electrodes 11 are arranged in the vertical direction of the screen, and the plurality of scan electrodes 12 and the plurality of sustain electrodes 13 are arranged.
Are arranged horizontally on the screen. In addition, the plurality of sustain electrodes 13 are commonly connected. Address electrode 11, scan electrode 12, and sustain electrode 13
Discharge cells 14 are formed at each intersection of
4 constitutes a pixel on the screen. Only one discharge cell 14 is shown in FIG.

The data driver 4 is connected to the plurality of address electrodes 11 of the PDP 7. Scan driver 5
Is internally provided with a drive circuit (driver IC) provided for each scan electrode 12, and each drive circuit is connected to the corresponding scan electrode 12 of the PDP 7. The sustain driver 6 is connected to the plurality of sustain electrodes 13 of the PDP 7.

The data driver 4 applies a write pulse to the corresponding address electrode 11 of the PDP 7 according to the image data SP in the write period according to the data driver drive control signal DS.

According to the scan driver drive control signal, the scan driver 5 sequentially applies the write pulse to the plurality of scan electrodes 12 of the PDP 7 while shifting the shift pulse in the vertical scanning direction in the write period. As a result, address discharge is performed in the corresponding discharge cell 14.

Further, the scan driver 5 responds to the control signals CS2, CS4 given from the subfield processor 3 and the control signals CS1a, CS3 given from the drive circuit transmission delay time corrector 17 in the sustain period. The sustain pulse Psc is applied to the plurality of scan electrodes 12 of the PDP 7. On the other hand, sustain driver 6
Is a control signal U supplied from the subfield processor 3.
In response to the control signals US1a, US3 provided from S2, US4 and the drive circuit transmission delay time corrector 18, the sustain electrodes 13 of the PDP 7 are maintained in the sustain period.
18 for the sustain pulse Psc of the scan electrode 12.
Sustain pulses Psu with a phase difference of 0 ° are simultaneously applied.
As a result, the sustain discharge is performed in the corresponding discharge cell 14. As will be described later, each of the sustain pulse Psc applied to the scan electrode 12 and the sustain pulse Psu applied to the sustain electrode 13 has a first pulse (first pulse) in order to generate continuous first and second discharges. It has a double peak waveform consisting of a first peak and a second pulse (second peak).

The output detector 15 detects the first rising edge and the second rising edge of the sustain pulse Psc supplied from the scan driver 5. The drive circuit transmission delay time corrector 17 calculates the time difference between the first rising edge and the second rising edge of the sustain pulse Psc detected by the output detector 15, and transfers the control signal CS1 given from the subfield processor 3. The delay time is corrected, the corrected control signal CS1a is output to the scan driver 5, and
Control signal CS3 given from subfield processor 3
To the scan driver 5.

The output detector 16 includes the sustain driver 6
The first rising edge and the second rising edge of the sustain pulse Psu given by the above are detected. The drive circuit transmission delay time compensator 18 calculates the time difference between the first rise and the second rise of the sustain pulse Psc detected by the output detector 16, and transmits the control signal US1 given from the subfield processor 3. The delay time is corrected and the corrected control signal US1a is output to the sustain driver 6.

The subfield lighting rate measuring device 8 detects the lighting rate of the discharge cells 14 simultaneously driven on the PDP 7 from the image data SP for each subfield, and outputs the result as the subfield lighting rate signal SL. Output to the processor 3.

Here, the lighting rate is defined as a discharge cell, which is the minimum unit of the discharge space that can be independently controlled to be in a lighting / non-lighting state. Number) / (P
The total number of discharge cells of DP).

Specifically, the subfield lighting rate measuring device 8 is decomposed into 1-bit information which is generated by the video signal-subfield correlating device 2 and represents lighting / non-lighting of discharge cells for each subfield. Calculate the lighting rate of all subfields separately using the video signal information,
The result is output to the subfield processor 3 as the subfield lighting rate signal SL.

For example, the subfield lighting rate measuring device 8
Is provided with a counter therein, and when the video signal information decomposed into 1-bit information indicating lighting / non-lighting indicates lighting, the total number of lighting discharge cells is increased by incrementing the value of the counter by one. It is obtained for each field, and this is divided by the number of all the discharge cells of the PDP 7 to obtain the lighting rate.

The scan driver 5 and the sustain driver 6 have control signals CS1a and CS1 as described later.
2, CS3, CS4 and control signals US1a, US2
According to US3 and US4, the second rising timing of the sustain pulses Psc and Psu is changed according to the subfield lighting rate signal SL in the sustain period.

In the plasma display device shown in FIG. 1, the ADS (Address Displa
y-Period Separation (address / display period separation) method is used. FIG. 2 is a diagram for explaining an ADS method applied to the plasma display device shown in FIG. Although FIG. 2 shows an example of a negative pulse that discharges when the drive waveform falls, the basic operation is the same as in the case of a positive pulse that discharges when the drive waveform rises.

In the ADS method, one field (1/60
(Second = 16.67 ms) is temporally divided into a plurality of subfields. For example, when displaying 256 gradations with 8 bits, one field is divided into eight subfields SF1.
To SF8. In addition, each subfield SF1 to
The SF8 is divided into a setup (initialization) period P1, a writing period P2, and a sustaining period P3. The setup (initialization) process of each subfield is performed in the setup period P1, and the discharge cells 14 lighted in the writing period P2. The address discharge for selecting is performed, and the sustain discharge for display is performed in the sustain period P3.

In the setup period P1, a single reset pulse is applied to the sustain electrodes 13 and the scan electrodes 12 (n in FIG. 2 are displayed as the number of scan electrodes, but actually, for example, 480). Scan electrodes are used) and each has a single reset pulse. As a result, preliminary discharge is performed.

In the writing period P2, the scan electrodes 12 are sequentially scanned, and a predetermined writing process is performed only on the discharge cells 14 that have received the writing pulse from the address electrodes 11. As a result, address discharge is performed.

In the sustain period P3, sustain pulses corresponding to the weighted values of the subfields SF1 to SF8 are output to the sustain electrode 13 and the scan electrode 12. For example, in the subfield SF1, the sustain pulse is applied once to the sustain electrode 13 and the sustain pulse is applied once to the scan electrode 12. Since each sustain pulse has the first and second pulses, the write period P2
The discharge cell 14 selected in 4 performs the sustain discharge four times. In the subfield SF2, the sustain pulse is applied twice to the sustain electrode 13 and the sustain pulse is applied twice to the scan electrode 12, and the discharge cells 14 selected in the writing period P2 perform sustain discharge eight times.

As described above, each sub-field SF1 ...
In SF8, the sustain electrode 13 and the scan electrode 1
2 times 1 time, 2 times, 4 times, 8 times, 16 times, 32 times, 64
The sustain pulse is applied 128 times, and the discharge cell 14 emits light with brightness (luminance) according to the number of pulses. That is, the sustain period P3 is a period in which the discharge cells 14 selected in the writing period P2 are discharged a number of times according to the weighting amount of brightness.

As described above, the subfields SF1 to SF
8 is 1, 2, 4, 8, 16, 32, 6 respectively.
The brightness of 4 and 128 are weighted, and by combining these subfields SF1 to SF8,
The brightness level can be adjusted in 256 steps from 0 to 255. Note that the number of subfield divisions, weighting values, and the like are not particularly limited to the above example, and various changes are possible. For example, in order to reduce a moving image pseudo contour, the subfield SF8 is divided into two. The weighting value of the two subfields may be set to 64.

Next, the sustain driver 6 shown in FIG. 1 will be described in detail. FIG. 3 is a circuit diagram showing a configuration of the sustain driver 6 shown in FIG. In the following description, an example of a positive pulse that discharges when the drive waveform rises is shown, but a negative pulse that discharges at the fall may be used.

The sustain driver 6 shown in FIG.
It includes T (field effect transistor) Q1 to Q4, a recovery capacitor C1, a recovery coil L, diodes D1 and D2, and FET drivers 61 to 64.

The node N1 is connected to, for example, 480 sustain electrodes 13, but FIG. 3 shows the panel capacitance Cp corresponding to the total capacitance between the plurality of sustain electrodes 13 and the ground terminal. . Note that this point is the same in FIG.

The recovery capacitor C1 is connected between the node N3 and the ground terminal. The recovery coil L is connected between the node N1 and the node N2.

The FET Q1 is connected between the power supply terminal V1 receiving the voltage Vsus and the node N1. The FET driver 61 responds to the control signal US1a provided from the drive circuit transmission delay time compensator 18 of FIG.
To the gate of FET Q1. The FET Q2 is connected between the node N1 and the ground terminal. The FET driver 62 outputs the control signal S2 to the FET Q2 in response to the control signal US2 provided from the subfield processor 3 of FIG.
Give to the gate.

The FET Q3 and the diode D1 are connected in series between the node N3 and the node N2. F
The ET driver 63 gives the control signal S3 to the gate of the FET Q3 in response to the control signal US3 given from the drive circuit transmission delay time corrector 18 of FIG. Diode D2
And the FET Q4 are connected in series between the node N2 and the node N3. The FET driver 64 provides the control signal S4 to the gate of the FET Q4 in response to the control signal US4 provided from the subfield processor 3 of FIG.

FIG. 4 is a timing chart showing the operation of the sustain driver 6 shown in FIG. 3 during the sustain period. In Figure 4,
The voltage of the node N1 in FIG. 3 (sustain pulse Psu), PDP
The discharge intensity LR of 7 and the control signals S1 to S4 input to the FETs Q1 to Q4 are shown.

The discharge intensity is measured by the following method. In the case of a PDP using a mixed gas containing xenon, its emission uses vacuum ultraviolet rays (wavelength 147 nm) generated at the time of discharge from xenon at the resonance level. This vacuum ultraviolet ray cannot be observed in the air through the front glass of the PDP. On the other hand, near-infrared rays (wavelength 828 nm) are emitted during the transition of electrons from the energy level higher than the resonance level to the resonance level, and it is considered that the near-infrared rays are almost proportional to the discharge intensity. In the calligraphy,
Near-infrared intensity is measured for one discharge cell using an avalanche photodiode or the like having spectral sensitivity characteristics in the near-infrared region, and this is taken as the discharge intensity.

Therefore, the continuous first described below
The second discharge and the second discharge mean that the second discharge is performed after the first discharge for each discharge cell, and all the discharge cells to be lighted of the PDP are always discharged twice. This does not include the case where a discharge cell that discharges early and a discharge cell that discharges slowly due to variations in cells are discharged only once at different timings.

First, in the period TA, the control signal S2 goes low and the FET Q2 turns off, and the control signal S3 goes high and the FET Q3 turns on. At this time, the control signal S1 is at a low level and the FET Q1 is off, and the control signal S4 is at a low level and the FET Q4 is off. Therefore, the recovery capacitor C1 is connected to the recovery coil L via the FET Q3 and the diode D1, and the voltage of the node N1 smoothly rises from the ground potential Vg due to LC resonance caused by the recovery coil L and the panel capacitance Cp. At this time, the charge of the recovery capacitor C1 is FETQ.
3, is discharged to the panel capacitance Cp via the diode D1 and the recovery coil L.

When the voltage of the node N1 rises, exceeds the discharge start voltage in the sustain period, and the discharge cells 14 start the first discharge, the discharge intensity LR starts to rise. After that, when the first discharge becomes large to some extent and the required discharge current exceeds the current supply capacity of the circuit composed of the recovery capacitor C1 and the recovery coil L, the voltage of the node N1 changes from the maximum value Vpu to the minimum value Vpb. , The first discharge weakens, and the discharge intensity LR also decreases accordingly. From the moment the first discharge begins to weaken, the saturation of the amount of UV emission begins to be relaxed by current limitation, and then the saturation of UV with respect to the discharge current decreases, and an extra discharge current that does not contribute to light emission does not flow, so the luminous efficiency is improved. improves.

Next, in the period TB, when the control signal S1 goes high and the FET Q1 turns on, and the control signal S3 goes low and the FET Q3 turns off, the node N1
Voltage rises to Vsus.

When the voltage of the node N1 rises from the minimum value Vpb and exceeds the discharge start voltage again, the discharge cell 14 is set to the first
The second discharge is started following the discharge of 1, and the discharge intensity LR also starts to rise again. At this time, following the first discharge, the second discharge
Since the discharge of the first discharge is generated, the first discharge is generated during the second discharge.
The priming effect of charged particles and excited atoms remaining in the discharge space due to the discharge of the
The second discharge can be stably performed.

Further, during the second discharge, the discharge current is sufficiently supplied from the power supply terminal V1 without being limited, so that the second discharge has a sufficient intensity, that is, a peak larger than the peak value of the first discharge. The wall charge has a value, and the wall charges necessary for the next first discharge are sufficiently stored, and the sustain discharge can be stably repeated.

After that, when the voltage of the node N1 is held at Vsus, the second discharge is stopped as in the conventional case, and the discharge intensity LR is also reduced accordingly.

As described above, the discharge cell 14 is continuously connected to the first
It is considered that the emission efficiency is improved by generating the second discharge for the following reason.

First, in the first discharge, the recovery capacitor C
The electric charge necessary for discharging is supplied from 1 through the recovery coil L, and thus the supplied current is limited to a value determined by the panel capacitance Cp and the resonance circuit of the recovery coil L. Further, since the supply source of the discharge current is the recovery capacitor C1, sufficient charge cannot be supplied when the discharge becomes large, and the first discharge weakens or stops as the voltage of the node N1 drops. That is, in the first discharge, unlike the case of the discharge by the current supply from the power supply which is connected without the intermediary of the inductance element or the like and can supply a sufficient charge, the minimum charge necessary for the discharge is supplied. From the moment the first discharge begins to weaken, the saturation of the amount of UV emission starts to be relaxed by current limitation, and then the saturation of UV with respect to the discharge current decreases. Therefore, an extra discharge current that does not contribute to the phosphor emission of the discharge cell 14 does not flow, so that the luminous efficiency with respect to the input power can be improved.

In the second discharge, the wall voltage is reduced by the first discharge, and the effective voltage applied to the discharge space is considerably low, that is, excessive due to the priming effect utilizing the space charges remaining in the discharge space. The discharge is performed without applying a voltage, and the luminous efficiency is improved even in the second discharge.

As described above, since the luminous efficiency can be improved by continuously performing the first and second discharges, the luminous efficiency with respect to the input power can be improved and the power consumption can be reduced. Further, when the input power is not reduced, the power saved by the improvement of the light emission efficiency can be applied to the improvement of the display brightness by the increase of the number of times of light emission.

Next, in the period TC, the control signal S1 goes low and the FET Q1 turns off, and the control signal S4 goes high and the FET Q4 turns on. Therefore,
Recovery capacitor C1 is diode D2 and FET Q4
Is connected to the recovery coil L via LC, and the voltage at the node N1 gradually drops due to LC resonance caused by the recovery coil L and the panel capacitance Cp. At this time, the electric charge stored in the panel capacitance Cp is stored in the recovery capacitor C1 via the recovery coil L, the diode D2 and the FET Q4, and the electric charge is recovered.

Next, in the period TD, the control signal S2 goes high and the FET Q2 turns on, and the control signal S4 goes low and the FET Q4 turns off. Therefore,
Node N1 is connected to the ground terminal, the voltage of node N1 drops, and is fixed at ground potential Vg.

By repeating the above operation in the sustain period, when the ground potential Vg rises to the voltage Vsus, the periodic sustain pulse Psu for continuously generating the first and second discharges is applied to the plurality of sustain electrodes. 1
3 can be applied.

In the same manner as above, the scan electrode 1
2, the scan driver 5 causes the sustain pulse P
A sustain pulse Psc having a waveform similar to that of su and having a phase shift of 180 ° is periodically applied.

FIG. 5 mainly shows the output detector 16 shown in FIG.
3 is a circuit diagram showing the configuration of FIG. Output detector 16 shown in FIG.
Are resistors R1 to R4, bipolar transistors (hereinafter,
Q5, a capacitor C2, diodes D3 and D4, and a buffer circuit 60. The resistor R4 and the capacitor C2 form an RC differentiating circuit 160.

The node N4 of the output detector 16 is connected to the node N1 of the sustain driver 6. Note that FIG. 5 shows the panel capacitance Cp corresponding to the total capacitance between the plurality of sustain electrodes 13 and the ground terminal.

The resistor R1 is connected between the node N4 and the node N5, and the resistor R2 is connected between the node N5 and the ground terminal. The base of the transistor Q5 is the node N
5, the collector is connected to the power supply terminal receiving the voltage + 15V, and the emitter is connected to the ground terminal via the resistor R3. The capacitor C2 is connected between the emitter of the transistor Q5 and the node N6, and the resistor R4 is connected between the node N6 and the ground terminal. The cathode of the diode D3 is connected to the power supply terminal that receives the voltage + 5V, and the anode is connected to the node N6. The cathode of the diode D4 is connected to the node N6, and the anode is connected to the ground terminal. The input terminal of the buffer circuit 60 is connected to the node N6, and the output terminal thereof is connected to the drive circuit transmission delay time corrector 18. Buffer circuit 6
One power source terminal of 0 is connected to the power source terminal for receiving the voltage + 5V, and the other power source terminal is connected to the ground terminal.

FIG. 6 is a waveform diagram of each part of the output detector 16 shown in FIG. Next, referring to the waveform diagram of FIG.
The operation of the output detector 16 will be described.

The sustain pulse Psu output from the sustain driver 6 is applied to the node N4 of the output detector 16 (see FIG. 6A). Here, the sustain pulse Psu
The maximum voltage of is 175V.

The sustain pulse Psu is voltage-divided by the resistors R1 and R2, and the voltage-divided voltage is applied to the transistor Q5.
Given to the base of. Thereby, the transistor Q5
A voltage DIV having a waveform similar to that of the sustain pulse Psu appears at the emitter of the (see FIG. 6B). This voltage DIV
The maximum voltage is 15V.

The RC differentiating circuit 160 includes a transistor Q5
Differentiate the voltage DIV of the emitter of the. As a result, the differentiated voltage DIF is output to the node N6 (see FIG. 6).
(See (c)). The diode D3 has a voltage D of the node N6.
Limit the highest value of IF to 5V and the lowest value to 0V.

The buffer circuit 160 binarizes the voltage DIF of the node N6 with a predetermined threshold value. Thereby, the detection signal DE having the first and second pulses of the voltage 5V
T is output (see FIG. 6D). In the detection signal DET, the time difference T2 between the rising points of the first and second pulses corresponds to the time difference between the rising of the control signal S3 and the rising of the control signal S1, that is, the start timing of the first discharge and the second timing. Corresponds to the time difference from the discharge start timing of.

FIG. 7 is a block diagram showing the sub-field processor 3, sustain driver 6, output detector 16 and drive circuit transmission delay time corrector 18 of FIG.

As shown in FIG. 7, the drive circuit transmission delay time corrector 18 includes a control timing corrector 181, a correction time adder 182 and a control timing comparator 183. In FIG. 7, only the FET drivers 61 and 63 and the FETs Q1 and Q3 included in the sustain driver 6 are shown.

8 and 9 are timing charts for explaining the operation of the drive circuit transmission delay time compensator 18 of FIG. 7, FIG. 8 shows a state before correction, and FIG. 9 shows a state after correction. Show. Here, the operation of the drive circuit transmission delay time corrector 18 in FIG. 7 will be described with reference to FIGS. 8 and 9. Note that FIG. 8 shows the first sustain pulse Psu, and FIG. 9 shows the second sustain pulse Psu continuing from FIG.

First, the control signal US3 output from the subfield processor 3 rises to the high level,
As shown in (a), the control signal US3 output from the control timing corrector 181 rises to a high level.
As a result, the control signal S3 given to the FET Q3 of the sustain driver 6 rises to the high level.

After a lapse of the delay time T1 from the rising of the control signal US3, the control signal US1 output from the subfield processor 3 rises to the high level, and FIG.
As shown in, the control signal US1a output from the control timing corrector 181 rises to the high level. As a result, the control signal S1 applied to the FET Q1 of the sustain driver 6 rises to the high level.

In the initial state, as shown in FIG.
The correction signal DE4 output from the correction time adder 182 remains low level and does not change. That is, the correction time is 0
Is.

As shown in FIG. 8D, the control signals S1,
In response to S3, sustain driver 6 outputs sustain pulse Psu having the first pulse and the second pulse. As described with reference to FIGS. 5 and 6, the output detector 16 receives the first pulse of the sustain pulse Psu as shown in FIG.
And a detection signal DET indicating the second rising edge. The detection signal DET has a first pulse that rises in response to the first rise of the sustain pulse Psu and a second pulse that rises in response to the second rise of the sustain pulse Psu. Here, the time difference between the rising edge of the first pulse and the rising edge of the second pulse of the detection signal DET is T2.

The control timing comparator 183 receives the control signals US1 and US3 from the subfield processor 3 and the detection signal DET from the output detector 16. The control timing comparator 183 controls the control signal U
The delay time detection signal DE1 shown in FIG. 8 (g) is generated from S1 and US3, the time difference detection signal DE2 shown in FIG. 8 (f) is generated from the detection signal DET, and the delay time detection signal DE1 and the time difference detection signal are generated. Compare with DE2. The delay time detection signal DE1 is at the high level only during the delay time T1 from the rising of the control signal US3 to the rising of the control signal US1. The time difference detection signal DE2 becomes high level only during the time difference T2 between the rising edge of the first pulse and the rising edge of the second pulse of the detection signal DET.

The control timing comparator 183 is shown in FIG.
As shown in (h), the correction time detection signal DE3 that rises to the high level for the time difference T3 between the high level period of the time difference detection signal DE2 and the high level period of the delay time detection signal DE1 is output. That is, T3 = T2-T1
Is.

The correction time adder 182 holds the correction time detection signal DE3 output from the control timing comparator 183, adds the held correction time detection signal DE3 and the correction signal DE4 described later, and outputs the addition result. It is output as the correction signal DE4. Before the addition, the correction signal DE4 is at the low level as shown in FIG. 8 (i).
Here, the high level period of the correction signal DE4 is referred to as a correction time T4. The initial value of the correction time T4 is 0.

As shown in FIG. 8J, after the addition, the correction signal DE4 rises to the high level for the time difference T3. As a result, the correction time T4 by the correction signal DE4 becomes the time difference T3. That is, T4 = T3 + T4.

Next, the control signal US3 output from the sub-field processor 3 rises to the high level,
As shown in (a), the control signal US3 output from the control timing corrector 181 rises to a high level.
As a result, the control signal S3 given to the FET Q3 of the sustain driver 6 rises to the high level.

Thereafter, the control signal US1 output from the subfield processor 3 rises to the high level. At this time, the correction signal D output from the correction time adder 182
As shown in FIG. 9B, E4 becomes high level for the correction time T4. Thereby, the control timing corrector 1
As shown in FIG. 9C, the control signal US1a output from 81 rises to a high level when the correction delay time T5 has elapsed from the rise of the control signal US3. As a result, the control signal S3 given to the FET Q1 of the sustain driver 6 rises to the high level. Here, the correction delay time T5 is expressed by the following equation.

T5 = T1−T4 The correction delay time T5 corresponds to the period TA in FIG. Figure 9
As shown in (d), sustain driver 6 outputs sustain pulse Psu having the first pulse and the second pulse in response to control signals S1 and S3. As shown in FIG. 9E, the output detector 16 outputs the detection signal DET indicating the first and second rising edges of the sustain pulse Psu.

The control timing comparator 183 generates the delay time detection signal DE1 shown in FIG. 9 (g) from the control signals US1 and US3, and the time difference detection signal DE2 shown in FIG. 9 (f) from the detection signal DET. The delay time detection signal DE1 is generated and the time difference detection signal DE2 is compared. The delay time detection signal DE1 becomes high level for the delay time T1. Further, the time difference detection signal DE2 becomes high level for the time difference T2. In this case, the control signal US1a has the correction time T longer than the time when the correction delay time T5 has passed from the rising of the control signal US3, that is, the time when the delay time T1 has passed.
Since it rises to a high level at a time point that is four points before, the time difference T2 between the rising edge of the first pulse and the rising edge of the second pulse of the detection signal DET becomes equal to the delay time T1.

The control timing comparator 183 is shown in FIG.
As shown in (h), the correction time detection signal DE3 that rises to the high level for the time difference T3 between the delay time T1 and the time difference T2 is output. In this case, the delay time T1 and the time difference T
The time difference T3 from 2 is 0. Therefore, the correction time detection signal DE3 remains low level and does not change.

The correction time adder 182 holds the correction time detection signal DE3 output from the control timing comparator 183, adds the held correction time detection signal DE3 and the correction signal DE4, and adds the addition result to the correction signal. DE4
Output as. Here, as shown in FIG.
The correction signal DE4 before addition rises to the high level for the correction time T4. Therefore, the correction signal DE4 after addition also rises to the high level for the correction time T4.

In this way, the time difference T2 between the rising edge of the first pulse and the rising edge of the second pulse of the detection signal DET output from the output detector 16 is the control signal US.
The rising timing of the control signal US1a is controlled so as to be equal to the delay time T1 from the rising of 3 to the rising of the control signal US1. Thereby, F
Even if the transmission delay time of the control signal varies due to the temperature change of the ET drivers 61 and 63 and the FETs Q1 and Q3 or the difference in the production lot, the sustain pulse Psu is generated.
It is possible to keep the time difference between the first rising and the second rising of the above and to keep the time difference between the first discharging and the second discharging constant. Therefore, it becomes possible to drive the discharge cells at a timing where the luminous efficiency is always maximized.

FIG. 10 is a block diagram showing the configuration of the scan driver shown in FIG. As shown in FIG. 10, the scan driver 5 includes a sustain pulse generator (sustain circuit) 51, an initialization pulse generator 52, a write pulse generator 53, and a sustain / initialization combiner 54.

The sustain pulse generating section 51 has a control signal CS1 supplied from the drive circuit transmission delay time compensator 17 of FIG.
a, CS3 and sustain pulse Psc in response to control signals CS2, CS4 provided from subfield processor 3
To occur. The configuration and operation of sustain pulse generator 51 are similar to the configuration and operation of sustain driver 6 shown in FIG. The sustain pulse Psc has a double-peak waveform including a first pulse (first peak) and a second pulse (second peak), like the sustain pulse Psu shown in FIG.

Initializing pulse generator 52 generates initializing pulse Pse in response to the scan driver drive control signal supplied from subfield processor 3. The write pulse generator 53 generates the write pulse Pw in response to the scan driver drive control signal provided from the subfield processor 3. The maintenance / initialization combining unit 54
The sustain pulse Psc and the reset pulse generator 5 generated from the sustain pulse generator 51 in response to the scan driver drive control signal supplied from the subfield processor 3.
The initialization pulse Pse generated from 2 is synthesized. Initialization pulse Ps output from the maintenance / initialization combining unit 54
e, the write pulse Pw generated from the write pulse generator 53 and the sustain pulse Psc output from the sustain / initialization synthesizer 54 are scanned during the setup period P1, the write period P2, and the sustain period P3 shown in FIG. 2, respectively. It is sequentially applied to the scan electrodes 12 via a driver IC (integrated circuit) 55.

The sustain pulse Psc generated from the sustain pulse generator 51 is applied to the output detector 15. The configuration and operation of the output detector 15 are similar to the configuration and operation of the output detector 16 shown in FIG.

Further, the configuration and operation of drive circuit transmission delay time corrector 17 shown in FIG. 1 are the same as the configuration and operation of drive circuit transmission delay time corrector 18 shown in FIG.

In this case, the time difference between the rising edge of the first pulse and the rising edge of the second pulse of the detection signal DET output from the output detector 15 is the delay time from the rising edge of the control signal CS3 to the rising edge of the control signal CS1. The rising timing of the control signal CS1a is controlled so as to be equal to. As a result, even when the transmission delay time of the control signal varies due to the temperature change of the FET driver or FET included in the sustain pulse generating unit 51 or the difference in the production lot, the first rise and the second rise of the sustain pulse Psc. It is possible to keep a constant time difference from the rising of the first discharge and a constant time difference between the first discharge and the second discharge. Therefore, it becomes possible to drive the discharge cells at a timing where the luminous efficiency is always maximized.

FIG. 11 is a block diagram showing a structure of a main part of the subfield processor 3 shown in FIG.

The subfield processor 3 shown in FIG.
Lighting rate / delay time LUT (look-up table) 3
1, a delay time determination unit 32, a basic control signal generator 33, and delay units 34 and 35.

The lighting rate / delay time LUT 31 is connected to the delay time determining unit 32 and stores the relationship between the lighting rate and the delay time T1 based on the experimental data in a table format. For example, when the lighting rate is 30%, the delay time T1 is 65
0 ns is stored, and the delay time is T for the lighting rate of 50%.
700 ns is stored as 1, and 750 ns is stored as the delay time T1 for the lighting rate of 70%.

The delay time determining unit 32 reads out and reads the corresponding delay time T1 from the lighting rate / delay time LUT 31 according to the subfield lighting rate signal SL output from the subfield lighting rate measuring device 8 in FIG. Delay time T
The delay devices 34 and 35 are controlled so that the delay operation is performed by one. The determination of the delay time T1 is not particularly limited to the example in which the relationship between the lighting rate and the delay time T1 based on the experimental data is stored in the table format as described above, and the relationship between the lighting rate and the delay time T1 is represented. The delay time T1 corresponding to the lighting rate may be obtained from the approximate expression.

The basic control signal generator 33 controls the control signal CS
1-CS4 and control signals US1-US4.
The control signal CS1 is given to the drive circuit transmission delay time corrector 17 via the delay device 34, the control signals CS2 and CS4 are given to the scan driver 5, and the control signal CS3 is given to the drive circuit transmission delay time corrector 17. . Further, the control signal US1 is given to the drive circuit transmission delay time corrector 18 via the delay device 35, the control signals US2 and US4 are given to the sustain driver 6, and the control signal US3 is given to the drive circuit transfer delay time corrector 18. Given.

The delay device 34 receives the input control signal CS1.
Delay of the control signal CS1 output by the delay time T1 determined by the delay time determining unit 32 with respect to the rising edge of the delay time.
The rising edge of the control signal US1 is delayed by the delay time T1 determined by.

With the above-described structure, the subfield processor 3 changes the delay time T1 according to the lighting rate measured by the subfield lighting rate measuring device 8 to control the control signal CS.
1, controls the timing when US1 goes high.

As described above, in the present embodiment, the time difference T2 between the rising edge of the first pulse and the rising edge of the second pulse of the detection signal DET is the delay from the rising edge of the control signal US3 to the rising edge of the control signal US1. Time T1
The rising timing of the control signal US1a is controlled so as to be equal to. Therefore, in the following description, the sub-field processor 3 is used to control the delay time T1 from the rising of the control signal US3 to the rising of the control signal US1 according to the lighting rate for each sub-field, and thus the time difference of the detection signal DET is controlled. An example of controlling T2 will be described.

FIG. 12 is a diagram showing the relationship between the luminous efficiency ratio and the time difference T2 of the detection signal DET. The horizontal axis of FIG. 12 is the time difference T2 between the rising edge of the first pulse and the rising edge of the second pulse of the detection signal DET, and the vertical axis is each time difference T.
2 is the ratio of the luminous efficiency at 2 and the luminous efficiency when the time difference T2 is 500 ns. FIG. 12 shows the case where the lighting rate is 70%. Here, when the time difference T2 is 500 ns, the sustain pulse has a waveform composed of one pulse (one peak).

As shown in FIG. 12, as the time difference T2 between the rising edge of the first pulse and the rising edge of the second pulse of the detection signal DET increases from 500 ns to 675 ns, the luminous efficiency ratio increases from 1 to 1.2. To increase.

FIG. 13 is a diagram showing a control example of the time difference T2 of the detection signal DET according to the lighting rate. The horizontal axis of FIG. 13 is the lighting rate for each subfield, and the vertical axis is the detection signal DE.
The time difference T2 between the rising edge of the first pulse of T and the rising edge of the second pulse.

As shown in FIG. 13, as the lighting rate for each subfield increases from 30% to 70%, the time difference T2 of the detection signal DET changes from 650 ns to 750 ns.
The delay time T1 is controlled so that the time difference T2 of the detection signal DET decreases from 750 ns to 700 ns as the lighting rate increases from 80% to 100%.

FIG. 14 is a diagram showing the relationship between the luminous efficiency ratio and the lighting rate in the control example of FIG. The horizontal axis of FIG. 14 is the lighting rate for each subfield, and the vertical axis is each time difference T2.
Is the ratio of the luminous efficiency at 1 to the luminous efficiency when the time difference T2 is 500 ns.

As shown in FIG. 14, as the lighting rate increases from 30% to 80%, the luminous efficiency ratio increases from 1.02 to 1.22, and the lighting rate increases from 80% to 100%. Therefore, the luminous efficiency ratio is 1.22 to 1.
It has decreased to 17.

As described above, by changing the discharge state according to the lighting rate for each subfield, the sustain discharge can be performed in the optimum state according to the lighting rate for each subfield.

As described above, in the present embodiment, the first and second discharges are continuously generated at the rising edge of the sustain pulse to improve the luminous efficiency with respect to the input power and reduce the power consumption. You can Further, by controlling the time difference between the first rising edge and the second rising edge of the sustain pulse according to the lighting rate for each subfield, it is possible to drive the discharge cells with optimum light emission efficiency according to the lighting rate.

The delay time T1 of rising of the control signals US3 and US1 is set according to the lighting rate of each subfield.
When the delay time is always set constant without controlling the delay time of rising of the control signals SC3 and SC1,
The lighting rate / delay time LUT 31 in the subfield lighting rate measuring device 8 of FIG. 1 and the subfield processing unit 3 of FIG.
The delay time determining unit 32 may not be provided.

In this embodiment, the PDP 7 corresponds to a display panel, the scan driver 5 and the sustain driver 6 correspond to driving means, the subfield processor 3 corresponds to control means and a control signal generating circuit, and output detection is performed. Bowl 1
Reference numerals 5 and 16 correspond to detection means, and drive circuit transmission delay time correction devices 17 and 18 correspond to correction means. Further, the control timing comparator 183 corresponds to the comparing means, the correction time adder 182 corresponds to the adding means, and the control timing corrector 1
Reference numeral 81 corresponds to the timing shift means.

The RC differentiating circuit 160 corresponds to a differentiating circuit, and the buffer circuit 60 corresponds to a rectangular wave signal generating circuit. Further, the FET driver 63 and the FET Q3 are the first
Of the FET driver 61 and the FET
Q1 constitutes a second drive circuit. FET driver 63
Corresponds to the first driver, and the FET driver 61 is the second
The FET Q3 corresponds to the first transistor, and the FET Q1 corresponds to the second transistor.

The video signal-subfield correlator 2 corresponds to the converting means, the subfield lighting rate measuring device 8 corresponds to the lighting rate detecting means and the subfield lighting rate detecting means, and the lighting rate / delay time LUT31. The delay time determination unit 32 and the delay device 34 correspond to the reference value control means.

(Second Embodiment) FIG. 15 is a block diagram showing the structure of an output detector of a plasma display device according to a second embodiment of the present invention. The configuration of the other parts of the plasma display device of the second embodiment is similar to the configuration of the plasma display device of the first embodiment.

As shown in FIG. 15, the output detector 16a is composed of output detection circuits 161 and 162. The output detection circuit 161 is connected to the output terminal of the FET driver 63 of the sustain driver 6 (see FIG. 3). Further, the output detection circuit 162 is connected to the F of the sustain driver 6.
It is connected to the output terminal of the ET driver 61 (see FIG. 3).

The output detection circuit 161 includes resistors R11 and R1.
2 and a photo coupler PH1. Resistor R11 is FE
It is connected between the output terminal of the T driver 63 and the node N7, and the resistor R12 is connected between the node N7 and the node N8. Photocoupler PH1 has a pair of input terminals connected to nodes N7 and N8, and a pair of power supply terminals connected to a power supply terminal receiving a voltage + 5V and a ground terminal. The detection signal DET3 is output from the output terminal of the photocoupler PH1.

The output detection circuit 162 includes resistors R21 and R2.
2 and a photocoupler PH2. Resistor R21 is FE
It is connected between the output terminal of the T driver 61 and the node N9, and the resistor R22 is connected between the node N9 and the node N10. Photocoupler PH2 has a pair of input terminals connected to nodes N9 and N10, and a pair of power supply terminals connected to a power supply terminal receiving a voltage + 5V and a ground terminal. The detection signal DET1 is output from the output terminal of the photocoupler PH2.

The detection signals DET3 and DET1 output from the output detection circuits 161 and 162 are applied to the drive circuit transmission delay time corrector 18.

FIG. 16 is a waveform diagram of each part of the output detector 16a shown in FIG. Next, the operation of the output detector 16a of FIG. 15 will be described with reference to the waveform diagram of FIG.

Here, the node N8 of the output detection circuit 161 is
Is set to SH, and the node N10 of the output detection circuit 162 is
The potential of is MH.

When the control signal US3 applied to the FET driver 63 rises from the ground potential GND to 5 V as shown in FIG. 16A, the control signal output from the driver FET 63 as shown in FIG. 16B. S3 rises from the potential SH to SH + 15V. The control signal S3 is voltage-divided by the resistors R11 and R12, and the division signal DIV3 appears at the node N7. Divided signal DIV of node N7
3 indicates potentials SH to SH + as shown in FIG.
Stand up to 5V. In response to the divided signal DIV3 from the node N7, as shown in FIG.
The detection signal DET3 output from 1 rises from the ground potential GND to 5V.

As shown in FIG. 16E, the control signal US1a applied to the FET driver 61 is at the ground potential GND.
When rising from 5V to 5V, as shown in FIG.
The control signal S1 output from the driver FET 61 rises from the potential MH to MH + 15V. The control signal S1 is voltage-divided by the resistors R21 and R22, and the division signal DIV1 appears at the node N9. Division signal DI of node N9
V1 is, as shown in FIG. 16 (g), from the potentials MH to MH.
It rises to + 5V. In response to the division signal DIV1 from the node N9, as shown in FIG.
The detection signal DET1 output from H2 is the ground potential GND.
Rises to 5V.

The time difference between the rising edge of the detection signal DET3 and the rising edge of the detection signal DET1 corresponds to the time difference between the rising edge of the control signal S3 and the rising edge of the control signal S1, that is, the start timing of the first discharge and the second discharge. It corresponds to the time difference from the start timing.

FIG. 17 is a block diagram showing the subfield processor 3, the sustain driver 6, the output detector 16a, and the drive circuit transmission delay time corrector 18.

As shown in FIG. 17, drive circuit transmission delay time corrector 18 includes a control timing corrector 181, a correction time adder 182 and a control timing comparator 183. Note that FIG. 17 shows only the FET drivers 61 and 63 and the FETs Q1 and Q3 included in the sustain driver 6.

18 and 19 are timing charts for explaining the operation of the drive circuit transmission delay time compensator 18 of FIG. 17, FIG. 18 shows a state before correction, and FIG. 19 shows a state after correction. Show. Here, the operation of the drive circuit transmission delay time corrector 18 of FIG. 17 will be described with reference to FIGS. 18 and 19. In FIG. 18, the first sustain pulse P
The control signal US3 for generating su is displayed, as shown in FIG.
In FIG. 9, the control signal US3 for generating the second sustain pulse Psu continuing from FIG. 18 is displayed.

First, the control signal US3 output from the subfield processor 3 rises to the high level, and FIG.
As shown in (a), the control signal US3 output from the control timing corrector 181 rises to a high level.
As a result, the control signal S3 given to the FET Q3 of the sustain driver 6 rises to the high level.

After the elapse of the delay time T1 from the rise of the control signal US3, the control signal US1 output from the subfield processor 3 rises to the high level, and FIG.
As shown in (c), the control signal US1a output from the control timing corrector 181 rises to a high level. As a result, the control signal S1 applied to the FET Q1 of the sustain driver 6 rises to the high level.

In the initial state, as shown in FIG. 18B, the correction signal DE output from the correction time adder 182 is output.
4 remains low level and does not change. That is, the correction time is 0.

In response to control signals S1 and S3, sustain driver 6 outputs sustain pulse Psu having the first pulse and the second pulse. As shown in FIG. 18D, the output detection circuit 161 of the output detector 16a (see FIG.
5) outputs the detection signal DET3. In addition, FIG.
As shown in (e), the output detection circuit 162 (FIG. 15) of the output detector 16a outputs the detection signal DET1. Here, the rising of the detection signal DET3 and the detection signal DET
The time difference from the rise of 1 is T6. This time difference T
6 corresponds to the time difference between the rising edge of the control signal S3 and the rising edge of the control signal S1, that is, the time difference between the start timing of the first discharge and the start timing of the second discharge.

The control timing comparator 183 receives the control signals US1 and US3 from the subfield processor 3 and the detection signal DET from the output detector 16a.
3, DET1 is given. Control timing comparator 18
3 generates the delay time detection signal DE1 shown in FIG. 18 (g) from the control signals US1 and US3, and detects the detection signal DET.
The time difference detection signal DE6 shown in FIG. 18 (f) is generated from 1, DET3, and the delay time detection signal DE1 and the time difference detection signal DE6 are compared. Delay time detection signal DE1
Becomes high level only during the delay time T1 from the rising of the control signal US3 to the rising of the control signal US1. The time difference detection signal DE6 is the time difference T between the rising edge of the detection signal DET3 and the rising edge of the detection signal DET1.
It goes high for 6 periods.

The control timing comparator 183 is shown in FIG.
As shown in (h), the correction time detection signal DE3 that rises to the high level by the time difference T3 between the high level period of the time difference detection signal DE6 and the high level period of the delay time detection signal DE1 is output. That is, T3 = T6-T1
Is.

The correction time adder 182 holds the correction time detection signal DE3 output from the control timing comparator 183, adds the held correction time detection signal DE3 to a correction signal DE4 described later, and outputs the addition result. It is output as the correction signal DE4. Before the addition, the correction signal DE4 is at the low level as shown in FIG. 18 (i). Here, the high level period of the correction signal DE4 is referred to as a correction time T4. The initial value of the correction time T4 is 0.

As shown in FIG. 18 (j), after the addition,
The correction signal DE4 rises to the high level for the time difference T3. As a result, the correction time T4 by the correction signal DE4 becomes the time difference T3. That is, T4 = T3 + T4.

Next, the control signal US3 output from the subfield processor 3 rises to the high level, and FIG.
As shown in (a), the control signal US3 output from the control timing corrector 181 rises to a high level.
As a result, the control signal S3 given to the FET Q3 of the sustain driver 6 rises to the high level.

Thereafter, the control signal US1 output from the subfield processor 3 rises to the high level. At this time, the correction signal D output from the correction time adder 182
As shown in FIG. 19B, E4 becomes high level for the correction time T4. As a result, the control signal US1a output from the control timing corrector 181 is
As shown in (c), it rises to the high level when the correction delay time T5 elapses from the rise of the control signal US3. As a result, the control signal S3 given to the FET Q1 of the sustain driver 6 rises to the high level. Here, the correction delay time T5 is expressed by the following equation.

T5 = T1-T4 The correction time difference T5 corresponds to the period TA in FIG. The sustain driver 6 outputs the first signal in response to the control signals S1 and S3.
Sustain pulse Psu having a pulse of
Is output. As shown in FIG. 19D, the output detection circuit 161 of the output detector 16a outputs the detection signal DET3. Further, as shown in FIG. 19E, the output detection circuit 162 of the output detector 16a outputs the detection signal DET1.

The control timing comparator 183 generates the delay time detection signal DE1 shown in FIG. 19 (g) from the control signals US1 and US3, and the time difference detection signal shown in FIG. 19 (f) from the detection signals DET1 and DET3. DE6 is generated, and the delay time detection signal DE1 and the time difference detection signal DE6 are compared. The delay time detection signal DE1 becomes high level for the delay time T1. Further, the time difference detection signal DE6 becomes high level for the time difference T6. In this case, the control signal U
Since S1a rises to the high level at the time when the correction delay time T5 elapses from the rising of the control signal US3, that is, at the time before the correction time T4 by the correction time T4, the time difference T6 becomes equal to the delay time T1.

The control timing comparator 183 is shown in FIG.
As shown in (h), the correction time detection signal DE3 that rises to the high level for the time difference T3 between the delay time T1 and the time difference T6 is output. In this case, the delay time T1 and the time difference T
The time difference T3 from 6 is 0. Therefore, the correction time detection signal DE3 remains low level and does not change.

The correction time adder 182 holds the correction time detection signal DE3 output from the control timing comparator 183, adds the held correction time detection signal DE3 and the correction signal DE4, and outputs the addition result as a correction signal. DE4
Output as. Here, as shown in FIG. 19 (i), the correction signal DE4 before addition rises to the high level for the correction time T4. Therefore, the correction signal DE after addition
4 also rises to the high level for the correction time T4.

In this way, the rising edge of the detection signal DET3 output from the output detector 16a and the detection signal DE
The rising timing of the control signal US1a is controlled such that the time difference T6 from the rising of T1 is equal to the delay time T1 from the rising of the control signal US3 to the rising of the control signal US1. As a result, the FET
Temperature change of drivers 61 and 63 or FET driver 6
Even if the control signal transmission delay time varies due to differences in the production lots of 1,63, etc., the sustain pulse Psu
It is possible to keep the time difference between the first rising and the second rising of the above and to keep the time difference between the first discharging and the second discharging constant. Therefore, it becomes possible to drive the discharge cells at the timing when the efficiency is always maximized.

In the first embodiment, it is possible to completely eliminate the variation in the transmission delay time of the control signal due to the temperature change of the FET drivers 61 and 63 and the FETs Q1 and Q3 or the difference in the production lot. The control signal transmission delay time by the FET driver is as large as about 100 ns, whereas the control signal transmission delay time by the FET is as small as about 10 ns. Therefore, the control signal transmission due to the temperature change of the FETs Q1 and Q3 or the difference in production lot The variation in delay time is smaller than that of the FET drivers 61 and 63. Therefore, also in the second embodiment, the time difference between the first rising and the second rising of the sustain pulse Psu can be kept constant and the time difference between the first discharge and the second discharge can be kept constant. it can.

As described above, in the present embodiment, the first and second discharges are continuously generated at the rising of the sustain pulse to improve the luminous efficiency with respect to the input power and reduce the power consumption. You can Further, by controlling the time difference between the first rising edge and the second rising edge of the sustain pulse according to the lighting rate for each subfield, it is possible to drive the discharge cells with optimum light emission efficiency according to the lighting rate.

The delay time T1 of rising of the control signals US3 and US1 is set in accordance with the lighting rate of each subfield.
When the delay time is always set constant without controlling the delay time of rising of the control signals SC3 and SC1,
The lighting rate / delay time LUT 31 in the subfield lighting rate measuring device 8 of FIG. 1 and the subfield processing unit 3 of FIG.
The delay time determining unit 32 may not be provided.

In this embodiment, the PDP 7 corresponds to a display panel, the scan driver 5 and the sustain driver 6 correspond to driving means, the subfield processor 3 corresponds to control means and a control signal generating circuit, and output detection is performed. Bowl 1
6a corresponds to the detection means, and the drive circuit transmission delay time correctors 17 and 18 correspond to the correction means. Further, the control timing comparator 183 corresponds to the comparing means, and the correction time adder 1
Reference numeral 82 corresponds to the adding means, and the control timing corrector 181
Corresponds to the timing shift means.

The buffer circuit 60 corresponds to a rectangular wave signal generation circuit. Further, the FET driver 63 and the FE
The TQ3 constitutes a first drive circuit, and the FET driver 61
And the FET Q1 constitutes a second drive circuit. FET
The driver 63 corresponds to a first driver, the FET driver 61 corresponds to a second driver, the FET Q3 corresponds to a first transistor, and the FET Q1 corresponds to a second transistor.

The video signal-subfield correlator 2 corresponds to the converting means, the subfield lighting rate measuring device 8 corresponds to the lighting rate detecting means and the subfield lighting rate detecting means, and the lighting rate / delay time LUT31. The delay time determination unit 32 and the delay device 34 correspond to the reference value control means.

(Third Embodiment) FIG. 20 is a block diagram showing the structure of a plasma display device according to a third embodiment of the present invention.

The plasma display device of FIG. 20 has the output detectors 15 and 16 of the plasma display device of FIG.
Also, output detectors 15c and 16c and drive circuit transmission delay time correctors 17c and 18c are provided in place of the drive circuit transmission delay time correctors 17 and 18, and lighting ratio / reference value lookup tables (LUT) 8c and 8d are further provided. Prepare The configuration of the other parts of the plasma display device of FIG. 20 is similar to that of the plasma display device of FIG.

The subfield lighting rate measuring device 8 detects the lighting rate of the discharge cells 14 simultaneously driven on the PDP 7 from the image data SP for each subfield, and outputs the result as the subfield lighting rate signal SL. It outputs to the processor 3 and the lighting rate / reference value LUTs 8c and 8d. The configuration and operation of the subfield lighting rate measuring instrument 8 of FIG. 20 are the same as those of the subfield lighting rate measuring instrument 8 of FIG.

The lighting rate / reference value LUT 8c is a reference value T7 for each subfield according to the subfield lighting rate signal SL input from the subfield lighting rate measuring device 8.
Is given to the drive circuit transmission time corrector 17c.

The lighting rate / reference value LUT 8d is a reference value T7 for each subfield according to the subfield lighting rate signal SL input from the subfield lighting rate measuring device 8.
Is given to the drive circuit transmission time corrector 18c.

Specifically, the lighting rate / reference value LUTs 8c, 8
d stores a relationship between a previously calculated lighting rate and a reference value T7 corresponding to each lighting rate in a table format. For example, the lighting rate / reference values LUTs 8c and 8d store as the reference value T7 a value that is shorter than the delay time T1 stored in the lighting rate / delay time LUT 31 of FIG. 11 for each lighting rate.

Scan driver 5 is responsive to control signals CS2 and CS4 provided from subfield processor 3 and control signals CS1a and CS3 provided from drive circuit transmission delay time corrector 17c to periodically scan the sustain period. The sustain pulse Psc is applied to the plurality of scan electrodes 12 of the PDP 7. On the other hand, the sustain driver 6 controls the control signal US2 supplied from the subfield processor 3.
In response to the control signals US1a and US3 provided from US4 and the drive circuit transmission delay time corrector 18c, the sustain electrodes 13 of the PDP 7 are supplied to the plurality of sustain electrodes 13 in the sustain period.
180 ° with respect to the sustain pulse Psc of the scan electrode 12
The sustain pulses Psu having a phase shift are applied at the same time. As a result, the sustain discharge is performed in the corresponding discharge cell 14. Similar to the first embodiment, the sustain pulse Psc applied to the scan electrode 12 and the sustain electrode 13 are applied.
Each of the sustaining pulses Psu applied to the
And a two-peak waveform consisting of a first pulse (first peak) and a second pulse (second peak) to generate a second discharge.

The output detector 15c is the scan driver 5
To output a digital signal showing the waveform of the sustain pulse Psc given from. Drive circuit propagation delay time corrector 17c
Is the maximum point of the first pulse and the rising start point of the second pulse (the minimum point between the first pulse and the second pulse) in the waveform indicated by the digital signal output by the output detector 15c. Is calculated, the transmission delay time of the control signal CS1 given from the subfield processor 3 is corrected based on the time difference and the reference value T7 given from the lighting rate / reference value LUT 8c, and the corrected control signal C
It outputs S1a to the scan driver 5 and also outputs the control signal CS3 given from the subfield processor 3 to the scan driver 5.

The output detector 16c outputs a digital signal showing the waveform of the sustain pulse Psu supplied from the sustain driver 6. Drive circuit transmission delay time compensator 18c
Is the maximum point of the first pulse and the rising start point of the second pulse (the minimum point between the first pulse and the second pulse) in the waveform indicated by the digital signal output by the output detector 16c. Is calculated, the transmission delay time of the control signal US1 given from the subfield processor 3 is corrected based on the time difference and the reference value T7 given from the lighting rate / reference value LUT 8d, and the corrected control signal U
It outputs S1a to the sustain driver 6.

FIG. 21 is a circuit diagram mainly showing the structure of the output detector 16c shown in FIG. The output detector 16c shown in FIG. 21 includes resistors R1a to R3a, a bipolar transistor (hereinafter abbreviated as transistor) Q5a, and an analog-digital conversion circuit 60a.

The node N4 of the output detector 16c is connected to the node N1 of the sustain driver 6. In addition,
FIG. 21 shows the panel capacitance Cp corresponding to the total capacitance between the plurality of sustain electrodes 13 and the ground terminal.

The resistor R1a is connected between the node N4 and the node N5, and the resistor R2a is connected between the node N5 and the ground terminal. The base of the transistor Q5a is connected to the node N5, the collector is connected to the power supply terminal receiving the voltage + 3.3V, and the emitter is connected to the ground terminal via the resistor R3a. The input terminal of the analog-digital conversion circuit 60a is connected to the emitter of the transistor Q5a, and the output terminal of the analog-digital conversion circuit 60a is connected to the drive circuit transmission delay time corrector 18c. One power supply terminal of the analog-digital conversion circuit 60a is connected to the power supply terminal that receives the voltage + 3.3V, and the other power supply terminal is connected to the ground terminal.

FIG. 22 is a waveform diagram of each part of the output detector 16c shown in FIG. Next, the operation of the output detector 16c shown in FIG. 21 will be described with reference to the waveform chart shown in FIG.

The sustain pulse Psu output from the sustain driver 6 is applied to the node N4 of the output detector 16c (see FIG. 22A). Here, the sustain pulse P
The maximum voltage of su is 175V.

The sustain pulse Psu is voltage-divided by the resistors R1a and R2a, and the voltage-divided voltage is applied to the base of the transistor Q5a. As a result, a voltage DIV having a waveform similar to the sustain pulse Psu appears at the emitter of the transistor Q5a (see FIG. 22 (b)). The maximum voltage of this voltage DIV is 3.3V.

The analog-digital conversion circuit 60a performs analog-digital conversion on the voltage DIV in the range of 1V to 3V and outputs the digital signal A representing the waveform of FIG.
Output D.

FIG. 23 shows the sub-field processor 3, sustain driver 6, lighting rate / reference value LUT 8 of FIG.
FIG. 6 is a block diagram showing an output detector 16c, an output detector 16c, and a drive circuit transmission delay time corrector 18c.

As shown in FIG. 23, the drive circuit transmission delay time corrector 18c includes a control timing corrector 181, a correction time adder 182, a control timing comparator 183 and a waveform time difference detector 184. In FIG. 23, the FET drivers 61 and 6 included in the sustain driver 6 are included.
Only 3 and FETs Q1, Q3 are shown.

24 and 25 are timing charts for explaining the operation of the drive circuit transmission delay time compensator 18c of FIG. 23. FIG. 24 shows a state before correction and FIG. 25 shows a state after correction. Show. Here, referring to FIGS. 24 and 25, the drive circuit transmission delay time corrector 18c of FIG.
The operation of will be described. Note that FIG. 24 shows the first sustain pulse Psu, and FIG. 25 shows the second sustain pulse Psu continuing from FIG. 24.

First, the control signal US3 output from the subfield processor 3 rises to the high level, and FIG.
As shown in (a), the control signal US3 output from the control timing corrector 181 rises to a high level.
As a result, the control signal S3 given to the FET Q3 of the sustain driver 6 rises to the high level.

After the delay time T1 has elapsed from the rise of the control signal US3, the control signal US1 output from the subfield processor 3 rises to the high level, and FIG.
As shown in (c), the control signal US1a output from the control timing corrector 181 rises to a high level. As a result, the control signal S1 applied to the FET Q1 of the sustain driver 6 rises to the high level.

In the initial state, as shown in FIG. 24B, the correction signal DE output from the correction time adder 182 is output.
4a remains low level and does not change. That is, the correction time is 0.

As shown in FIG. 24D, the control signal S
In response to 1, S3, sustain driver 6 outputs sustain pulse Psu having the first pulse and the second pulse. Further, as shown in FIG. 24 (e), the output detector 16c (FIG. 21) outputs a digital signal AD representing a partial waveform of the sustain pulse Psu.

The waveform time difference detector 184 is supplied with the digital signal AD from the output detector 16c. As shown in FIG. 24 (f), the waveform time difference detector 184 detects the maximum point of the first pulse and the rising start point of the second pulse of the digital signal AD, and detects the maximum point of the first pulse from the maximum point of the first pulse. The time difference T8 from the rising start point of the second pulse is calculated and given to the control timing comparator 183. In this example, the waveform time difference detector 184 detects the rising start point from the minimum point between the first pulse and the second pulse from the timing of the rising start point from the maximum point of the first pulse of the digital signal AD. The time difference up to the timing is detected as a time difference T8 from the maximum point of the first pulse to the rising start point of the second pulse.

The control timing comparator 183 is provided with a reference value T7 which is stored in advance in a table format from the lighting rate / reference value LUT 8d and corresponds to the lighting rate, and a waveform time difference detector 184 provides a time difference T8. The control timing comparator 183 uses the reference value T7 as shown in FIG.
The reference signal DE1a shown in FIG.
8 to FIG. 24 (f), the time difference detection signal DE2a
Of the reference signal DE1a and the time difference detection signal D
Compare with E2a. The reference signal DE1a has a reference value T7.
High level only during the period. Time difference detection signal DE2a
Becomes high level only during the time difference T8.

The control timing comparator 183 is shown in FIG.
As shown in (h), the correction time detection signal DE3a that rises to the high level by the time difference T9 between the high level period of the time difference detection signal DE2a and the high level period of the reference signal DE1a is output. That is, T9 = T8-T7.

The correction time adder 182 outputs the correction time detection signal DE3a output from the control timing comparator 183.
Is held, and the held correction time detection signal DE3
a and a correction signal DE4a described later are added, and the addition result is output as a correction signal DE4a. Before the addition,
As shown in (i), the correction signal DE4a is at low level. Here, the high level period of the correction signal DE4a is referred to as a correction time T10. The initial value of the correction time T10 is 0.

As shown in FIG. 24 (j), after the addition,
The correction signal DE4a rises to the high level for the time difference T9. Thereby, the correction time T by the correction signal DE4a
10 is the time difference T9. That is, T10 = T9 + T
It is 10.

Next, the control signal US3 output from the subfield processor 3 rises to the high level, and FIG.
As shown in (a), the control signal US3 output from the control timing corrector 181 rises to a high level.
As a result, the control signal S3 given to the FET Q3 of the sustain driver 6 rises to the high level.

After that, the control signal US1 output from the subfield processor 3 rises to the high level. At this time, the correction signal D output from the correction time adder 182
As shown in FIG. 25B, E4a is the correction time T10.
Only high level. As a result, the control signal US1a output from the control timing corrector 181 is as shown in FIG.
As shown in (c), it rises to the high level when the correction delay time T11 elapses from the rise of the control signal US3. As a result, the control signal S3 given to the FET Q1 of the sustain driver 6 rises to the high level. Here, the correction delay time T11 is expressed by the following equation.

T11 = T1−T10 The correction delay time T11 corresponds to the period TA in FIG. As shown in FIG. 25D, the sustain driver 6 outputs the sustain pulse Psu having the first pulse and the second pulse in response to the control signals S1 and S3. As shown in FIG. 25 (e), the output detector 16c outputs a digital signal AD representing a part of the waveform of the sustain pulse Psu.

The waveform time difference detector 184 is supplied with the digital signal AD from the output detector 16c. As shown in FIG. 25F, the waveform time difference detector 184 calculates the time difference T8 from the maximum point of the first pulse of the digital signal AD to the rising start point of the second pulse, and the control timing comparator 183. Give to.

The control timing comparator 183 determines the lighting rate /
The reference value DE1a shown in FIG. 25 (g) is generated from the reference value LUT 8d in advance in a table format and corresponding to the lighting rate, and the waveform time difference detector 18 is generated.
The time difference detection signal DE2a is generated based on the time difference T8 given by 4, and the reference signal DE1a and the time difference detection signal DE2a are compared. The reference signal DE1a is the reference value T7.
High level only during the period. Also, the time difference detection signal D
E2a goes high only during the time difference T8. In this case, the control signal US1a rises to the high level at the time when the correction delay time T11 elapses from the rising of the control signal US3, that is, at the time before the correction time T10 before the time when the delay time T1 elapses. 1
The time difference T8 between the maximum point of the pulse and the second pulse rising start point is equal to the reference value T7.

The control timing comparator 183 is shown in FIG.
As shown in (h), the correction time detection signal D that rises to the high level by the time difference T9 between the reference value T7 and the time difference T8.
Outputs E3a. In this case, the reference value T7 and the time difference T8
And the time difference T9 from is 0. Therefore, the correction time detection signal DE3a remains low level and does not change.

The correction time adder 182 outputs the correction time detection signal DE3a output from the control timing comparator 183.
Is held, and the held correction time detection signal DE3
a and the correction signal DE4a are added, and the addition result is output as the correction signal DE4a. Here, as shown in FIG. 25 (i), the correction signal DE4a before addition is the correction time T10.
Only rise to a high level. Therefore, the correction signal DE4a after addition also rises to the high level for the correction time T10.

In this way, the time difference T8 between the maximum point of the first pulse and the rising start point of the second pulse of the digital signal AD output from the output detector 16c is determined by the lighting rate / reference value LUT8d. The rising timing of the control signal US1a is controlled so as to be equal to the preset reference value T7 for each time. Thereby, FE
Even if variations in the transmission delay time of the control signal occur due to temperature changes of the T drivers 61 and 63 and the FETs Q1 and Q3, or differences in production lots, the maximum point of the first pulse of the sustain pulse Psu and the second pulse of the sustain pulse Psu. The time difference from the rising start point can be kept constant, and the time difference between the first discharge and the second discharge can be kept constant. Therefore, it becomes possible to drive the discharge cells at a timing where the luminous efficiency is always maximized.

In particular, even if the slopes of the front edges of the first pulse and the second pulse of the sustain pulse Psu change, the timing of the maximum point and the minimum point in the digital signal AD representing a part of the waveform of the sustain pulse Psu is Since it does not change, the time difference between the first discharge and the second discharge can be accurately kept constant.

The configuration and operation of scan driver 5 of the plasma display device according to the third embodiment are similar to those of scan driver 5 of FIG. The configuration and operation of the output detector 15c are the same as the configuration and operation of the output detector 16c shown in FIG. Further, the configuration and operation of the drive circuit transmission delay time corrector 17c shown in FIG.
The configuration and operation of the drive circuit transmission delay time corrector 18c shown in FIG.

In this case, the time difference between the maximum point of the first pulse and the rising start point of the second pulse of the digital signal AD output from the output detector 15c is the lighting rate / reference value L.
The UT 8c controls the rising timing of the control signal CS1a so that it becomes equal to a preset reference value for each lighting rate. As a result, even if the transmission delay time of the control signal varies due to the temperature change of the FET driver or FET included in the sustain pulse generating unit 51 of FIG.
The time difference between the maximum point of the first pulse of c and the rising start point of the second pulse can be kept constant, and the time difference between the first discharge and the second discharge can be kept constant. Therefore,
It becomes possible to drive the discharge cell at a timing where the luminous efficiency is always maximized.

Also in the plasma display device according to the present embodiment, the discharge state is changed in accordance with the lighting rate of each subfield in the same manner as in FIGS. 12 to 14, so that the lighting rate of each subfield is adjusted. The sustain discharge can be performed in the optimum state. In particular, the sustain pulse P
Even if the slopes of the front edges of the first pulse and the second pulse of su change, the timings of the maximum point and the minimum point in the digital signal AD that represents a part of the waveform of the sustain pulse Psu do not change, and therefore, the precise The time difference between the first discharge and the second discharge can be kept constant.

As described above, in the present embodiment, the first and second discharges are continuously generated at the rising edge of the sustain pulse to improve the luminous efficiency with respect to the input power and reduce the power consumption. You can Further, by controlling the time difference between the maximum point of the first pulse of the sustain pulse and the rising start point of the second pulse in accordance with the lighting rate for each subfield, the discharge cell is optimally luminous efficiency according to the lighting rate. Can be driven.

The delay time T1 of rising of the control signals US3 and US1 is set according to the lighting rate of each subfield.
When the delay time is always set constant without controlling the delay time of rising of the control signals SC3 and SC1,
The lighting rate / delay time LUT3 in the subfield lighting rate measuring device 8 of FIG. 20 and the subfield processor 3 of FIG.
1 (see FIG. 11), the delay time determining unit 32 (see FIG. 11), and the lighting rate / reference value LUTs 8c and 8d in FIG.
Need not be provided.

In this embodiment, the PDP 7 corresponds to the display panel, the scan driver 5 and the sustain driver 6 correspond to the driving means, the subfield processor 3 corresponds to the control means and the control signal generating circuit, and the output detection is performed. Bowl 1
5c and 16c correspond to the detecting means, and the drive circuit transmission delay time correctors 17c and 18c correspond to the correcting means. Further, the control timing comparator 183 corresponds to the comparison means,
The correction time adder 182 corresponds to the adding means, the control timing corrector 181 corresponds to the timing shift means, and the waveform time difference detecting means 184 corresponds to the maximum / minimum detecting means.

The analog-digital conversion circuit 60 corresponds to the analog-digital conversion circuit. In addition, FET
The driver 63 and the FET Q3 form a first drive circuit, and the FET driver 61 and the FET Q1 form a second drive circuit. The FET driver 63 corresponds to the first driver, the FET driver 61 corresponds to the second driver, the FET Q3 corresponds to the first transistor, and the FET
Q1 corresponds to the second transistor.

The video signal-subfield correlator 2 corresponds to the converting means, the subfield lighting rate measuring device 8 corresponds to the lighting rate detecting means and the subfield lighting rate detecting means, and the lighting rate / reference value LUT8. Corresponds to the reference value control means and the storage means.

In the first, second and third embodiments, the time difference between the first discharge and the second discharge is controlled by controlling the rising timing of the control signals US1a and CS1a. However, the time difference between the first discharge and the second discharge may be controlled by controlling the rising timing of the control signals US3 and CS3.

[0239]

According to the present invention, the voltage of the drive waveform is reduced by the first discharge, and the voltage of the drive waveform is increased again after the first discharge is at least weakened. The second discharge can be continuously generated. As a result, since only the minimum electric power required for the discharge is applied in the first discharge, the saturation of the ultraviolet rays is relaxed by the current limitation from the moment the first discharge begins to weaken.
The luminous efficiency of the discharge is improved. As a result, the first discharge having a high luminous efficiency is performed in all the discharge cells to be lit, and the second discharge is further performed. Therefore, the luminous efficiency of all the discharge cells to be lit can be improved.

The time difference between the first pulse and the second pulse of the drive waveform generated by the drive means is detected,
At least one of the first and second timings is corrected based on the detected time difference. Therefore, even when the characteristics of the driving means vary due to the temperature change of the display panel or the driving means or the difference in the production lot, the time difference between the first and second discharges can be accurately controlled. As a result, it becomes possible to drive the discharge cells so as to emit light in a state of good light emission efficiency.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a plasma display device according to a first embodiment of the present invention.

FIG. 2 is a diagram for explaining an ADS method used in the plasma display device shown in FIG.

3 is a circuit diagram showing a configuration of a sustain driver shown in FIG.

FIG. 4 is a timing diagram showing an operation during a sustain period of the sustain driver shown in FIG.

5 is a circuit diagram mainly showing a configuration of an output detector shown in FIG.

6 is a waveform diagram of each part of the output detector shown in FIG.

7 is a block diagram showing a subfield processor, a sustain driver, an output detector and a drive circuit transmission delay time compensator of FIG.

8 is a timing diagram for explaining the operation of the drive circuit transmission delay time corrector shown in FIG.

9 is a timing chart for explaining the operation of the drive circuit transmission delay time corrector shown in FIG.

FIG. 10 is a block diagram showing the configuration of the scan driver shown in FIG.

FIG. 11 is a block diagram showing a configuration of a main part of the subfield processor shown in FIG.

FIG. 12 is a diagram showing a relationship between a luminous efficiency ratio and a time difference between detection signals.

FIG. 13 is a diagram showing an example of controlling the time difference of detection signals according to the lighting rate.

FIG. 14 is a diagram showing a relationship between a lighting rate and a current luminous efficiency ratio.

FIG. 15 is a circuit diagram showing a configuration of an output detector of the plasma display device according to the second embodiment of the present invention.

16 is a waveform diagram of each part of the output detector shown in FIG.

FIG. 17 is a circuit diagram showing configurations of a subfield processor, a sustain driver output detector, and a drive circuit transmission delay time corrector.

FIG. 18 is a timing chart for explaining the operation of the drive circuit transmission delay time corrector shown in FIG.

19 is a timing chart for explaining the operation of the drive circuit transmission delay time corrector shown in FIG.

FIG. 20 is a block diagram showing a configuration of a plasma display device according to a third embodiment of the present invention.

FIG. 21 is a circuit diagram mainly showing the configuration of an output detector shown in FIG.

22 is a waveform diagram of each part of the output detector shown in FIG.

23 is a block diagram showing the subfield processor, sustain driver, lighting rate / reference value LUT, output detector, and drive circuit transmission delay time corrector of FIG. 20.

24 is a timing chart for explaining the operation of the drive circuit transmission delay time corrector of FIG. 23.

25 is a timing diagram for explaining the operation of the drive circuit transmission delay time corrector of FIG. 23.

FIG. 26 is a diagram for explaining a method of driving a discharge cell of a conventional plasma display device.

FIG. 27 is a circuit diagram showing a configuration of a sustain driver of a conventional plasma display device.

28 is a timing chart showing an operation during a sustain period of the sustain driver shown in FIG.

[Description of Reference Signs] 1 A / D converter 2 Video signal-subfield correlator 3 Subfield processor 4 Data driver 5 Scan driver 6 Sustain driver 7 PDP 8 Subfield lighting rate measuring devices 8c, 8d Lighting rate / reference value LUT 11 Address electrode 12 Scan electrode 13 Sustain electrode 14 Discharge cell 15, 16, 16a, 15c, 16c Output detector 17, 18, 17c, 18c Drive circuit transmission delay time corrector 31 Lighting rate / delay time LUT 32 Delay time determination Part 33 Basic control signal generator 34,35 Delay device 61-64 FET driver 160 Differentiation circuit 161,162 Output detection circuit 181 Control timing corrector 182 Correction time adder 183 Control timing comparator 184 Waveform time difference detector C1 Recovery capacitor C2 Capacitor D1 D4 diode L recovery coil L1 coil Q1 to Q4 FET Q5 transistor R1~R4, R11, R12, R21, R22 resistor PH1, PH2 photocoupler

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) G09G 3/20 623 G09G 3/20 624N 624 641E 641 642C 642 642P H04N 5/66 101B H04N 5/66 101 G09G 3/28 K (72) Inventor Shigeo Kiko 1006 Kadoma, Kadoma, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. F term (reference) 5C058 AA11 BA01 BB04 5C080 AA05 BB05 DD04 DD20 EE29 HH04 HH05 JJ02 JJ03 JJ04 JJ05

Claims (15)

[Claims] 1. A display device for displaying an image by selectively discharging a plurality of discharge cells, wherein a display panel including the plurality of discharge cells and a first discharge cell selected in the display panel are provided. Driving means for generating a drive waveform having continuous first and second pulses to generate a second discharge after generating the second discharge, and generation of the first and second pulses of the drive waveform Control means for controlling the drive means at first and second timings for controlling the drive waveform, and the first drive waveform of the drive waveform generated by the drive means.
Detecting means for detecting a time difference between the pulse and the second pulse, and a correcting means for correcting at least one of the first and second timings by the control means based on the time difference detected by the detecting means. A display device comprising: 2. The correction means corrects at least one of the first and second timings by the control means so that the time difference detected by the detection means becomes equal to a predetermined reference value. The display device according to claim 1. 3. The compensating means compares the time difference detected by the detecting means with the reference value and outputs a difference between the time difference and the reference value as a correction time, and the first and the second means. The display device according to claim 2, further comprising a timing shift unit that shifts at least one of the second timings by the correction time output by the comparison unit. 4. The correction means holds the correction time previously detected by the comparison means,
4. The display device according to claim 3, further comprising adding means for adding the held correction time to the correction time currently detected by the comparison means and outputting the correction time as the current correction time to the timing shift means. 5. The detection means detects the time difference between the timing of the front edge of the first pulse and the timing of the front edge of the second pulse of the drive waveform generated by the drive means. The display device according to any one of claims 2 to 4, wherein the display device detects the time difference between the first pulse and the second pulse. 6. The detecting means includes a differentiating circuit for differentiating the drive waveform generated by the driving means, and a rectangular wave signal generating circuit for generating a rectangular wave signal from an output signal of the differentiating circuit. The display device according to claim 5, wherein the display device is a display device. 7. The control means includes a control signal generating circuit that generates a first control signal at the first timing and a second control signal at the second timing, and the driving means includes A first drive circuit for generating the first pulse in response to the first control signal generated by the control signal generation circuit; and a second control signal generated by the control signal generation circuit The display device according to any one of claims 2 to 4, further comprising: a second drive circuit that generates the second pulse in response to the second drive circuit. 8. The first driver circuit includes a first driver that outputs a first drive signal in response to the first control signal generated by the control signal generation circuit, and a first driver. A first transistor driven by a first drive signal output from the second drive circuit, the second drive circuit responsive to the second control signal generated by the control signal generation circuit, And a second transistor driven by the second drive signal output from the second driver, wherein the detection unit is output from the first driver. The time difference between the timing of the first drive signal and the timing of the second drive signal output from the second driver is detected as the time difference between the first pulse and the second pulse of the drive waveform. thing The display device according to claim 7, wherein: 9. The detecting means detects a minimum point between the first pulse and the second pulse from the timing of the maximum point of the first pulse of the drive waveform generated by the driving means. The display device according to claim 2, wherein a time difference until timing is detected as a time difference between the first pulse and the second pulse of the drive waveform. 10. The detection means includes an analog-digital conversion circuit that performs analog-digital conversion of the drive waveform generated by the drive means, and a maximum of the first pulse in an output signal of the analog-digital conversion circuit. 10. The display device according to claim 9, further comprising: a point and a maximum / minimum detecting means for determining a minimum point between the first pulse and the second pulse. 11. A lighting rate detection unit that detects a lighting rate of discharge cells that are simultaneously turned on among the plurality of discharge cells, and a reference that controls the reference value according to the lighting rate detected by the lighting rate detection unit. The display device according to claim 2, further comprising a value control unit. 12. The display device according to claim 11, wherein the reference value control unit includes a storage unit that stores a reference value according to a lighting rate in advance. 13. The image data of one field is converted into the image data of each subfield in order to divide one field into a plurality of subfields and discharge a selected discharge cell for each subfield to perform gradation display. The lighting rate detection means further includes a subfield lighting rate detection means for detecting a lighting rate for each subfield, and the reference value control means is detected by the subfield lighting rate detection means. 13. The display device according to claim 11, wherein the reference value is controlled according to the lighting rate. 14. The driving means increases the voltage of the drive waveform again after the voltage of the drive waveform is reduced by the first discharge and the first discharge is at least weakened. The display device according to claim 1, wherein a second discharge is generated following the discharge of 1. 15. A driving method of a display device for selectively discharging a plurality of discharge cells to display an image, wherein a second discharge is generated after a first discharge is generated in the selected discharge cells.
Generating a drive waveform having continuous first and second pulses by the drive means to generate the discharge of the drive waveform, and the drive means for generating the first and second pulses of the drive waveform. Controlling at first and second timings; and the first of the drive waveforms generated by the drive means.
And a step of detecting a time difference between the second pulse and the second pulse, and a step of correcting at least one of the first and second timings based on the detected time difference. Driving method.