JP2003249654A - Semiconductor device and its manufacturing method - Google Patents
Semiconductor device and its manufacturing methodInfo
- Publication number
- JP2003249654A JP2003249654A JP2002049357A JP2002049357A JP2003249654A JP 2003249654 A JP2003249654 A JP 2003249654A JP 2002049357 A JP2002049357 A JP 2002049357A JP 2002049357 A JP2002049357 A JP 2002049357A JP 2003249654 A JP2003249654 A JP 2003249654A
- Authority
- JP
- Japan
- Prior art keywords
- main surface
- conductive layer
- semiconductor device
- type
- electrode film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 111
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 66
- 239000012535 impurity Substances 0.000 claims description 8
- 238000003825 pressing Methods 0.000 claims description 6
- 230000000149 penetrating effect Effects 0.000 claims description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 43
- 229910052710 silicon Inorganic materials 0.000 abstract description 43
- 239000010703 silicon Substances 0.000 abstract description 43
- 239000013078 crystal Substances 0.000 abstract description 22
- 230000007547 defect Effects 0.000 abstract description 22
- 238000000034 method Methods 0.000 abstract description 17
- 238000007796 conventional method Methods 0.000 abstract description 4
- 239000010410 layer Substances 0.000 description 125
- 239000011229 interlayer Substances 0.000 description 20
- 229920001721 polyimide Polymers 0.000 description 8
- 238000002347 injection Methods 0.000 description 6
- 239000007924 injection Substances 0.000 description 6
- 238000009792 diffusion process Methods 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 238000007788 roughening Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
- H01L21/3043—Making grooves, e.g. cutting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
- H01L29/0661—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
Abstract
Description
【０００１】[0001]
【発明の属する分野】本発明は、半導体装置およびその
製造法に係り、特に電源回路等に利用されるＩＧＢＴの
構成を有する半導体装置およびその製造方法に関するも
のである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device having an IGBT structure used for a power supply circuit and the like and a method for manufacturing the same.
【従来の技術】ＩＧＢＴの構成を有する半導体装置は、
近年、バイポーラトランジスタとＭＯＳＦＥＴとの双方
の長所を併せ持つ半導体装置として、その利用が広がっ
ている。図７は、従来技術に係るＩＧＢＴの構成を有す
る半導体装置を示す断面図である。図７中、１１０は半
導体装置、１１１はシリコン基板、１１２はＮ−型ベー
ス層、１１３はＰウェル領域、１１４はＮ＋型エミッタ
領域、１１５はＮ＋型バッファ層、１１７はゲート電極
膜、１１８は層間絶縁膜、１１９はゲート絶縁膜、１２
０はエミッタ電極膜、１２１はコレクタ電極膜、１２５
はＰ＋型コレクタ層である。2. Description of the Related Art A semiconductor device having an IGBT structure is
In recent years, its use has spread as a semiconductor device having advantages of both a bipolar transistor and a MOSFET. FIG. 7 is a sectional view showing a semiconductor device having a configuration of an IGBT according to a conventional technique. In FIG. 7, 110 is a semiconductor device, 111 is a silicon substrate, 112 is an N − type base layer, 113 is a P well region, 114 is an N + type emitter region, 115 is an N + type buffer layer, 117 is a gate electrode film, 118 is an interlayer insulating film, 119 is a gate insulating film, 12
0 is an emitter electrode film, 121 is a collector electrode film, 125
Is a P + type collector layer.
【０００２】半導体装置１１０は、シリコン基板１１１
の内部に、Ｐ＋型コレクタ層１２５、Ｎ＋型バッファ層
１１５およびＮ−型ベース層１１２を積層形成してい
る。また、Ｎ−型ベース層１１２内にＰウェル層１１３
を形成し、さらにＰウェル層１１３内にＮ＋型エミッタ
領域１１４を形成している。また、シリコン基板１１１
の表面上には、Ｎ−型ベース層１１２、Ｐウェル層１１
３およびＮ＋型拡散領域１１４に跨るように層間絶縁膜
１１８とゲート電極膜１１７を積層して形成している。
さらに、層間絶縁膜１１８およびゲート電極膜１１７を
覆うようにゲート絶縁膜１１９を形成している。くわえ
て、ゲート絶縁膜１１９を含むシリコン基板１１１の表
面上には、これらを覆うエミッタ電極膜１２０を形成し
ている。また、シリコン基板１１１の裏面、すなわちＰ
＋型コレクタ層１２５の表面には、コレクタ電極膜１２
１を形成している。A semiconductor device 110 includes a silicon substrate 111.
A P + -type collector layer 125, an N + -type buffer layer 115, and an N − -type base layer 112 are laminated inside. In addition, the P well layer 113 is formed in the N − type base layer 112.
And an N + type emitter region 114 is formed in the P well layer 113. In addition, the silicon substrate 111
On the surface of the N − type base layer 112 and the P well layer 11
The interlayer insulating film 118 and the gate electrode film 117 are formed so as to extend over the 3 and N + type diffusion regions 114.
Further, a gate insulating film 119 is formed so as to cover the interlayer insulating film 118 and the gate electrode film 117. In addition, an emitter electrode film 120 that covers the gate insulating film 119 is formed on the surface of the silicon substrate 111. In addition, the back surface of the silicon substrate 111, that is, P
The collector electrode film 12 is formed on the surface of the + type collector layer 125.
1 is formed.
【０００３】以上の構成において、ゲート電極膜１１７
とエミッタ電極膜１２０との間に所定閾値以上の電圧を
印加すると、Ｐウェル層１１３の、層間絶縁膜１１８と
の境界付近の部分にＮ型の反転層が形成されてチャネル
となる。そして、コレクタ電極膜１２１からエミッタ電
極膜１２０へこのチャネルを通って電流が流れる。この
とき、正孔がＰ＋型コレクタ層１２５からＮ＋型バッフ
ァ層１１５を介してＮ −型ベース層１１２へ注入される
が、この正孔が伝導度変調作用を引き起こし、コレクタ
電極膜１２１とエミッタ電極膜１２０との間のオン電圧
が低下する。In the above structure, the gate electrode film 117
Between the emitter electrode film 120 and the emitter electrode film 120
When applied, the P-well layer 113 and the interlayer insulating film 118
N-type inversion layer is formed near the boundary of the channel
Becomes Then, from the collector electrode film 121 to the emitter electrode.
Current flows through this channel to the polar membrane 120. this
When the hole is P+Type collector layer 125 to N+Type buff
Through the layer 115 −Injected into the mold base layer 112
However, this hole causes conductivity modulation effect and
ON voltage between the electrode film 121 and the emitter electrode film 120
Is reduced.
【０００４】また、上述の半導体装置１１０は、ゲート
電極膜１１７とエミッタ電極膜１２０との間の電圧を零
または負電圧にすることによってターンオフする。とこ
ろが、ゲート電極膜１１７とエミッタ電極膜１２０との
間の電圧を零または負電圧にしてからも、正孔の注入が
一定程度の時間継続する。したがって、このような正孔
の注入がほとんどないＭＯＳＦＥＴの構成を有する半導
体装置と比較すると、ターンオフに要する時間が長くな
るので、ターンオフ時のスイッチング特性が劣っている
と言える。The semiconductor device 110 described above is turned off by setting the voltage between the gate electrode film 117 and the emitter electrode film 120 to zero or a negative voltage. However, even after the voltage between the gate electrode film 117 and the emitter electrode film 120 is set to zero or a negative voltage, the injection of holes continues for a certain time. Therefore, as compared with a semiconductor device having a MOSFET structure in which almost no holes are injected, the time required for turn-off is longer, and it can be said that the switching characteristics at turn-off are inferior.
【０００５】そこで、ＩＧＢＴの構成を有する半導体装
置のスイッチング特性を改善する対策として、様々な改
良構造が提案されている。図８は、ＩＧＢＴの構成を有
する半導体装置のスイッチング特性を改善した第１の従
来例を示す断面図である。図８中、２１０は半導体装
置、２１１はシリコン基板、２１２はＮ−型ベース層、
２１３はＰウェル領域、２１４はＮ＋型エミッタ領域、
２１５はＮ＋型バッファ層、２１７はゲート電極膜、２
１８は層間絶縁膜、２１９はゲート絶縁膜、２２０はエ
ミッタ電極膜、２２１はコレクタ電極膜、２２５はＰ＋
型コレクタ層、２２６はＮ＋型ドレイン領域である。ま
た、図９は、ＩＧＢＴの構成を有する半導体装置のスイ
ッチング特性を改善した第２の従来例を示す断面図であ
る。図９中、３１０は半導体装置、３１１はシリコン基
板、３１２はＮ−型ベース層、３１３はＰウェル領域、
３１４はＮ＋型エミッタ領域、３１５はＮ＋型バッファ
層、３１７はゲート電極膜、３１８は層間絶縁膜、３１
９はゲート絶縁膜、３２０はエミッタ電極膜、３２１は
コレクタ電極膜、３２５はＰ＋型コレクタ層、３２７は
穴部である。さらに、図１０は、ＩＧＢＴの構成を有す
る半導体装置のスイッチング特性を改善した第３の従来
例を示す断面図である。図１０中、４１０は半導体装
置、４１１はシリコン基板、４１２はＮ−型ベース層、
４１３はＰウェル領域、４１４はＮ＋型エミッタ領域、
４１５はＮ＋型バッファ層、４１７はゲート電極膜、４
１８は層間絶縁膜、４１９はゲート絶縁膜、４２０はエ
ミッタ電極膜、４２１はコレクタ電極膜、４２４は結晶
欠陥、４２５はＰ＋型コレクタ層である。Therefore, various improved structures have been proposed as measures for improving the switching characteristics of a semiconductor device having an IGBT structure. FIG. 8 is a sectional view showing a first conventional example in which the switching characteristics of a semiconductor device having an IGBT structure are improved. In FIG. 8, 210 is a semiconductor device, 211 is a silicon substrate, 212 is an N − type base layer,
213 is a P well region, 214 is an N + type emitter region,
215 is an N + type buffer layer, 217 is a gate electrode film, 2
18 is an interlayer insulating film, 219 is a gate insulating film, 220 is an emitter electrode film, 221 is a collector electrode film, 225 is P +
The type collector layer 226 is an N + type drain region. Further, FIG. 9 is a cross-sectional view showing a second conventional example in which the switching characteristics of a semiconductor device having an IGBT structure are improved. In FIG. 9, 310 is a semiconductor device, 311 is a silicon substrate, 312 is an N − type base layer, 313 is a P well region,
314 is an N + type emitter region, 315 is an N + type buffer layer, 317 is a gate electrode film, 318 is an interlayer insulating film, 31
Reference numeral 9 is a gate insulating film, 320 is an emitter electrode film, 321 is a collector electrode film, 325 is a P + -type collector layer, and 327 is a hole. Furthermore, FIG. 10 is a sectional view showing a third conventional example in which the switching characteristics of a semiconductor device having an IGBT structure are improved. In FIG. 10, 410 is a semiconductor device, 411 is a silicon substrate, 412 is an N − -type base layer,
413 is a P well region, 414 is an N + type emitter region,
415 is an N + type buffer layer, 417 is a gate electrode film, 4
18 is an interlayer insulating film, 419 is a gate insulating film, 420 is an emitter electrode film, 421 is a collector electrode film, 424 is a crystal defect, and 425 is a P + -type collector layer.
【０００６】図８に示した半導体装置２１０は、Ｐ＋型
コレクタ層２２５とともに、Ｎ＋型ドレイン領域２２６
を形成したものであり、ＩＧＢＴの構成とＭＯＳＦＥＴ
の構成とを併せ持っている。したがって、半導体装置２
１０は、ＭＯＳＦＥＴの構成とした部分において正孔の
注入を抑さえることができるので、図７の半導体装置１
１０よりもスイッチング特性が改善される。The semiconductor device 210 shown in FIG. 8 includes a P + type collector layer 225 and an N + type drain region 226.
And the structure of the IGBT and the MOSFET.
It also has the configuration of. Therefore, the semiconductor device 2
10 can suppress the injection of holes in the portion configured as the MOSFET, so that the semiconductor device 1 shown in FIG.
The switching characteristics are improved as compared with 10.
【０００７】また、図９に示した半導体装置３１０は、
Ｐ＋型コレクタ層３２５およびＮ−型ベース層３１２を
貫く穴部３２７をエッチングで形成するとともに、穴部
３２７の内部にもコレクタ電極膜３２１を形成してＭＯ
ＳＦＥＴの構成を設けたものである。したがって、半導
体装置２１０と同様に、ＭＯＳＦＥＴの構成とした部分
において正孔の注入を抑さえることができる。Further, the semiconductor device 310 shown in FIG.
A hole 327 that penetrates the P + -type collector layer 325 and the N − -type base layer 312 is formed by etching, and a collector electrode film 321 is also formed inside the hole 327 to form a MO film.
The configuration of the SFET is provided. Therefore, like the semiconductor device 210, the injection of holes can be suppressed in the portion having the MOSFET structure.
【０００８】また、図１０に示した半導体装置４１０
は、Ｎ−型ベース層４１２とＮ＋型バッファ層４１５と
の境界面付近に、Ｈ＋＋イオンを注入するなどの方法に
よって結晶欠陥４２４を形成したものである。当該部位
に結晶欠陥４２４を導入することにより、結晶欠陥４２
４がシリコンのバンドギャップ中に深い不純物凖位を形
成するので、結晶欠陥４２４において正孔を捕捉するこ
とが可能になる。したがって、結晶欠陥４２４を形成す
る設けることによって、半導体装置４１０のスイッチン
グ特性が改善される。Further, the semiconductor device 410 shown in FIG.
Is a crystal defect 424 formed near the boundary between the N − type base layer 412 and the N + type buffer layer 415 by a method such as implanting H ++ ions. By introducing the crystal defect 424 into the part, the crystal defect 42
Since 4 forms deep impurity lattices in the band gap of silicon, it becomes possible to trap holes in the crystal defects 424. Therefore, the switching characteristics of the semiconductor device 410 are improved by providing the crystal defects 424.
【０００９】さらに、図８ないし図１０に示した半導体
装置の構造を複数組み合わせて利用すれば、スイッチン
グ特性をさらに改善することが可能になる。しかしなが
ら、これらの構造のいずれを製造する場合においても、
図７に示した半導体装置の構造よりも工程数が増加する
ので、製造コストを増加させる要因となる。したがっ
て、図８ないし図１０に示した半導体装置の構造を複数
組み合わせて利用することは、経済的に見て困難性が高
いと言える。Further, by using a plurality of structures of the semiconductor device shown in FIGS. 8 to 10 in combination, the switching characteristics can be further improved. However, when producing either of these structures,
Since the number of steps is larger than that of the structure of the semiconductor device shown in FIG. 7, it becomes a factor of increasing the manufacturing cost. Therefore, it can be said that it is economically difficult to use a plurality of structures of the semiconductor devices shown in FIGS. 8 to 10 in combination.
【００１０】[0010]
【発明が解決しようとする課題】本発明は、上述の課題
を解決するために、簡便な構造及び方法によってターン
オフ時のスイッチング特性を改善したＩＧＢＴの構成を
有する半導体装置およびその製造方法を提供することを
目的とするものである。SUMMARY OF THE INVENTION In order to solve the above problems, the present invention provides a semiconductor device having an IGBT structure in which switching characteristics at turn-off are improved by a simple structure and method, and a manufacturing method thereof. That is the purpose.
【課題を解決するための手段】上記課題を解決するため
の手段として、本発明は、半導体基板の第１の主面上に
ゲート電極およびエミッタ電極を形成し、前記半導体基
板の第２の主面上にコレクタ電極を形成してなる半導体
装置において、前記半導体基板に、前記第２の主面に露
出するように形成してなる第１導電型の第１の導電層
と、該第１の導電層に積層させて形成してなる第１導電
型の第２の導電層を設け、前記第２の主面に前記第１の
導電層を貫通する凹面部を形成して第２の導電層を露出
させるとともに、前記凹面部を含む前記第２の主面を粗
面化し、前記コレクタ電極を前記第１の導電層と前記第
２の導電層とにショットキー接続させてなることを特徴
とするものとした。As a means for solving the above-mentioned problems, the present invention forms a gate electrode and an emitter electrode on a first main surface of a semiconductor substrate, and a second main surface of the semiconductor substrate. In a semiconductor device having a collector electrode formed on a surface thereof, a first conductive type first conductive layer formed on the semiconductor substrate so as to be exposed at the second main surface, and the first conductive layer. A second conductive layer of the first conductivity type formed by stacking on the conductive layer is provided, and a concave portion penetrating the first conductive layer is formed on the second main surface to form a second conductive layer. Is exposed, and the second main surface including the concave portion is roughened, and the collector electrode is Schottky-connected to the first conductive layer and the second conductive layer. I decided to do it.
【００１１】したがって、本発明に係る半導体装置は、
第２の主面上に形成したコレクタ電極を第１の導電層と
第２の導電層との双方に直接接続したので、エミッタ電
極とコレクタ電極との間に、第１の導電層を含む第１の
半導体装置の構成と、第１の導電層を含まない第２の半
導体装置の構成とを同時に実現することができる。さら
に、凹面部を含む半導体基板の第２の主面を粗面化した
ので、第１の導電層、および凹面部内に露出した第２の
導電層に結晶欠陥を持つ部分を形成でき、第２の導電層
への正孔の注入を抑えることができる。くわえて、コレ
クタ電極を第１の導電層と第２の導電層とにショットキ
ー接続させたので、半導体基板の内部に形成するＰＮ接
続を１つ減らす、すなわち半導体基板の内部に形成する
導電層を１つ減らすことができる。Therefore, the semiconductor device according to the present invention is
Since the collector electrode formed on the second main surface is directly connected to both the first conductive layer and the second conductive layer, the first conductive layer including the first conductive layer is provided between the emitter electrode and the collector electrode. It is possible to simultaneously realize the configuration of the first semiconductor device and the configuration of the second semiconductor device that does not include the first conductive layer. Further, since the second main surface of the semiconductor substrate including the concave portion is roughened, it is possible to form a portion having crystal defects in the first conductive layer and the second conductive layer exposed in the concave portion. Injecting holes into the conductive layer can be suppressed. In addition, since the collector electrode is Schottky-connected to the first conductive layer and the second conductive layer, the PN connection formed inside the semiconductor substrate is reduced by one, that is, the conductive layer formed inside the semiconductor substrate. Can be reduced by one.
【００１２】また、本発明は、半導体基板の第１の主面
上にゲート電極およびエミッタ電極を形成し、前記半導
体基板の第２の主面上にコレクタ電極を形成してなる半
導体装置において、前記半導体基板に、前記第２の主面
に露出するように形成してなる第２導電型の第１の導電
層と、該第１の導電層に積層させて形成してなる第１導
電型の第２の導電層を設け、前記第２の主面に前記第１
の導電層を貫通する凹面部を形成して第２の導電層を露
出させるとともに、前記凹面部を含む前記第２の主面を
粗面化し、前記コレクタ電極を前記第１の導電層と前記
第２の導電層とにオーミック接続させてなることを特徴
とするものとした。Further, the present invention provides a semiconductor device comprising a gate electrode and an emitter electrode formed on a first main surface of a semiconductor substrate and a collector electrode formed on a second main surface of the semiconductor substrate, A second conductive type first conductive layer formed on the semiconductor substrate so as to be exposed on the second main surface, and a first conductive type formed by being laminated on the first conductive layer. Second conductive layer is provided on the second main surface of the first conductive layer.
Forming a concave surface portion penetrating the conductive layer to expose the second conductive layer, roughening the second main surface including the concave surface portion, and setting the collector electrode to the first conductive layer and the first conductive layer. It is characterized in that it is ohmic-connected to the second conductive layer.
【００１３】したがって、本発明に係る半導体装置は、
第２の主面上に形成したコレクタ電極を第１の導電層と
第２の導電層との双方に直接接続したので、エミッタ電
極とコレクタ電極との間に、第１の導電層を含む第１の
半導体装置の構成と、第１の導電層を含まない第２の半
導体装置の構成とを同時に実現することができる。さら
に、凹面部を含む半導体基板の第２の主面を粗面化した
ので、第１の導電層、および凹面部内に露出した第２の
導電層に結晶欠陥を持つ部分を形成でき、第２の導電層
への正孔の注入を抑えることができる。Therefore, the semiconductor device according to the present invention is
Since the collector electrode formed on the second main surface is directly connected to both the first conductive layer and the second conductive layer, the first conductive layer including the first conductive layer is provided between the emitter electrode and the collector electrode. It is possible to simultaneously realize the configuration of the first semiconductor device and the configuration of the second semiconductor device that does not include the first conductive layer. Further, since the second main surface of the semiconductor substrate including the concave portion is roughened, it is possible to form a portion having crystal defects in the first conductive layer and the second conductive layer exposed in the concave portion. Injecting holes into the conductive layer can be suppressed.
【００１４】さらに、本発明は、半導体装置の製造方法
において、半導体基板の第１の主面上にゲート電極およ
びエミッタ電極を形成する工程と、前記半導体基板の第
２の主面から不純物を注入して加熱拡散することによ
り、該第２の主面に露出する第１の導電層および該第１
の導電層に積層される第２の導電層を形成する工程と、
前記半導体基板を前記第１の主面側から押圧しつつ、前
記半導体基板を前記第２の主面側から研削することによ
り、前記第２の主面全体を研削しつつ、前記第２の主面
の、前記ゲート電極と前記エミッタ電極との双方または
いずれか一方に対応する部位に、前記第１の導電層を貫
通して前記第２の導電層を露出させる凹面部を形成する
工程と、前記凹面部を含む前記第２の主面上にコレクタ
電極を形成する工程を有することを特徴とするものとし
た。Further, according to the present invention, in a method of manufacturing a semiconductor device, a step of forming a gate electrode and an emitter electrode on a first main surface of a semiconductor substrate, and an impurity implantation from the second main surface of the semiconductor substrate. And heat diffusion to expose the first conductive layer and the first conductive layer exposed on the second main surface.
Forming a second conductive layer laminated on the conductive layer of
By pressing the semiconductor substrate from the first main surface side and grinding the semiconductor substrate from the second main surface side, the second main surface is ground while the second main surface is ground as a whole. Forming a concave surface portion that penetrates the first conductive layer and exposes the second conductive layer at a portion of the surface corresponding to both or one of the gate electrode and the emitter electrode; The method further comprises the step of forming a collector electrode on the second main surface including the concave surface portion.
【００１５】したがって、本発明に係る半導体装置は、
半導体基板を第２の主面側から研削する工程において、
凹面部の形成と、結晶欠陥の形成とを同時に行うことが
でき、従来技術に係る正孔の注入抑制構造を採用した場
合よりも、工程数を減らすことができる。Therefore, the semiconductor device according to the present invention is
In the step of grinding the semiconductor substrate from the second main surface side,
The formation of the concave portion and the formation of the crystal defect can be performed at the same time, and the number of steps can be reduced as compared with the case of adopting the hole injection suppressing structure according to the related art.
【００１６】[0016]
【発明の実施の形態】以下に、本発明の第１の実施の形
態に係る半導体装置を図面に基づいて詳細に説明する。
図１は、本発明の第１の実施の形態に係る半導体装置を
示す断面図である。図１中、１０は半導体装置、１１は
シリコン基板、１２はＮ−型ベース層、１３はＰウェル
領域、１４はＮ＋型エミッタ領域、１５はＮ＋型バッフ
ァ層、１７はゲート電極膜、１８は層間絶縁膜、１９は
ゲート絶縁膜、２０はエミッタ電極膜、２１はコレクタ
電極膜、２２ａ，２２ｂは凹面部、２３は粗面、２４は
結晶欠陥である。BEST MODE FOR CARRYING OUT THE INVENTION A semiconductor device according to a first embodiment of the present invention will be described below in detail with reference to the drawings.
FIG. 1 is a sectional view showing a semiconductor device according to the first embodiment of the present invention. In FIG. 1, 10 is a semiconductor device, 11 is a silicon substrate, 12 is an N − type base layer, 13 is a P well region, 14 is an N + type emitter region, 15 is an N + type buffer layer, 17 is a gate electrode film, Reference numeral 18 is an interlayer insulating film, 19 is a gate insulating film, 20 is an emitter electrode film, 21 is a collector electrode film, 22a and 22b are concave surfaces, 23 is a rough surface, and 24 is a crystal defect.
【００１７】半導体装置１０は、シリコン基板１１の内
部に、Ｎ−型ベース層１２およびＮ ＋型バッファ層１５
を積層形成している。また、Ｎ−型ベース層１２内にＰ
ウェル層１３を形成している。さらに、Ｐウェル層１３
内にＮ＋型エミッタ領域１４を２つ形成している。な
お、Ｐウェル層１３は、Ｎ−型であるシリコン基板１１
の一方の面からＰ型の不純物を注入し、これを拡散させ
ることによって形成される。さらに、Ｎ＋型エミッタ領
域１４は、Ｐウェル層１３を形成した側の面（以下、第
１の主面とする）において、Ｐウェル層１３が露出した
領域内にＮ型の不純物を注入し、これを拡散させること
によって形成される。なお、Ｐウェル層１３とＮ＋型エ
ミッタ領域１４は、１つのセルを形成しており、このよ
うなセルが半導体装置１０に多数形成されている。セル
の形状および配置については、一般的に、セルをストラ
イプ状に細長く形成して、これらのセルを平行に配置す
るものと、各セルを矩形状に形成して、これらのセルを
格子状に配置するものとのいずれかを採用することが多
い。この発明の実施の形態においては、いずれであって
も良いし、他のセルの形状および配置を採用しても良
い。The semiconductor device 10 includes a silicon substrate 11
Part, N−Mold base layer 12 and N +Type buffer layer 15
Are laminated. Also, N−P in the mold base layer 12
The well layer 13 is formed. Further, the P well layer 13
Within N+Two mold emitter regions 14 are formed. Na
The P well layer 13 is N−Mold silicon substrate 11
P-type impurities are injected from one surface and diffused
It is formed by Furthermore, N+Type emitter area
The region 14 is a surface on the side where the P well layer 13 is formed (hereinafter, referred to as the first
1), the P well layer 13 was exposed.
Injecting N-type impurities into the region and diffusing it
Formed by. The P well layer 13 and the N+Type d
The miter region 14 forms one cell,
Many such cells are formed in the semiconductor device 10. cell
For the shape and placement of
Elongate and place these cells in parallel
And each cell in a rectangular shape,
It is often the case that one of those arranged in a grid is adopted.
Yes. In any of the embodiments of the present invention,
Or other cell shapes and arrangements may be used.
Yes.
【００１８】また、Ｎ＋型バッファ層１５は、シリコン
基板１１の、第１の主面と反対側の面（以下、第２の主
面とする）からＮ型の不純物を注入し、これを拡散させ
て形成する。なお、Ｎ＋型バッファ層１５の厚さは、こ
の実施の形態においては１０μｍ前後である。さらに、
シリコン基板１１の、これらの不純物拡散層および領域
を形成しない残余の部分は、Ｎ−型ベース層１２とな
る。The N + -type buffer layer 15 is formed by implanting N-type impurities from the surface of the silicon substrate 11 opposite to the first main surface (hereinafter referred to as the second main surface), and implanting this. It is formed by diffusion. The thickness of the N + type buffer layer 15 is about 10 μm in this embodiment. further,
The remaining portion of the silicon substrate 11 where these impurity diffusion layers and regions are not formed becomes the N − type base layer 12.
【００１９】また、シリコン基板１１の第１の主面上に
は、ゲート電極膜１７、層間絶縁膜１８、ゲート絶縁膜
１９およびエミッタ電極膜２０を形成している。層間絶
縁膜１８は、Ｎ−型ベース層１２、Ｐウェル層１３およ
びＮ＋型拡散領域１４に跨るように形成されている。さ
らに、層間絶縁膜１８の上には、ゲート電極膜１７を形
成している。また、ゲート絶縁膜１９は、ゲート電極膜
１７および層間絶縁膜１８を覆うように形成されてい
る。さらに、エミッタ電極膜２０は、ゲート絶縁膜１９
を含む第１の主面全体を覆うように形成されている。A gate electrode film 17, an interlayer insulating film 18, a gate insulating film 19 and an emitter electrode film 20 are formed on the first main surface of the silicon substrate 11. The interlayer insulating film 18 is formed so as to extend over the N − type base layer 12, the P well layer 13, and the N + type diffusion region 14. Further, the gate electrode film 17 is formed on the interlayer insulating film 18. The gate insulating film 19 is formed so as to cover the gate electrode film 17 and the interlayer insulating film 18. Further, the emitter electrode film 20 is the gate insulating film 19
Is formed so as to cover the entire first main surface including.
【００２０】また、シリコン基板１１の第２の主面に
は、コレクタ電極膜２１、凹面部２２ａ，２２ｂおよび
結晶欠陥２４を形成している。なお、凹面部２２ａ，２
２ｂは、Ｎ＋型バッファ層１５を貫通して、Ｎ−型ベー
ス層１２が凹面部２２ａ，２２ｂ内に露出する深さ、す
なわち１０μｍ以上の深さに形成されている。また、粗
面２３は、凹面部２２ａ，２２ｂの内面を含むシリコン
基板１１の第２の主面全体に形成される。さらに、結晶
欠陥２４は、凹面部２２ａ，２２ｂの内面を含むシリコ
ン基板１１の第２の主面下に形成される。なお、凹面部
２２ａ，２２ｂと結晶欠陥２４は、後述するように、同
じ工程によって形成される。くわえて、コレクタ電極膜
２１は、凹面部２２ａ，２２ｂの内面を含むシリコン基
板１１の第２の主面全体を覆うように形成されている。
また、コレクタ電極膜２１と、Ｎ＋型バッファ層１５お
よびＮ−型ベース層１２とは、ショットキー接続されて
いる。On the second main surface of the silicon substrate 11, a collector electrode film 21, concave surface portions 22a and 22b, and crystal defects 24 are formed. The concave surface portions 22a, 2
2b is formed so as to penetrate the N + type buffer layer 15 and to expose the N − type base layer 12 in the concave portions 22a and 22b, that is, a depth of 10 μm or more. The rough surface 23 is formed on the entire second main surface of the silicon substrate 11 including the inner surfaces of the concave portions 22a and 22b. Furthermore, the crystal defects 24 are formed below the second main surface of the silicon substrate 11 including the inner surfaces of the concave portions 22a and 22b. The concave portions 22a and 22b and the crystal defect 24 are formed by the same process as described later. In addition, the collector electrode film 21 is formed so as to cover the entire second main surface of the silicon substrate 11 including the inner surfaces of the concave surface portions 22a and 22b.
Further, the collector electrode film 21 and the N + type buffer layer 15 and the N − type base layer 12 are Schottky connected.
【００２１】さらに、半導体装置１０の動作について説
明する。ゲート電極膜１７とエミッタ電極膜２０との間
に所定閾値以上の電圧を印加すると、Ｐウェル層１３
の、層間絶縁膜１８との境界付近の部分にＮ型の反転層
が形成されてチャネルとなる。そして、コレクタ電極膜
２１からエミッタ電極膜２０へこのチャネルを通って電
流が流れる。このとき、正孔がコレクタ電極膜２１から
Ｎ＋型バッファ層１５およびＮ−型ベース層１２へ注入
される。しかしながら、コレクタ電極膜２１とＮ ＋型バ
ッファ層１５およびＮ−型ベース層１２とはショットキ
ー接続されているので、図７に示した半導体装置１１０
と比較した場合、注入される正孔の量は、非常に少なく
なる。Further, the operation of the semiconductor device 10 will be explained.
Reveal Between the gate electrode film 17 and the emitter electrode film 20
When a voltage higher than a predetermined threshold is applied to the P-well layer 13
Of the N-type inversion layer near the boundary with the interlayer insulating film 18.
Are formed to become channels. And collector electrode film
21 to the emitter electrode film 20 through this channel.
The flow flows. At this time, holes are emitted from the collector electrode film 21.
N+Type buffer layer 15 and N−Injection into the mold base layer 12
To be done. However, the collector electrode film 21 and N +Type
Buffer layer 15 and N−What is the mold base layer 12?
Are connected, the semiconductor device 110 shown in FIG.
The amount of holes injected is very small when compared to
Become.
【００２２】また、半導体装置１０は、凹面部２２ａ，
２２ｂを形成し、コレクタ電極膜２１とＮ＋型バッファ
層１５およびＮ−型ベース層１２とを接続したので、Ｉ
ＧＢＴの構成とＭＯＳＦＥＴの構成との双方を併せ持っ
ている。したがって、ＭＯＳＦＥＴの構成とした部分に
おいて正孔の注入を抑さえることができる。さらに、シ
リコン基板１１の第２の主面下に形成された結晶欠陥２
４において注入された正孔を捕捉することが可能であ
る。したがって、本発明の第１の実施の形態に係る半導
体装置１０は、従来技術に係る半導体装置よりも、オフ
時のスイッチング特性を改善することが容易にできる。Further, the semiconductor device 10 has a concave surface portion 22a,
22b is formed and the collector electrode film 21 and the N + type buffer layer 15 and the N − type base layer 12 are connected to each other.
It has both a GBT structure and a MOSFET structure. Therefore, the injection of holes can be suppressed in the portion configured as the MOSFET. Further, crystal defects 2 formed below the second main surface of the silicon substrate 11
It is possible to trap the holes injected in 4. Therefore, the semiconductor device 10 according to the first embodiment of the present invention can easily improve the switching characteristics at the time of OFF, as compared with the semiconductor device according to the related art.
【００２３】次に、本発明の第１の実施の形態に係る半
導体装置の製造方法を図面に基づいて詳細に説明する。
図３〜図５は、本発明の第１の実施の形態に係る半導体
装置の製造方法を示す断面図（ａ）〜（ｃ）である。図
３〜図５中、３１は上定盤、３２は下定盤である。その
他の符号は、図１において用いた符号と同じものを示す
ものである。なお、図３〜図５は、ウェハプロセスの一
部の工程を示すものであり、シリコン基板１１として示
したものは、シリコンウェハの断面の一部を表したもの
である。Next, a method of manufacturing the semiconductor device according to the first embodiment of the present invention will be described in detail with reference to the drawings.
3 to 5 are cross-sectional views (a) to (c) showing a method for manufacturing a semiconductor device according to the first embodiment of the present invention. 3 to 5, 31 is an upper surface plate and 32 is a lower surface plate. Other reference numerals are the same as those used in FIG. 3 to 5 show some steps of the wafer process, and what is shown as the silicon substrate 11 shows a part of the cross section of the silicon wafer.
【００２４】まず、図３に示すように、シリコン基板１
１の第２の主面側を研削する前に、第１の主面上に、ゲ
ート電極膜１７、層間絶縁膜１８、ゲート絶縁膜１９、
エミッタ電極膜２０、ゲート電極膜１７、層間絶縁膜１
８、ゲート絶縁膜１９およびエミッタ電極膜２０を形成
しておく。なお、これらの製造工程は、特定の方法に限
定されるものではなく、周知の製造方法のいずれを採用
しても良い。First, as shown in FIG. 3, a silicon substrate 1
Before grinding the second main surface side of No. 1, on the first main surface, the gate electrode film 17, the interlayer insulating film 18, the gate insulating film 19,
Emitter electrode film 20, gate electrode film 17, interlayer insulating film 1
8, the gate insulating film 19 and the emitter electrode film 20 are formed in advance. Note that these manufacturing steps are not limited to particular methods, and any known manufacturing method may be adopted.
【００２５】次に、図４に示すように、上定盤３１によ
ってシリコン基板１１の第１の主面側を矢印Ａに示すよ
うに押圧しながら、下定盤３２によってシリコン基板１
１の第２の主面側を研削する。このとき、上定盤３１の
押圧力は、従来技術に係る製造方法を用いる場合よりも
強く、かつ、シリコン基板１１にクラック等が生じて破
損しない範囲とする。そうすると、シリコン基板１１
は、エミッタ電極膜２０などを介して強く押圧されるの
で、シリコン基板１１の第２の主面と下定盤３２との間
に生じる摩擦力が従来技術に係る製造方法を用いる場合
よりも不均一になる。すなわち、シリコン基板１１の第
２の主面の、上定盤３１とエミッタ電極膜２０とが接し
ている部分の下方の部位には、その周辺部よりも大きな
摩擦力が生じるので、周辺部よりも研削厚が大きくな
る。Next, as shown in FIG. 4, while the upper surface plate 31 presses the first main surface side of the silicon substrate 11 as indicated by the arrow A, the lower surface plate 32 causes the silicon substrate 1 to move.
The second main surface side of No. 1 is ground. At this time, the pressing force of the upper surface plate 31 is stronger than that in the case of using the manufacturing method according to the related art, and is within a range in which the silicon substrate 11 is not damaged due to cracks or the like. Then, the silicon substrate 11
Is strongly pressed through the emitter electrode film 20 and the like, so that the frictional force generated between the second main surface of the silicon substrate 11 and the lower surface plate 32 is more uneven than in the case of using the manufacturing method according to the related art. become. That is, since a larger frictional force is generated in the second main surface of the silicon substrate 11 below the portion where the upper surface plate 31 and the emitter electrode film 20 are in contact with each other than in the peripheral portion thereof, Also increases the grinding thickness.
【００２６】したがって、シリコン基板１１を所定の厚
さになるまで研削すると、図５に示すように、上定盤３
１とエミッタ電極膜２０とが接している部分の下方に凹
面部２２ａ，２２ｂが形成される。すなわち、シリコン
基板１１の第１の主面側に形成したパターンの最も厚い
部分の下方に凹面部２２ａ，２２ｂが形成される。同時
に、シリコン基板１１の第２の主面には、凹面部２２の
内面も含めて、研削によるダメージによって結晶欠陥２
４が形成される。なお、上定盤３１によってシリコン基
板１１の第１の主面側を押圧する際の押圧力は、通常の
研削工程における押圧力よりも強くすることが好まし
い。この程度の押圧力を加えると、凹面部２２ａ，２２
ｂがＮ＋型バッファ層１５を貫通し、Ｎ−型ベース層１
２を凹面部２２ａ，２２ｂ内に露出させることが容易に
できる。Therefore, when the silicon substrate 11 is ground to a predetermined thickness, as shown in FIG.
Concave portions 22a and 22b are formed below the portion where 1 and the emitter electrode film 20 are in contact with each other. That is, the concave surface portions 22a and 22b are formed below the thickest portion of the pattern formed on the first main surface side of the silicon substrate 11. At the same time, on the second main surface of the silicon substrate 11, including the inner surface of the concave portion 22, crystal defects 2 due to damage due to grinding are caused.
4 is formed. In addition, it is preferable that the pressing force when the upper surface plate 31 presses the first main surface side of the silicon substrate 11 is stronger than the pressing force in the normal grinding process. When this pressing force is applied, the concave surface portions 22a, 22a
b penetrates the N + type buffer layer 15, and the N − type base layer 1
2 can be easily exposed in the concave portions 22a and 22b.
【００２７】以上の工程によれば、シリコン基板１１の
第２の主面側に、凹面部２２ａ，２２ｂを形成すること
と、結晶欠陥２４を形成することを同時に行うことがで
きる。なお、図３〜図５に示した工程を行う前に、エミ
ッタ電極膜２０上にポリイミド膜等の保護膜を形成して
も良い。また、凹面部２２ａ，２２ｂは、研削工程では
なく、研磨工程で形成しても良い。研磨工程の場合、形
成される結晶欠陥の量がやや少なくなるが、結晶欠陥の
導入が可能である。According to the above steps, it is possible to simultaneously form the concave portions 22a and 22b and the crystal defect 24 on the second main surface side of the silicon substrate 11. A protective film such as a polyimide film may be formed on the emitter electrode film 20 before performing the steps shown in FIGS. The concave portions 22a and 22b may be formed by a polishing process instead of the grinding process. In the case of the polishing step, the amount of crystal defects formed is slightly reduced, but crystal defects can be introduced.
【００２８】以上のように、本発明の第１の実施の形態
に係る半導体装置の製造方法においては、図９および図
１０に示した半導体装置の構成と同様の作用効果を有す
るものを簡便な方法によって実現することができる。ま
た、図９に示した従来技術に係る製造方法においては、
穴部３２７をエッチングによって形成しているが、エッ
チングを用いた場合には、穴部３２７の内面を粗面化す
ることはきわめて困難である。しかし、本発明の第１の
実施の形態に係る半導体装置の製造方法によれば、穴部
３２７に相当する凹面部２２ａ，２２ｂの内面を粗面化
することが容易にできる。しかも、凹面部２２ａ，２２
ｂの内面を粗面化するために、特別の工程を設ける必要
がない。As described above, in the method of manufacturing a semiconductor device according to the first embodiment of the present invention, a semiconductor device having the same effects as those of the semiconductor device shown in FIGS. Can be realized by the method. Further, in the manufacturing method according to the conventional technique shown in FIG.
Although the hole 327 is formed by etching, it is extremely difficult to roughen the inner surface of the hole 327 when etching is used. However, according to the method of manufacturing the semiconductor device of the first embodiment of the present invention, it is possible to easily roughen the inner surfaces of the concave portions 22a and 22b corresponding to the holes 327. Moreover, the concave portions 22a, 22
No special process is required to roughen the inner surface of b.
【００２９】さらに、本発明の第２の実施の形態に係る
半導体装置を図面に基づいて詳細に説明する。図２は、
本発明の第２の実施の形態に係る半導体装置を示す断面
図である。図２中、２５はＰ＋型コレクタ層である。そ
の他の符号は、図１において用いた符号と同じものを示
すものである。Further, a semiconductor device according to a second embodiment of the present invention will be described in detail with reference to the drawings. Figure 2
It is sectional drawing which shows the semiconductor device which concerns on the 2nd Embodiment of this invention. In FIG. 2, 25 is a P + type collector layer. Other reference numerals are the same as those used in FIG.
【００３０】本発明の第２の実施の形態に係る半導体装
置１０は、本発明の第１の実施の形態に係るものとほぼ
同一の構成であるが、Ｐ＋型コレクタ層２５を形成し、
Ｐ＋型コレクタ層２５と、Ｐ＋型コレクタ層２５および
Ｎ＋型バッファ層１５とをオーミック接続している。し
たがって、本発明の第１の実施の形態に係るものより
も、Ｎ＋型バッファ層１５およびＮ−型ベース層１２へ
注入される正孔の量は多くなるが、従来技術に係る半導
体装置よりもオフ時のスイッチング特性を改善すること
が容易にできる。The semiconductor device 10 according to the second embodiment of the present invention has substantially the same structure as that of the first embodiment of the present invention, except that a P + -type collector layer 25 is formed,
The P + -type collector layer 25 is ohmic-connected to the P + -type collector layer 25 and the N + -type buffer layer 15. Therefore, the amount of holes injected into the N + type buffer layer 15 and the N − type base layer 12 is larger than that in the first embodiment of the present invention, but is larger than that in the semiconductor device according to the related art. Also, it is possible to easily improve the switching characteristics at the time of off.
【００３１】なお、凹面部２２ａ，２２ｂの大きさや形
成部位は、シリコン基板１１の第１の主面上に形成する
パターンによって自在に変えることが可能である。図６
は、本発明の第１の実施の形態に係る半導体装置の変形
例を示す断面図である。１６はポリイミド膜、２９は除
去部である。その他の符号は、図１において用いた符号
と同じものを示すものである。The size and formation site of the concave portions 22a and 22b can be freely changed according to the pattern formed on the first main surface of the silicon substrate 11. Figure 6
[FIG. 8] A sectional view showing a modification of the semiconductor device according to the first embodiment of the invention. 16 is a polyimide film, and 29 is a removal part. Other reference numerals are the same as those used in FIG.
【００３２】図６に示すように、この例においては、ポ
リイミド膜１６を形成してから、図３〜図５に示した工
程を施している。また、除去部２９に示すように、ポリ
イミド膜１６を部分的に除去して、ポリイミド膜１６の
厚さに差異を設けている。したがって、凹面部２２は、
シリコン基板１１の第１の主面側に形成したパターンの
厚い部分であるポリイミド膜１６の厚い部分の下方に形
成されている。すなわち、凹面部２２は、研削工程にお
いて、上定盤３１によって強く押圧することによって形
成されるので、除去部２９を形成した部分のように、シ
リコン基板１１の第１の主面側に形成したパターンの最
も厚い部分よりも薄い部分を形成すると、所定の部位に
凹面部２２が形成されないようにすることが容易にでき
る。As shown in FIG. 6, in this example, after the polyimide film 16 is formed, the steps shown in FIGS. 3 to 5 are performed. Further, as shown in the removed portion 29, the polyimide film 16 is partially removed to provide a difference in the thickness of the polyimide film 16. Therefore, the concave surface portion 22 is
It is formed below the thick portion of the polyimide film 16, which is the thick portion of the pattern formed on the first main surface side of the silicon substrate 11. That is, since the concave surface portion 22 is formed by being strongly pressed by the upper surface plate 31 in the grinding step, it is formed on the first main surface side of the silicon substrate 11 like the portion where the removed portion 29 is formed. By forming a thinner portion than the thickest portion of the pattern, it is possible to easily prevent the concave portion 22 from being formed at a predetermined portion.
【００３３】なお、以上説明した２つの実施の形態に係
る半導体装置においては、ＩＧＢＴの構成を主とし、Ｍ
ＯＳＦＥＴの構成を付加的に設けるものとしたが、本発
明は、ＭＯＳＦＥＴの構成を主とし、ＩＧＢＴの構成を
付加的に設ける場合においても好ましく適用できる。こ
の場合、第１の主面側に形成したパターンの一部分のみ
が他のパターンよりも薄くなるようにすることにより、
ＭＯＳＦＥＴの構成を主とする半導体装置を製造するこ
とが容易にできる。また、凹面部の形成は、エミッタ電
極膜およびポリイミド膜を利用するほかに、シリコン酸
化膜など他の膜を用いても良い。要するに、第１の主面
に形成したパターンの最も厚いパターンの最も厚い部分
に凹面部が形成されるので、第２の主面の凹面部に対応
する部位のパターンが最も厚くなるようにすれば良い。In the semiconductor devices according to the two embodiments described above, the structure of the IGBT is mainly used and M
Although the structure of the OSFET is additionally provided, the present invention is mainly applicable to the structure of the MOSFET and is preferably applicable to the case where the structure of the IGBT is additionally provided. In this case, by making only a part of the pattern formed on the first main surface side thinner than the other patterns,
A semiconductor device mainly having a MOSFET structure can be easily manufactured. Further, in forming the concave surface portion, besides the emitter electrode film and the polyimide film, another film such as a silicon oxide film may be used. In short, since the concave portion is formed in the thickest part of the thickest pattern of the first main surface, if the pattern of the portion corresponding to the concave portion of the second main surface is thickest. good.
【００３４】[0034]
【発明の効果】以上のように、本発明は、半導体基板の
第１の主面上にパターンを形成した後に、半導体基板の
第２の主面側を研削するので、第２の主面に凹面部を形
成することが容易にできるとともに、凹面部を含む第２
の主面側に結晶欠陥を形成することができる。したがっ
て、ＩＧＢＴの構成を有する半導体装置の、ターンオフ
時のスイッチング特性の改善を簡便な構造および方法に
よって実現することができる。As described above, according to the present invention, the second main surface side of the semiconductor substrate is ground after the pattern is formed on the first main surface of the semiconductor substrate. The concave portion can be easily formed, and the second portion including the concave portion can be formed.
A crystal defect can be formed on the main surface side of. Therefore, it is possible to improve the switching characteristics of the semiconductor device having the IGBT configuration at turn-off with a simple structure and method.
【図１】本発明の第１の実施の形態に係る半導体装置を
示す断面図である。FIG. 1 is a sectional view showing a semiconductor device according to a first embodiment of the present invention.
【図２】本発明の第２の実施の形態に係る半導体装置を
示す断面図である。FIG. 2 is a sectional view showing a semiconductor device according to a second embodiment of the present invention.
【図３】本発明の第１の実施の形態に係る半導体装置の
製造方法を示す断面図（ａ）である。FIG. 3 is a sectional view (a) showing the method of manufacturing the semiconductor device according to the first embodiment of the invention.
【図４】本発明の第１の実施の形態に係る半導体装置の
製造方法を示す断面図（ｂ）である。FIG. 4 is a sectional view (b) showing the method for manufacturing the semiconductor device according to the first embodiment of the invention.
【図５】本発明の第１の実施の形態に係る半導体装置の
製造方法を示す断面図（ｃ）である。FIG. 5 is a sectional view (c) showing the method for manufacturing the semiconductor device according to the first embodiment of the invention.
【図６】本発明の第１の実施の形態に係る半導体装置の
変形例を示す断面図である。FIG. 6 is a cross-sectional view showing a modified example of the semiconductor device according to the first embodiment of the invention.
【図７】従来技術に係るＩＧＢＴの構成を有する半導体
装置を示す断面図である。FIG. 7 is a sectional view showing a semiconductor device having a configuration of an IGBT according to a conventional technique.
【図８】ＩＧＢＴの構成を有する半導体装置のスイッチ
ング特性を改善した第１の従来例を示す断面図である。FIG. 8 is a cross-sectional view showing a first conventional example in which a semiconductor device having an IGBT configuration has improved switching characteristics.
【図９】ＩＧＢＴの構成を有する半導体装置のスイッチ
ング特性を改善した第２の従来例を示す断面図である。FIG. 9 is a cross-sectional view showing a second conventional example in which a semiconductor device having an IGBT configuration has improved switching characteristics.
【図１０】ＩＧＢＴの構成を有する半導体装置のスイッ
チング特性を改善した第３の従来例を示す断面図であ
る。FIG. 10 is a sectional view showing a third conventional example in which a semiconductor device having an IGBT configuration has improved switching characteristics.
１０ 半導体装置 １１ シリコン基板 １２ Ｎ−型ベース層 １３ Ｐウェル領域 １４ Ｎ＋型エミッタ領域 １５ Ｎ＋型バッファ層 １６ ポリイミド膜 １７ ゲート電極膜 １８ 層間絶縁膜 １９ ゲート絶縁膜 ２０ エミッタ電極膜 ２１ コレクタ電極膜 ２２ 凹面部 ２２ａ 凹面部 ２２ｂ 凹面部 ２３ 粗面 ２４ 結晶欠陥 ２９ 除去部 ３１ 上定盤 ３２ 下定盤 １１０ 半導体装置 １１１ シリコン基板 １１２ Ｎ−型ベース層 １１３ Ｐウェル領域 １１４ Ｎ＋型エミッタ領域 １１５ Ｎ＋型バッファ層 １１７ ゲート電極膜 １１８ 層間絶縁膜 １１９ ゲート絶縁膜 １２０ エミッタ電極膜 １２１ コレクタ電極膜 １２５ Ｐ＋型コレクタ層 ２１０ 半導体装置 ２１１ シリコン基板 ２１２ Ｎ−型ベース層 ２１３ Ｐウェル領域 ２１４ Ｎ＋型エミッタ領域 ２１５ Ｎ＋型バッファ層 ２１７ ゲート電極膜 ２１８ 層間絶縁膜 ２１９ ゲート絶縁膜 ２２０ エミッタ電極膜 ２２１ コレクタ電極膜 ２２５ Ｐ＋型コレクタ層 ２２６ Ｎ＋型ドレイン領域 ３１０ 半導体装置 ３１１ シリコン基板 ３１２ Ｎ−型ベース層 ３１３ Ｐウェル領域 ３１４ Ｎ＋型エミッタ領域 ３１５ Ｎ＋型バッファ層 ３１７ ゲート電極膜 ３１８ 層間絶縁膜 ３１９ ゲート絶縁膜 ３２０ エミッタ電極膜 ３２１ コレクタ電極膜 ３２５ Ｐ＋型コレクタ層 ３２７ 穴部 ４１０ 半導体装置 ４１１ シリコン基板 ４１２ Ｎ−型ベース層 ４１３ Ｐウェル領域 ４１４ Ｎ＋型エミッタ領域 ４１５ Ｎ＋型バッファ層 ４１７ ゲート電極膜 ４１８ 層間絶縁膜 ４１９ ゲート絶縁膜 ４２０ エミッタ電極膜 ４２１ コレクタ電極膜 ４２４ 結晶欠陥 ４２５ Ｐ＋型コレクタ層10 semiconductor device 11 silicon substrate 12 N − type base layer 13 P well region 14 N + type emitter region 15 N + type buffer layer 16 polyimide film 17 gate electrode film 18 interlayer insulating film 19 gate insulating film 20 emitter electrode film 21 collector electrode Film 22 Concave part 22a Concave part 22b Concave part 23 Rough surface 24 Crystal defect 29 Removal part 31 Upper surface plate 32 Lower surface plate 110 Semiconductor device 111 Silicon substrate 112 N − type base layer 113 P well region 114 N + type emitter region 115 N + Type buffer layer 117 gate electrode film 118 interlayer insulating film 119 gate insulating film 120 emitter electrode film 121 collector electrode film 125 P + type collector layer 210 semiconductor device 211 silicon substrate 212 N − type base layer 213 P well region 214 N + type emitter region 215 N + type buffer Layer 217 gate electrode film 218 interlayer insulating film 219 gate insulating film 220 emitter electrode film 221 a collector electrode film 225 P + -type collector layer 226 N + -type drain region 310 a semiconductor device 311 silicon substrate 312 N - type base layer 313 P-well region 314 N + type emitter region 315 N + type buffer layer 317 gate electrode film 318 interlayer insulating film 319 gate insulating film 320 emitter electrode film 321 collector electrode film 325 P + type collector layer 327 hole 410 semiconductor device 411 silicon substrate 412 N − type Base layer 413 P well region 414 N + type emitter region 415 N + type buffer layer 417 Gate electrode film 418 Interlayer insulating film 419 Gate insulating film 420 Emitter electrode film 421 Collector electrode film 424 Crystal defect 425 P + type collector layer
Claims (3)
およびエミッタ電極を形成し、前記半導体基板の第２の
主面上にコレクタ電極を形成してなる半導体装置におい
て、 前記半導体基板に、前記第２の主面に露出するように形
成してなる第１導電型の第１の導電層と、該第１の導電
層に積層させて形成してなる第１導電型の第２の導電層
を設け、 前記第２の主面に前記第１の導電層を貫通する凹面部を
形成して第２の導電層を露出させるとともに、前記凹面
部を含む前記第２の主面を粗面化し、 前記コレクタ電極を前記第１の導電層と前記第２の導電
層とにショットキー接続させてなることを特徴とする半
導体装置。1. A semiconductor device in which a gate electrode and an emitter electrode are formed on a first main surface of a semiconductor substrate and a collector electrode is formed on a second main surface of the semiconductor substrate. A first conductive type first conductive layer formed so as to be exposed on the second main surface, and a first conductive type second conductive layer formed by being laminated on the first conductive layer. A conductive layer is provided, and a concave portion penetrating the first conductive layer is formed on the second main surface to expose the second conductive layer, and the second main surface including the concave portion is roughened. A planarized semiconductor device, wherein the collector electrode is Schottky-connected to the first conductive layer and the second conductive layer.
およびエミッタ電極を形成し、前記半導体基板の第２の
主面上にコレクタ電極を形成してなる半導体装置におい
て、 前記半導体基板に、前記第２の主面に露出するように形
成してなる第２導電型の第１の導電層と、該第１の導電
層に積層させて形成してなる第１導電型の第２の導電層
を設け、 前記第２の主面に前記第１の導電層を貫通する凹面部を
形成して第２の導電層を露出させるとともに、前記凹面
部を含む前記第２の主面を粗面化し、 前記コレクタ電極を前記第１の導電層と前記第２の導電
層とにオーミック接続させてなることを特徴とする半導
体装置。2. A semiconductor device in which a gate electrode and an emitter electrode are formed on a first main surface of a semiconductor substrate, and a collector electrode is formed on a second main surface of the semiconductor substrate. A second conductive type first conductive layer formed so as to be exposed on the second main surface, and a first conductive type second conductive layer formed by being laminated on the first conductive layer. A conductive layer is provided, and a concave portion penetrating the first conductive layer is formed on the second main surface to expose the second conductive layer, and the second main surface including the concave portion is roughened. A planarized semiconductor device, wherein the collector electrode is ohmic-connected to the first conductive layer and the second conductive layer.
およびエミッタ電極を形成する工程と、 前記半導体基板の第２の主面から不純物を注入して加熱
拡散することにより、該第２の主面に露出する第１の導
電層および該第１の導電層に積層される第２の導電層を
形成する工程と、 前記半導体基板を前記第１の主面側から押圧しつつ、前
記半導体基板を前記第２の主面側から研削することによ
り、前記第２の主面全体を研削しつつ、前記第２の主面
の、前記ゲート電極と前記エミッタ電極との双方または
いずれか一方に対応する部位に、前記第１の導電層を貫
通して前記第２の導電層を露出させる凹面部を形成する
工程と、 前記凹面部を含む前記第２の主面上にコレクタ電極を形
成する工程を有することを特徴とする半導体装置の製造
方法。3. A step of forming a gate electrode and an emitter electrode on a first main surface of a semiconductor substrate, and a step of implanting impurities from the second main surface of the semiconductor substrate and thermally diffusing the impurities, thereby forming the second electrode. Forming a first conductive layer exposed on the main surface of the first conductive layer and a second conductive layer laminated on the first conductive layer; and pressing the semiconductor substrate from the first main surface side, By grinding the semiconductor substrate from the second main surface side, the entire second main surface is ground and at the same time, either or both of the gate electrode and the emitter electrode of the second main surface are ground. Forming a concave surface portion that penetrates the first conductive layer and exposes the second conductive layer at a portion corresponding to, and forming a collector electrode on the second main surface including the concave surface portion. A method of manufacturing a semiconductor device, comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2002049357A JP3907174B2 (en) | 2002-02-26 | 2002-02-26 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2002049357A JP3907174B2 (en) | 2002-02-26 | 2002-02-26 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2003249654A true JP2003249654A (en) | 2003-09-05 |
| JP3907174B2 JP3907174B2 (en) | 2007-04-18 |
Family
ID=28661893
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2002049357A Expired - Fee Related JP3907174B2 (en) | 2002-02-26 | 2002-02-26 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3907174B2 (en) |
Cited By (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007129195A (en) * | 2005-10-05 | 2007-05-24 | Sanken Electric Co Ltd | Semiconductor device |
| JP2008047772A (en) * | 2006-08-18 | 2008-02-28 | Sanken Electric Co Ltd | Insulated gate bipolar transistor |
| JP2009200098A (en) * | 2008-02-19 | 2009-09-03 | Toyota Motor Corp | Igbt, and manufacturing method thereof |
| JP2010135573A (en) * | 2008-12-05 | 2010-06-17 | Mitsubishi Electric Corp | Silicon carbide semiconductor device and method of manufacturing the same |
| JP2010258327A (en) * | 2009-04-28 | 2010-11-11 | Fuji Electric Systems Co Ltd | Vertical gallium nitride semiconductor device having reverse withstand voltage |
| KR101015460B1 (en) * | 2008-01-23 | 2011-02-18 | 미쓰비시덴키 가부시키가이샤 | Semiconductor device |
| CN103022099A (en) * | 2013-01-10 | 2013-04-03 | 江苏物联网研究发展中心 | IGBT (insulated gate bipolar transistor) collector structure and production method thereof |
| WO2013172059A1 (en) * | 2012-05-15 | 2013-11-21 | 富士電機株式会社 | Semiconductor device |
| JP2014150226A (en) * | 2013-02-04 | 2014-08-21 | Lapis Semiconductor Co Ltd | Semiconductor device and semiconductor device manufacturing method |
| CN104253154A (en) * | 2013-06-28 | 2014-12-31 | 无锡华润上华半导体有限公司 | IGBT (insulated gate bipolar transistor) with inlaid diode and manufacturing method of IGBT |
| CN104253152A (en) * | 2013-06-28 | 2014-12-31 | 无锡华润上华半导体有限公司 | IGBT (insulated gate bipolar transistor) and manufacturing method thereof |
| JPWO2013031212A1 (en) * | 2011-08-29 | 2015-03-23 | 富士電機株式会社 | Bidirectional element, bidirectional element circuit, and power converter |
| EP2560206A4 (en) * | 2010-04-15 | 2016-04-13 | Yoshitaka Sugawara | Semiconductor device |
| WO2016169818A1 (en) | 2015-04-24 | 2016-10-27 | Abb Technology Ag | Power semiconductor device with thick top-metal-design and method for manufacturing such power semiconductor device |
| WO2018016029A1 (en) * | 2016-07-20 | 2018-01-25 | 三菱電機株式会社 | Semiconductor device and method for manufacturing same |
| WO2023155584A1 (en) * | 2022-02-21 | 2023-08-24 | 珠海零边界集成电路有限公司 | Insulated gate bipolar transistor, manufacturing method, electronic device, and storage medium |
| WO2023155585A1 (en) * | 2022-02-21 | 2023-08-24 | 珠海零边界集成电路有限公司 | Insulated gate bipolar transistor and manufacturing method therefor, electronic device and storage medium |
-
2002
- 2002-02-26 JP JP2002049357A patent/JP3907174B2/en not_active Expired - Fee Related
Cited By (27)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007129195A (en) * | 2005-10-05 | 2007-05-24 | Sanken Electric Co Ltd | Semiconductor device |
| JP2008047772A (en) * | 2006-08-18 | 2008-02-28 | Sanken Electric Co Ltd | Insulated gate bipolar transistor |
| KR101015460B1 (en) * | 2008-01-23 | 2011-02-18 | 미쓰비시덴키 가부시키가이샤 | Semiconductor device |
| US8017974B2 (en) * | 2008-01-23 | 2011-09-13 | Mitsubishi Electric Corporation | Semiconductor device with increased withstand voltage |
| US8274095B2 (en) | 2008-01-23 | 2012-09-25 | Mitsubishi Electric Corporation | Semiconductor device |
| JP2009200098A (en) * | 2008-02-19 | 2009-09-03 | Toyota Motor Corp | Igbt, and manufacturing method thereof |
| JP4544313B2 (en) * | 2008-02-19 | 2010-09-15 | トヨタ自動車株式会社 | IGBT and its manufacturing method |
| US8242535B2 (en) | 2008-02-19 | 2012-08-14 | Toyota Jidosha Kabushiki Kaisha | IGBT and method of producing the same |
| JP2010135573A (en) * | 2008-12-05 | 2010-06-17 | Mitsubishi Electric Corp | Silicon carbide semiconductor device and method of manufacturing the same |
| JP2010258327A (en) * | 2009-04-28 | 2010-11-11 | Fuji Electric Systems Co Ltd | Vertical gallium nitride semiconductor device having reverse withstand voltage |
| EP2560206A4 (en) * | 2010-04-15 | 2016-04-13 | Yoshitaka Sugawara | Semiconductor device |
| US9478645B2 (en) | 2011-08-29 | 2016-10-25 | Fuji Electric Co., Ltd. | Bidirectional device, bidirectional device circuit and power conversion apparatus |
| JPWO2013031212A1 (en) * | 2011-08-29 | 2015-03-23 | 富士電機株式会社 | Bidirectional element, bidirectional element circuit, and power converter |
| WO2013172059A1 (en) * | 2012-05-15 | 2013-11-21 | 富士電機株式会社 | Semiconductor device |
| CN103022099A (en) * | 2013-01-10 | 2013-04-03 | 江苏物联网研究发展中心 | IGBT (insulated gate bipolar transistor) collector structure and production method thereof |
| JP2014150226A (en) * | 2013-02-04 | 2014-08-21 | Lapis Semiconductor Co Ltd | Semiconductor device and semiconductor device manufacturing method |
| WO2014206160A1 (en) * | 2013-06-28 | 2014-12-31 | 无锡华润上华半导体有限公司 | Insulated gate bipolar transistor and manufacturing method therefor |
| CN104253152A (en) * | 2013-06-28 | 2014-12-31 | 无锡华润上华半导体有限公司 | IGBT (insulated gate bipolar transistor) and manufacturing method thereof |
| CN104253154A (en) * | 2013-06-28 | 2014-12-31 | 无锡华润上华半导体有限公司 | IGBT (insulated gate bipolar transistor) with inlaid diode and manufacturing method of IGBT |
| WO2016169818A1 (en) | 2015-04-24 | 2016-10-27 | Abb Technology Ag | Power semiconductor device with thick top-metal-design and method for manufacturing such power semiconductor device |
| JP2018516459A (en) * | 2015-04-24 | 2018-06-21 | アーベーベー・シュバイツ・アーゲー | Power semiconductor device having a thick upper metal design and method of manufacturing the power semiconductor device |
| US10141196B2 (en) | 2015-04-24 | 2018-11-27 | Abb Schweiz Ag | Power semiconductor device with thick top-metal-design and method for manufacturing such power semiconductor device |
| WO2018016029A1 (en) * | 2016-07-20 | 2018-01-25 | 三菱電機株式会社 | Semiconductor device and method for manufacturing same |
| JPWO2018016029A1 (en) * | 2016-07-20 | 2018-12-06 | 三菱電機株式会社 | Semiconductor device and manufacturing method thereof |
| US10665670B2 (en) | 2016-07-20 | 2020-05-26 | Mitsubishi Electric Corporation | Semiconductor device and method for manufacturing same |
| WO2023155584A1 (en) * | 2022-02-21 | 2023-08-24 | 珠海零边界集成电路有限公司 | Insulated gate bipolar transistor, manufacturing method, electronic device, and storage medium |
| WO2023155585A1 (en) * | 2022-02-21 | 2023-08-24 | 珠海零边界集成电路有限公司 | Insulated gate bipolar transistor and manufacturing method therefor, electronic device and storage medium |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3907174B2 (en) | 2007-04-18 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP3907174B2 (en) | Semiconductor device | |
| JP6402773B2 (en) | Semiconductor device and manufacturing method thereof | |
| US9941395B2 (en) | Insulated gate semiconductor device and method for manufacturing the same | |
| JP5807724B2 (en) | Semiconductor device and manufacturing method of semiconductor device | |
| JP5754397B2 (en) | Manufacturing method of vertical trench IGBT | |
| WO2014013618A1 (en) | Semiconductor device and method for manufacturing same | |
| JP5509543B2 (en) | Manufacturing method of semiconductor device | |
| JP2007012972A (en) | Semiconductor device and its manufacturing method | |
| JP2008140828A (en) | Semiconductor device and method for manufacturing the same | |
| JP2004158844A (en) | Semiconductor device and method of manufacturing the same | |
| KR100689208B1 (en) | Semiconductor device and manufacturing process thereof | |
| JP2004247593A (en) | Semiconductor device, and manufacturing method thereof | |
| CN113809145B (en) | Narrow mesa insulated gate bipolar transistor device and method of forming | |
| JP2004221370A (en) | Semiconductor device | |
| JP5070668B2 (en) | Semiconductor device | |
| JP2024512868A (en) | MOSFET device and its manufacturing method | |
| JP2004296819A (en) | Semiconductor device | |
| JP4097416B2 (en) | Insulated gate bipolar transistor and manufacturing method thereof | |
| JP2008053610A (en) | Insulated-gate bipolar transistor | |
| JP2000223708A (en) | Semiconductor device | |
| JP2005136116A (en) | Semiconductor element and its manufacturing method | |
| JP2003289145A (en) | Horizontal power mos transistor and manufacturing method therefor | |
| KR20140033078A (en) | Bipolar punch-through semiconductor device and method for manufacturing such a semiconductor device | |
| US20240120406A1 (en) | Method of manufacturing semiconductor device | |
| WO2024034277A1 (en) | Silicon carbide semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20050105 |
|
| A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20061129 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20061201 |
|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20061206 |
|
| TRDD | Decision of grant or rejection written | ||
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20070112 |
|
| A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20070115 |
|
| R150 | Certificate of patent or registration of utility model |
Ref document number: 3907174 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100126 Year of fee payment: 3 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110126 Year of fee payment: 4 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110126 Year of fee payment: 4 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120126 Year of fee payment: 5 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120126 Year of fee payment: 5 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130126 Year of fee payment: 6 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130126 Year of fee payment: 6 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20140126 Year of fee payment: 7 |
|
| LAPS | Cancellation because of no payment of annual fees |