JP2003249595A - Transferred wiring support member - Google Patents
Transferred wiring support memberInfo
- Publication number
- JP2003249595A JP2003249595A JP2003087870A JP2003087870A JP2003249595A JP 2003249595 A JP2003249595 A JP 2003249595A JP 2003087870 A JP2003087870 A JP 2003087870A JP 2003087870 A JP2003087870 A JP 2003087870A JP 2003249595 A JP2003249595 A JP 2003249595A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- nickel
- copper
- pattern
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、転写配線支持部材
及びそれを使用した半導体パッケージの製造法に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transfer wiring supporting member and a semiconductor package manufacturing method using the same.
【０００２】[0002]
【従来の技術】電子機器の小型化、高速化に伴い、プリ
ント配線板上に半導体チップを高密度に実装する必要性
が増大している。理想的には、半導体チップを直接プリ
ント板上に実装できれば良いが、プリント板には、主に
シリコンでできた該チップに対する熱膨張係数の整合や
高放熱性、高配線密度などが要求される。このため、Ｑ
ＦＰ（Ｑｕａｄ Ｆｌａｔ Ｐａｃｋａｇｅ）をはじめ
とするリードパッケージが、プリント配線板に実装され
る場合が多い。しかし、入出力端子の増大に伴い、半導
体チップの周辺に二次元的に入出力端子を設けるピン挿
入型のＰＧＡ（Ｐｉｎ Ｇｒｉｄ Ａｒｒａｙ）が開発
されている。このＰＧＡでは、表面実装に適しないこと
から、入出力端子にハンダボールを形成する表面実装型
のＢＧＡ（Ｂａｌｌ Ｇｒｉｄ Ａｒｒａｙ）が開発さ
れている。さらに、パッケージを小型化するため、半導
体チップの周辺に、半導体チップとの接続端子を設け、
その端子と接続して実装領域内に配線と入出力端子を設
けるＣＳＰ（Ｃｈｉｐ Ｓｉｚｅ Ｐａｃｋａｇｅ）が
開発されている。これらは、チップキャリアパッケージ
として知られ、半導体チップをセラミックやプラスチッ
クの基板あるいはフィルムに実装し、封止材でトランス
ファモールドする形態をとる。このようなパッケージで
セラミック基板をベースとした場合、有機材料からなる
プリント板への実装は、熱膨張係数の不整合から接続部
での信頼性が低下し不利である。これに対しては、プラ
スチックの基板あるいはフィルムをベースとした場合が
有利であり、比較的安価である。しかし、熱放散性が低
く、耐吸湿性の改善が不可欠となっている。これらの問
題を解決する手段として、所定の配線が仮基板上にパタ
ーンめっきまたはエッチングで形成され、その形成され
た配線にチップを実装してモールドし、仮基板を剥離す
る転写モールドが提案されている。その中で、金属ベー
スにパターンめっきをする方法として、特開昭５９−２
０８７５６と特開平３−９４４５９がある。前者には、
厚さ３５μｍのＦｅ製基板に１μｍ金、１μｍニッケ
ル、３μｍ金属を順にパターンめっきし、半導体チップ
をＷ／Ｂ接続する。モールド前にめっきパターン下をア
ンダーエッチングする方法が示されている。この方法で
は、配線引き剥がし強度は改善されるものの、モールド
と配線界面での密着力が悪く、耐湿試験で信頼性が低下
する。また後者では、充分な配線の引き剥がし強度が得
られない。一方、電解銅箔をベースフィルムに接合した
転写フィルムをパターンエッチングして、チップ実装後
モールドする方法が特開平３−９９４５６に示されてい
る。エッチングでは微細配線に不利であり、フィルム面
を剥離したあとのモールド表面は、極めてフラットであ
り、ハンダボールなど外部端子接続を形成する際の保護
膜、例えばソルダレジストの密着性に問題が生じる。2. Description of the Related Art With the miniaturization and speeding up of electronic equipment, there is an increasing need for mounting semiconductor chips on a printed wiring board at a high density. Ideally, the semiconductor chip can be directly mounted on the printed board. However, the printed board is required to have a matching coefficient of thermal expansion with the chip, which is mainly made of silicon, high heat dissipation, and high wiring density. . Therefore, Q
A lead package such as an FP (Quad Flat Package) is often mounted on a printed wiring board. However, with the increase in the number of input / output terminals, a pin insertion type PGA (Pin Grid Array) in which the input / output terminals are two-dimensionally provided around the semiconductor chip has been developed. Since this PGA is not suitable for surface mounting, a surface mounting type BGA (Ball Grid Array) in which solder balls are formed on input / output terminals has been developed. Furthermore, in order to miniaturize the package, a connection terminal to the semiconductor chip is provided around the semiconductor chip,
A CSP (Chip Size Package) has been developed which is connected to the terminal and has a wiring and an input / output terminal in a mounting area. These are known as chip carrier packages, and have a form in which a semiconductor chip is mounted on a ceramic or plastic substrate or film and transfer molded with a sealing material. When a ceramic substrate is used as a base in such a package, mounting on a printed board made of an organic material is disadvantageous because the reliability of the connection portion is reduced due to mismatch of thermal expansion coefficients. On the other hand, it is advantageous to use a plastic substrate or film as a base, and it is relatively inexpensive. However, heat dissipation is low, and improvement in moisture absorption resistance is essential. As a means for solving these problems, a transfer mold has been proposed in which a predetermined wiring is formed on a temporary substrate by pattern plating or etching, a chip is mounted on the formed wiring and molded, and the temporary substrate is peeled off. There is. Among them, Japanese Patent Laid-Open No. 59-2 is a method for pattern plating a metal base.
08756 and JP-A-3-94459. For the former,
1 μm gold, 1 μm nickel, and 3 μm metal are sequentially pattern-plated on a Fe substrate having a thickness of 35 μm, and semiconductor chips are connected by W / B. A method of under-etching under the plating pattern before molding is shown. With this method, the peeling strength of the wiring is improved, but the adhesion between the mold and the wiring interface is poor, and the reliability decreases in the humidity resistance test. Further, in the latter case, sufficient peeling strength of the wiring cannot be obtained. On the other hand, Japanese Patent Application Laid-Open No. 3-99456 discloses a method of pattern-etching a transfer film in which an electrolytic copper foil is bonded to a base film, and mounting the chip and then molding. Etching is disadvantageous for fine wiring, and the mold surface after peeling off the film surface is extremely flat, which causes a problem with the adhesion of a protective film, for example, a solder resist when forming external terminal connections such as solder balls.
【０００３】[0003]
【発明が解決しようとする課題】本発明は、配線とモー
ルド界面の密着力を向上させ、充分な配線の引き剥がし
強度を確保し、ならびに仮基板を剥離したあと、モール
ド表面粗化を可能とする半導体パッケージの製造法を提
供するものである。SUMMARY OF THE INVENTION According to the present invention, the adhesion between the wiring and the mold interface is improved, sufficient peeling strength of the wiring is secured, and the mold surface can be roughened after the temporary substrate is peeled off. A method of manufacturing a semiconductor package is provided.
【０００４】[0004]
【課題を解決するための手段】本願の第一の発明は、
（１ａ）選択的にエッチング可能な第一、第二の２層の
金属からなる支持材の片面上である第二の金属上に、該
第二の金属と選択的にエッチング可能な金属を配線形成
する工程、（１ｂ）該配線上の所定の位置に、チップ実
装用のニッケル、金のめっきを形成する工程、（１ｃ）
該配線を粗化処理する工程により製造された転写配線支
持部材及びこの転写配線支持部材を使用した半導体パッ
ケージの製造法である。The first invention of the present application is
(1a) Wiring a metal that can be selectively etched with the second metal on a second metal that is one surface of a support material composed of first and second two-layer metal that can be selectively etched Forming step, (1b) forming nickel and gold plating for chip mounting at a predetermined position on the wiring, (1c)
A transfer wiring supporting member manufactured by a process of roughening the wiring, and a semiconductor package manufacturing method using the transfer wiring supporting member.
【０００５】本願の第二の発明は、（２ａ）選択的にエ
ッチング可能な第一、第二の２層の金属からなる支持材
の片面上である第二の金属上に、該第二の金属と選択的
にエッチング可能な金属を配線形成する工程、（２ｂ）
該配線上の所定の位置に、チップ実装用のニッケル、金
のめっきを形成する工程、（２ｃ）配線相互間隙にある
該第二の金属を剥離すると共に、第二の金属層間に接し
てある配線の下部をテーパ状にエッチングする工程、
（２ｄ）露出した第一の金属と共に、該配線を粗化処理
する工程により製造された転写配線支持部材及びこの転
写配線支持部材を使用した半導体パッケージの製造法で
ある。The second invention of the present application is: (2a) a second metal, which is one surface of a support material composed of first and second two-layer metal capable of being selectively etched, on the second metal. A step of forming a wiring with a metal that can be selectively etched, (2b)
Step of forming nickel and gold plating for chip mounting at a predetermined position on the wiring, (2c) peeling off the second metal in the mutual gap between the wirings, and contacting between the second metal layers A step of etching the lower part of the wiring into a taper shape,
(2d) A transfer wiring supporting member manufactured by a step of roughening the wiring together with the exposed first metal, and a method of manufacturing a semiconductor package using the transfer wiring supporting member.
【０００６】[0006]
【発明の実施の形態】本願の第一の発明では、
１．電解銅箔とその上にニッケルめっきされた２層箔の
ニッケル面側にパターン銅めっきでチップ実装用パッド
部とチップ実装用パッドを含む配線パターンを形成する
工程
２．配線パターンのなかで選択的にチップ実装用パッド
部にニッケル金めっきを形成する工程
３．ニッケル金めっきされた配線パターン部以外の露出
した銅配線部分を酸化還元処理する工程
４．チップ実装用パッド部に半導体チップを実装し、ニ
ッケル金めっきが形成されたチップ実装用パッド部とチ
ップの外部電極とを配線接続する工程
５．半導体チップと配線パターン部を樹脂封止する工程
６．電解銅箔とニッケルをエッチングする工程
７．転写した配線側に、保護膜を形成し、外部端子部を
露出させ、ニッケル、金めっきする工程
８．金めっきされた外部端子部にハンダボールを接続す
る工程
により半導体パッケージを製造する。BEST MODE FOR CARRYING OUT THE INVENTION In the first invention of the present application, 1. 1. A step of forming a wiring pattern including a chip mounting pad portion and a chip mounting pad by pattern copper plating on the nickel surface side of an electrolytic copper foil and a nickel-plated two-layer foil. Step of selectively forming nickel-gold plating on the chip mounting pad portion in the wiring pattern 3. 3. A step of subjecting exposed copper wiring portions other than the nickel-gold plated wiring pattern portion to redox treatment. 4. A step of mounting a semiconductor chip on the chip mounting pad section and wire-connecting the chip mounting pad section having nickel gold plating formed thereon and the external electrode of the chip. Step 6 of resin-sealing the semiconductor chip and the wiring pattern portion Step of etching electrolytic copper foil and nickel 7. Step 8 of forming a protective film on the transferred wiring side, exposing the external terminal portion, and plating with nickel and gold A semiconductor package is manufactured by the process of connecting a solder ball to the gold-plated external terminal portion.
【０００７】本願の第二の発明では、
１．電解銅箔とその上にニッケルめっきされた２層箔の
ニッケル面側にパターン銅めっきでチップ実装用パド部
とチップ実装用パッドを含む配線パターンを形成する工
程
２．配線パターンのなかで選択的にチップ実装用パッド
部にニッケル金めっきを形成する工程
３．配線パターン相互間隙のニッケルをエッチングする
工程
４．ニッケル金めっきされた配線パターン部以外の露出
した銅配線部分及び配線パターン相互間隙の露出した電
解銅箔部分を酸化還元処理する工程
５．チップ実装用パッド部に半導体チップを実装し、ニ
ッケル金めっきが形成されたチップ実装用パッド部とチ
ップの外部電極とを配線接続する工程
６．半導体チップと配線パターン部を樹脂封止する工程
７．電解銅箔をエッチングする工程
８．転写した配線側に、保護膜を形成し、外部端子部を
露出させ、金めっきする工程
９．金めっきされた外部端子部にハンダボールを接続す
る工程
により半導体パッケージを製造する。In the second invention of the present application, 1. A step of forming a wiring pattern including a chip mounting pad portion and a chip mounting pad by pattern copper plating on the nickel surface side of an electrolytic copper foil and a nickel-plated two-layer foil. Step of selectively forming nickel-gold plating on the chip mounting pad portion in the wiring pattern 3. 3. Process of etching nickel in the inter-wiring pattern gaps 4. A step of subjecting the exposed copper wiring portion other than the nickel-gold plated wiring pattern portion and the exposed electrolytic copper foil portion in the wiring pattern mutual gap portion to redox treatment. 5. A step of mounting a semiconductor chip on the chip mounting pad portion and wire-connecting the chip mounting pad portion formed with nickel gold plating and the external electrode of the chip. Step 7 of resin-sealing the semiconductor chip and the wiring pattern portion Step of etching electrolytic copper foil 8. Step of forming a protective film on the transferred wiring side, exposing the external terminal portion, and performing gold plating 9. A semiconductor package is manufactured by the process of connecting a solder ball to the gold-plated external terminal portion.
【０００８】[0008]
【作用】第一の発明により、配線パターンとモールドと
の界面が酸化還元銅の粗化形状を有することで密着力が
増し、耐吸湿性が改善される。第二の発明により、配線
パターンとモールドとの界面が酸化還元銅の粗化形状を
有することで密着力が増し、耐吸湿性が改善される。ま
た、ニッケルエッチング時に配線パターンにおいて局部
電池と思われる現象が生じ、めっき銅の下部にテーパが
生成され、これにより、モールド後配線引き剥がし強度
が増大する。さらに、ニッケルエッチングによりパター
ン相互間隙の電極銅箔が露出し、銅の酸化還元でパター
ン相互間隙も粗化形状となり、モールド及び電解銅箔の
剥離でモールド表面が粗化形状転写され、保護膜の密着
力改善に作用する。According to the first aspect of the invention, the interface between the wiring pattern and the mold has a roughened shape of redox copper, so that the adhesion is increased and the moisture absorption resistance is improved. According to the second aspect of the invention, the interface between the wiring pattern and the mold has a roughened shape of redox copper, so that the adhesion is increased and the moisture absorption resistance is improved. In addition, a phenomenon that seems to be a local battery occurs in the wiring pattern during nickel etching, and a taper is formed under the plated copper, which increases the wiring peeling strength after molding. Furthermore, the electrode copper foil in the pattern mutual gap is exposed by nickel etching, and the pattern mutual gap is also roughened by the oxidation and reduction of copper, and the mold surface is transferred by peeling the mold and electrolytic copper foil, and the protective film of the protective film is transferred. Acts to improve adhesion.
【０００９】[0009]
【実施例】実施例１
図１は、本発明に係わる転写モールドパッケージの製造
方法における実施例１である。
工程 １）まず、転写箔の製造では、銅（〜１）とニッ
ケル（〜２）からなる２層箔のニッケル面に金めっきレ
ジスト（〜３）をラミネートする。例えば、日立化成製
フォテックＨＮ６４０を真空ラミネートする。配線パタ
ーンをポジイメージとするマスクを露光し、現像する。
ニッケル面上には、配線パターンのイメージを除く部分
がレジストとして形成される。
工程 ２）次のパターンめっきでは、キャリア（銅とニ
ッケル）を電極として、該レジスト間隙に銅を電気めっ
きする。これにより、チップ実装用パッドを含む配線
（〜４）ならびに配線ＤＢ（ダイボンド）用パッド（〜
４’）が形成される。
工程 ３）、４）、５）次に、配線パターンに含まれる
チップ実装用パッド部をニッケル、金の順でめっきす
る。このため、該パッド部以外をマスクする。この工程
では、パッドの大きさ、ピッチに応じて配線パターンの
マスク方法を選択することが望ましい。ひとつは２段レ
ジスト工程、もうひとつは部分レジスト工程をとる。前
者の工程では、パターンめっき後レジスト上に、さらに
該レジスト（〜３’）をラミネートし、図２に示すよう
に、該パッド部から外側に沿面をとってマスクし露光、
現像でパッド部を露出させる。一方後者の工程では、パ
ターンめっき後レジストを剥離し、配線パターン全体を
露出させる。これに該レジスト（〜３’）を真空ラミネ
ートし、図３に示すように、該端子部か内側に沿面をと
ってマスクし露光、現像によりパッドの一部を露出させ
る。この両工程のいずれかを経て、露出されたパッド部
上に無電解ニッケル、金または、該キャリアを電極とし
た電解ニッケル金をめっきする。
工程 ６）この後、レジストを剥離する。これにより、
図１に示すようにすべて無機材料から構成される箔が形
成される。
工程 ７）この箔を酸化還元処理する。図１の４及び
４’で示す表面の銅が酸化銅の粗化形状を保持した状態
で還元銅となる。
工程 ８）次に、図１に示すように、チップ（〜６）を
ＤＢ材（〜７）を介して、ニッケル面上に銅めっきされ
たＤＢ用パッド（〜４’）に接着する。その後、該チッ
プの外部電極と該転写箔の該チップ実装用パッド間をワ
イヤボンディング（〜８）接続する。この後、図１に示
すようにトランスファー形成により、封止材（〜９）で
モールドする。
工程 ９）この後、該キャリア銅をメルテックス社製ア
ルカリエッチング液エープロセスを用いてエッチングす
る。この時、ニッケルはエッチングされず、転写された
銅パターンのエッチングを防いでいる。次に、該キャリ
アのニッケルをメルテックス社製ニッケルエッチング液
Ｎ−９５０を用いて選択エッチングする。この時、転写
された銅パターンはエッチングされない。これにより、
転写パターン表面はモールド面と同一レベルにある。
工程 １０）次に、太陽インク製ソルダレジストインク
ＰＳＲ４０００−ＡＵＳ５をスクリーン印刷後、表１に
示す工程を経て、外部端子用パッド部以外にソルダレジ
スト（〜１０）形成する。次に、無電解ニッケル、金を
めっき（〜５’）をする。
工程 １１）最後に、ハンダボールを所定の位置に設置
し、赤外線リフロを用いてハンダボール（〜１１）を接
続する。EXAMPLE 1 FIG. 1 shows Example 1 of a method for manufacturing a transfer mold package according to the present invention. Step 1) First, in the production of a transfer foil, a gold plating resist (~ 3) is laminated on the nickel surface of a two-layer foil made of copper (~ 1) and nickel (~ 2). For example, Hitachi Chemical Fotec HN640 is vacuum laminated. A mask having a wiring pattern as a positive image is exposed and developed.
A portion other than the image of the wiring pattern is formed as a resist on the nickel surface. Step 2) In the next pattern plating, copper is electroplated in the resist gap using the carrier (copper and nickel) as electrodes. Thereby, the wiring including the chip mounting pad (to 4) and the pad for wiring DB (die bond) (to
4 ') is formed. Steps 3), 4), 5) Next, the chip mounting pad portion included in the wiring pattern is plated in the order of nickel and gold. Therefore, the parts other than the pad part are masked. In this step, it is desirable to select a mask method for the wiring pattern according to the size and pitch of the pads. One is a two-step resist process and the other is a partial resist process. In the former step, the resist (up to 3 ′) is further laminated on the resist after pattern plating, and as shown in FIG.
The pad part is exposed by development. On the other hand, in the latter process, the resist is peeled off after pattern plating to expose the entire wiring pattern. The resist (to 3 ') is vacuum-laminated on this, and as shown in FIG. 3, a part of the pad is exposed by masking by exposing a creeping surface to the inside of the terminal portion or exposing. Through either of these steps, electroless nickel, gold, or electrolytic nickel gold using the carrier as an electrode is plated on the exposed pad portion. Step 6) Thereafter, the resist is peeled off. This allows
As shown in FIG. 1, a foil composed entirely of inorganic material is formed. Step 7) This foil is subjected to redox treatment. The copper on the surfaces indicated by 4 and 4'in FIG. 1 becomes reduced copper in a state where the roughened shape of copper oxide is retained. Step 8) Next, as shown in FIG. 1, the chip (~ 6) is bonded to the DB pad (~ 4 ') plated with copper on the nickel surface via the DB material (~ 7). After that, the external electrodes of the chip and the chip mounting pads of the transfer foil are connected by wire bonding (up to 8). After this, as shown in FIG. 1, transfer molding is performed to mold with the encapsulating material (to 9). Step 9) Thereafter, the carrier copper is etched by using an alkaline etching solution A process manufactured by Meltex. At this time, nickel is not etched, and etching of the transferred copper pattern is prevented. Next, the nickel of the carrier is selectively etched using a nickel etching solution N-950 manufactured by Meltex. At this time, the transferred copper pattern is not etched. This allows
The transfer pattern surface is at the same level as the mold surface. Step 10) Next, after screen-printing a solder resist ink PSR4000-AUS5 made by Taiyo Ink, through steps shown in Table 1, a solder resist (~ 10) is formed in addition to the external terminal pad portion. Next, electroless nickel and gold are plated (~ 5 '). Step 11) Finally, a solder ball is set at a predetermined position, and the infrared reflow is used to connect the solder balls (to 11).
【００１０】実施例２
図４は、本発明に係わる転写モールドパッケージの製造
方法における実施例２である。実施例１で示した図１の
工程６）で得られた転写箔を該ニッケルエッチングに浸
漬する。これにより図４に示すように、めっきされた配
線パターン間隙のニッケルをエッチングする。この時、
転写箔の断面は、パッケージ銅直下のニッケルは、エッ
チングされずに、パターン銅下部がテーパ状にエッチン
グされる。これは、パターン銅、ニッケル、電解銅箔が
局部電池となり、パターン銅とニッケルの界面付近で、
ニッケルのエッチングを抑制し、逆に銅のエッチングレ
ートが増大すると考えられる。次に、得られた箔を酸化
還元処理する。この後、実施例１で示した同様の工程を
８’）〜１１’）を実施する。ただし、キャリアの剥離
では、銅のみをエッチングする。Second Embodiment FIG. 4 shows a second embodiment of the method for manufacturing a transfer mold package according to the present invention. The transfer foil obtained in step 6) of FIG. 1 shown in Example 1 is immersed in the nickel etching. Thereby, as shown in FIG. 4, nickel in the plated wiring pattern gap is etched. At this time,
In the cross section of the transfer foil, nickel directly under the package copper is not etched, but the lower part of the pattern copper is etched in a tapered shape. This is because the pattern copper, nickel, electrolytic copper foil becomes a local battery, and near the interface between the pattern copper and nickel,
It is considered that the nickel etching is suppressed and the copper etching rate is increased. Next, the obtained foil is subjected to redox treatment. After this, the same steps as in Example 1 are carried out 8 ') to 11'). However, in peeling the carrier, only copper is etched.
【００１１】ソルダレジスト形成の工程を次に示す。
インク混合 ：主剤７０、硬化剤３０（重量比）
熱風乾燥 ：８０℃、２０〜３０分
露光 ：５００ｍＪ／ｃｍ2
現像 ：１ｗｔ％−Ｎａ2ＣＯ3 ３０℃ ６０〜
９０秒
流水洗を十分行うこと
ポストキュア：１５０℃、６０分
ポスト露光 ：２０００ｍＪ／ｃｍ2 The steps of forming the solder resist will be described below. Ink mixture: Main agent 70, curing agent 30 (weight ratio) Hot air drying: 80 ° C., 20 to 30 minutes exposure: 500 mJ / cm 2 development: 1 wt% -Na 2 CO 3 30 ° C. 60 to
Sufficient 90 seconds of running water wash Post cure: 150 ° C, 60 minutes Post exposure: 2000 mJ / cm 2
【００１２】[0012]
【発明の効果】本発明により、耐吸湿性に優れた半導体
パッケージを製造できる。According to the present invention, a semiconductor package having excellent moisture absorption resistance can be manufactured.
【図１】実施例１の製造工程を示す断面図。FIG. 1 is a cross-sectional view showing a manufacturing process of a first embodiment.
【図２】２段レジスト工程におけるマスキングの平面
図。FIG. 2 is a plan view of masking in a two-step resist process.
【図３】部分レジスト工程におけるマスキングの平面
図。FIG. 3 is a plan view of masking in a partial resist process.
【図４】実施例２の転写箔製造に続く製造工程を示す断
面図。FIG. 4 is a sectional view showing a manufacturing process that follows the manufacturing of the transfer foil of the second embodiment.
１ 銅箔 ２ ニッケル ３ レジスト ４ チップ実装用パッド部及び配線部のめっき銅 ４’ダイボンド用パッド部のめっき銅 ５ 電解または無電解ニッケル金めっき ５’無電解ニッケル金めっき ６ 半導体チップ ７ ダイボン材 ８ ワイヤボンディング ９ 封止材 １０ ソルダレジスト １１ ハンダボール 1 copper foil 2 nickel 3 resist 4 Plated copper for chip mounting pad and wiring 4'Die bond pad copper 5 Electrolytic or electroless nickel gold plating 5'electroless nickel gold plating 6 semiconductor chips 7 Daibon material 8 wire bonding 9 Sealant 10 Solder resist 11 solder balls
───────────────────────────────────────────────────── フロントページの続き (72)発明者 大畑 洋人 茨城県つくば市和台48 日立化成工業株式 会社筑波開発研究所内 ─────────────────────────────────────────────────── ─── Continued front page (72) Inventor Hiroshi Ohata 48 Wadai, Tsukuba, Ibaraki Prefecture Hitachi Chemical Co., Ltd. Company Tsukuba Development Laboratory
Claims (5)
持材のニッケル面に銅の配線パターンが形成されている
ことを特徴とする転写配線支持部材。1. A transfer wiring supporting member, wherein a copper wiring pattern is formed on a nickel surface of a supporting material made of a two-layer metal of copper foil and nickel.
樹脂封止された後に剥離されることを特徴とする請求項
１記載の転写配線支持部材。2. The transfer wiring supporting member according to claim 1, wherein the supporting material is peeled off after the semiconductor chip is mounted and sealed with resin.
箔が露出していることを特徴とする請求項１記載の転写
配線支持部材。3. The transfer wiring supporting member according to claim 1, wherein the copper foil in the gap between the copper wiring patterns is exposed.
線パターン相互間隙の露出した前記銅箔が粗化形状を有
することを特徴とする請求項３記載の転写配線支持部
材。4. The transfer wiring supporting member according to claim 3, wherein the copper wiring pattern and the copper foil in which the mutual gaps of the copper wiring patterns are exposed have a roughened shape.
脂封止された後に剥離されることを特徴とする請求項３
または４記載の転写配線支持部材。5. The copper foil is peeled off after a semiconductor chip is mounted and resin-sealed.
Alternatively, the transfer wiring supporting member according to item 4.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2003087870A JP4063119B2 (en) | 2003-03-27 | 2003-03-27 | Transfer wiring support member |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2003087870A JP4063119B2 (en) | 2003-03-27 | 2003-03-27 | Transfer wiring support member |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7401496A Division JP3879135B2 (en) | 1996-03-28 | 1996-03-28 | Transfer wiring support member and semiconductor package manufacturing method using the same |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2006245646A Division JP2007013204A (en) | 2006-09-11 | 2006-09-11 | Transferred wiring support member and semiconductor package manufacturing method using the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2003249595A true JP2003249595A (en) | 2003-09-05 |
| JP4063119B2 JP4063119B2 (en) | 2008-03-19 |
Family
ID=28672950
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2003087870A Expired - Lifetime JP4063119B2 (en) | 2003-03-27 | 2003-03-27 | Transfer wiring support member |
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| Country | Link |
|---|---|
| JP (1) | JP4063119B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP2072639A1 (en) * | 2007-12-12 | 2009-06-24 | Rohm and Haas Electronic Materials LLC | Method for adhesion promotion between the nickel and nickel alloy layer and another metal or a dielectric, such as in the manufacture of lead frames for semiconductor devices |
| JP2015164189A (en) * | 2014-02-13 | 2015-09-10 | 群成科技股▲分▼有限公司 | Electronic package, package carrier, and method of manufacturing both the electronic package and the package carrier |
-
2003
- 2003-03-27 JP JP2003087870A patent/JP4063119B2/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP2072639A1 (en) * | 2007-12-12 | 2009-06-24 | Rohm and Haas Electronic Materials LLC | Method for adhesion promotion between the nickel and nickel alloy layer and another metal or a dielectric, such as in the manufacture of lead frames for semiconductor devices |
| JP2015164189A (en) * | 2014-02-13 | 2015-09-10 | 群成科技股▲分▼有限公司 | Electronic package, package carrier, and method of manufacturing both the electronic package and the package carrier |
Also Published As
| Publication number | Publication date |
|---|---|
| JP4063119B2 (en) | 2008-03-19 |
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