JP2003249554A - Integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an integrated circuit which transmits clock signals with little skew and facilitates adjustment of buffers for driving clock wirings. <P>SOLUTION: A plurality of clock wirings 5a, 5b, 5c, 5d are developed radially, starting from one set meeting point 3 on a logical integrated circuit region 1 to transmit a clock signal to logic circuits 7 via the clock wirings 5a, 5b, 5c, 5d. A clock wiring 4, connected to the meeting point 3, has a buffer 6 outside the integrated circuit region 1. A propagation delay measuring circuit is connected to the clock wirings 5b, 5c and is composed of a combination of a first DELAY cell 8a with a monitor input/output part 2a and a combination of a second DELAY cell 8b with a monitor input/output part 2b. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit provided with clock wiring.

[0002]

2. Description of the Related Art In an integrated circuit having a clock-synchronous circuit configuration, a clock wiring pattern design is important. Conventionally known clock wiring systems include the clock tree system shown in FIG. 6 and the clock batch drive system (fixed system) shown in FIG.

In FIG. 6, reference numeral 21 denotes a logic circuit integrated area on a chip, and a large number of input / output sections 22 surround the area.
Are arranged. A large number of logic circuits 23 are integrated and arranged in the logic circuit integrated region 21. Here, a flip-flop circuit is given as an example of the logic circuit. A clock signal is transmitted to a large number of logic circuits 23 in a tree structure from a clock wiring trunk line (hereinafter referred to as “clock trunk line”) 24 through a clock wiring branch line (hereinafter referred to as “clock branch line”) 25. . Reference numeral 26 is a buffer provided in the clock trunk line 24.

When transmitting a clock signal, propagation delay is inevitably generated due to the resistance component and parasitic capacitance in the wiring. It suffices that the delays occur uniformly, but in the tree structure shown in FIG. 6, the wiring lengths from the clock trunk line 24 to the individual logic circuits 23 are unequal, and the delay amounts are unequal. That is, "skew" occurs. Skew causes problems such as incorrect timing. For this reason, the buffer 27 is inserted in each of the clock branch lines 25 to correct the skew.

However, if the buffer 27 for skew correction is inserted in a key portion as described above, it takes time to adjust the buffer, and the development time of the integrated circuit becomes long. This problem becomes more serious as the integrated structure becomes complicated.

In the collective clock driving system shown in FIG. 7, a matrix composed of the clock trunk lines 24 and the clock branch lines 25 is expanded in a plane, and each logic circuit 23 is connected to the nearest clock trunk line 24 or the clock branch line 25. is doing.
Even in this configuration, it is inevitable that the wiring length from the starting point of the clock trunk line 24 to the individual logic circuit 23 becomes unequal.

Japanese Patent Laid-Open No. 6-163536 proposes the following clock wiring system. That is, the wiring is formed in a planar shape so as to cover the input terminals, the distance of the redundant wiring to each input terminal is reduced, and the time difference of propagation until a signal reaches each input terminal is reduced.

In the above structure, a large amount of electrode material is required to form a wiring in a plane, and since there is a buffer inside the logic circuit integrated region, a relayout is necessary to adjust the buffer size. However, it is not a good idea in terms of cost.

In addition, in the above-mentioned conventional clock tree method, clock batch driving method, and the method described in Japanese Patent Laid-Open No. 6-163536, since a buffer is provided inside the integrated circuit, the buffer size after the integrated circuit is manufactured. If is found to be unsuitable, it is necessary to redesign the layout of the integrated circuit and remake the mask. This is costly and time consuming.

[0010]

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems of the conventional structure. It is possible to transmit a clock signal in a form with less skew and to easily adjust a buffer for driving a clock wiring. It is an object of the present invention to provide a simple integrated circuit.

[0011]

In order to achieve the above object, according to the present invention, a plurality of clock wirings are radially expanded from one gathering point and a clock signal is transmitted to a logic circuit through the clock wirings. did.

According to the above configuration, the clock signal can be transmitted to each logic circuit with the shortest wiring distance and with a small current loss.

Further, in the present invention, a buffer is provided outside the integrated circuit, and the buffer is connected to the collecting point.

According to the above arrangement, since the buffer is arranged outside the integrated circuit, adjustment can be performed after the layout of the integrated circuit.

Further, in the present invention, a propagation delay measuring circuit is connected to the clock wiring.

With the above arrangement, the buffer can be adjusted correctly by measuring the actual propagation delay.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described below with reference to FIG.
~ It demonstrates based on FIG.

In FIG. 1, reference numeral 1 denotes a logic circuit integrated area on a chip, and a large number of input / output units 2 are arranged so as to surround the logic circuit integrated area. The logic circuit integrated region 1 has a rectangular shape, and one corner of the logic circuit integrated region 1 becomes a collection point 3 of the clock wiring. The clock wiring 4 is drawn from outside the area surrounded by the input / output unit 2 toward the gathering point 3. Then, a plurality of clock wirings 5a, 5b,
5c and 5d are radially expanded.

For the clock wiring 4, a buffer 6 is provided on the substrate outside the integrated circuit. Clock wiring 5a, 5
As shown in FIG. 2, a logic circuit 7 such as a flip-flop circuit, a NAND circuit, and a NOR circuit is directly connected to b, 5c, and 5d without the input / output unit 2. The number of logic circuits 7 shared by the clock wirings 5a, 5b, 5c, and 5d should be as uniform as possible among the wirings.

Clock wiring 4 and clock wirings 5a, 5
b, 5c, and 5d have a wide width corresponding to a clock main line of a conventional structure in order to reduce resistance and allow a large current to flow and to suppress electromigration.

The wiring capacitance (delay value of wiring) of the clock wirings 5a, 5b, 5c and 5d is influenced by the signal transmission direction of the adjacent wiring. It is known that the wiring capacitance is small when signals are transmitted in the same direction, and the wiring capacitance is large when signals are transmitted in the opposite direction. Since the clock wirings 5a, 5b, 5c, and 5d are radially arranged, the signal transmission directions are not reversed between the adjacent wirings, and the wiring capacitance can be kept small.

The clock wirings 5a, 5b, 5c and 5d extend radially and there is no great difference in wiring length. However, since the logic circuit integrated area 1 is still rectangular, the clock wirings 5b and 5c extending in the diagonal direction of the rectangle are It is longer than the clock wirings 5a and 5d extending in the side direction of the rectangle. Therefore,
With respect to the longest clock wirings 5b and 5c, the first DELAY cell 8a is connected to the end of the clock wiring 5b and the second DELAY cell 8b is connected to the end of the clock wiring 5c. The clock wirings 5b and 5c have the same layout length,
The number of logic circuits 7 to be arranged is set to be the same. 1st DELAY
The outputs of the cell 8a and the second DELAY cell 8b are taken out from the monitor input / output unit 2a and the monitor input / output unit 2b. First
Combination of DELAY cell 8a and monitor input / output unit 2a,
Also, the combination of the second DELAY cell 8b and the monitor input / output unit 2b constitutes a propagation delay measuring circuit.

As seen in FIG. 3, the first DELAY cell 8
In a, 100 buffer cells 9 are connected in series, and in the second DELAY cell 8b, 200 buffer cells 9 are connected in series.

FIG. 4 shows a situation in which the waveforms output from the monitor input / output units 2a and 2b are delayed from the waveform of the reference clock. As is clear from FIG. 5, as an example, the delay value of the clock wiring 5b to which 100 buffer cells 9 are connected is 105 ns, and the delay value of the clock wiring 5c to which 200 buffer cells 9 are connected is Two
If it is 05 ns, it can be concluded that the propagation delay value in the wiring of the clock wiring having the same wiring length and serving the same number of logic circuits 3 is 5 ns.

In the above case, the buffer 6 is set to 5 ns as a guide.
The drive capacity of can be adjusted to the optimum value. The larger the drive capacity of the buffer 6, the more effective the delay prevention is. However, if a buffer having a larger drive capacity than necessary is selected, the power consumption becomes large. By measuring the propagation delay value in the wiring and providing a buffer having a drive capability that matches the propagation delay value, a buffer configuration in which the drive capability is not insufficient and the power consumption is not too large can be obtained.

Although the embodiment of the present invention has been described above, various other modifications can be made without departing from the scope of the invention.

[0027]

The present invention has the following effects.

In the present invention, a plurality of clock wirings are radially expanded from one gathering point, and the clock signal is transmitted to the logic circuit through the clock wirings. Moreover, the clock signal can be transmitted in a form with less current loss.

Further, according to the present invention, a buffer is provided outside the integrated circuit, and the buffer is connected to the gathering point. Since the integrated circuit and the buffer are arranged at different positions, the buffer should be adjusted after the layout of the integrated circuit. It can be carried out. The integrated circuit has a wiring resistance value of ± 20 to 30 in the manufacturing process, depending on the definition of the wiring rule.
It may fluctuate about%. Even if such a change occurs, it can be easily dealt with by adjusting the buffer.

Further, in the present invention, since the propagation delay measuring circuit is connected to the clock wiring, the buffer can be properly adjusted by measuring the actual propagation delay. There is no need to select a buffer that consumes more power than necessary.

[Brief description of drawings]

FIG. 1 is a schematic plan view showing an embodiment of an integrated circuit of the present invention.

FIG. 2 is a schematic plan view showing the relationship between clock wiring and a logic circuit.

[Figure 3] DELAY circuit configuration diagram

FIG. 4 is a comparison diagram of clock waveforms.

FIG. 5 is a graph showing the relationship between the number of buffer cells and the delay value.

FIG. 6 is a schematic plan view showing a conventional structure of an integrated circuit.

FIG. 7 is a schematic plan view showing another conventional structure of an integrated circuit.

[Explanation of symbols]

1 Logic circuit layout area 2 I / O section 2a, 2b Monitor input / output section 3 meeting points 4 clock wiring 5a, 5b, 5c, 5d Clock wiring 6 buffers 7 logic circuits 8a 1st DELAY cell 8b 2nd DELAY cell 9 buffer cells

Claims (3)

[Claims] 1. An integrated circuit characterized in that a plurality of clock wirings are radially expanded from one set point and a clock signal is transmitted to a logic circuit through the clock wirings. 2. A buffer is provided outside the integrated circuit, and the buffer is connected to the gathering point.
The integrated circuit according to. 3. The propagation delay measuring circuit is connected to the clock wiring.
The integrated circuit according to.