JP2003243623A - Memory cell array having ferroelectric capacitor and method of manufacturing the same, and ferroelectric memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a memory cell array with improved characteristics for ferroelectric capacitors and a method of manufacturing the same, and also to provide a ferroelectric memory device including the memory cell array. <P>SOLUTION: The memory cell array 100 is such that memory cells formed of the ferroelectric capacitors 20 are arranged in a matrix. The ferroelectric capacitor 20 includes lower electrodes 12, upper electrodes 16, and ferroelectric sections 14 disposed between the lower electrodes 12 and the upper electrodes 16. The ferroelectric sections 14 are disposed in regions where the lower electrodes 12 and the upper electrodes 16 cross one another. Between the ferroelectric sections 14 and the upper electrodes 16, intermediate electrodes 18 are disposed. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory cell array having a ferroelectric capacitor, and more particularly to a simple matrix type memory cell array having no cell transistor and using only a ferroelectric capacitor, and a method for manufacturing the same. The present invention relates to a ferroelectric memory device including a memory cell array.

[0002]

BACKGROUND OF THE INVENTION A simple matrix type memory cell array that does not have cell transistors and uses only ferroelectric capacitors has a very simple structure and can achieve a high degree of integration. Because you can
Its development is expected.

An object of the present invention is to provide a memory cell array having improved characteristics of a ferroelectric capacitor, a method of manufacturing the same,
Another object of the present invention is to provide a ferroelectric memory device including the memory cell array of the present invention.

[0004]

[Means for Solving the Problems] 1. Memory cell array In a memory cell array having a ferroelectric capacitor of the present invention, memory cells made of a ferroelectric capacitor are arranged in a matrix, and the ferroelectric capacitor has a lower electrode, an upper electrode, a lower electrode, and a lower electrode. A ferroelectric part provided between the upper electrode and the upper electrode, wherein the ferroelectric part is provided in an intersecting region of the lower electrode and the upper electrode, and the ferroelectric part and the upper electrode An intermediate electrode is provided between them.

According to the memory cell array of the present invention, the ferroelectric portion is provided in the intersection region of the lower electrode and the upper electrode. Therefore, the line of electric force is suppressed from protruding from the inside of the ferroelectric capacitor to the outside of the region of the ferroelectric capacitor. Therefore, as will be described later, the squareness of the hysteresis loop of the ferroelectric capacitor can be improved. As a result, according to the present invention, the characteristics of the ferroelectric capacitor can be improved.

The memory cell array of the present invention can take at least one of the following aspects.

(1) An insulating layer may be provided so as to cover at least a side surface of the lower electrode in the ferroelectric capacitor. As a result, it is possible to prevent a short circuit between the lower electrode and the upper electrode.

In this case, the insulating layer may be provided so as to cover side surfaces of the lower electrode, the ferroelectric layer and the intermediate electrode in the ferroelectric capacitor.

Further, in this case, the insulating layer may be provided under the upper electrode.

(2) At least a part of the insulating layer may be composed of a hydrogen barrier film. As a result, it is possible to prevent the ferroelectric portion from being reduced by hydrogen.

2. Method for Manufacturing Memory Cell Array A method for manufacturing a memory cell array according to the present invention is a method for manufacturing a memory cell array in which memory cells made of ferroelectric capacitors are arranged in a matrix, and includes the following steps. (A) a step of forming a first conductive layer on a substrate, (b)
Forming a ferroelectric layer on the first conductive layer;
(C) forming a second conductive layer on the ferroelectric layer, and (d) at least the ferroelectric layer and the second layer.
Patterning a conductive layer, (e) forming an insulating layer on the base so as to cover a laminate including the first conductive layer, the ferroelectric layer and the second conductive layer,
(F) removing the insulating layer until the upper surface of the second conductive layer is exposed, and (g) forming a third conductive layer having a predetermined pattern so as to partially overlap with the second conductive layer. Forming process.

According to the present invention, the second conductive layer is formed on the ferroelectric layer. Therefore, when the insulating layer is removed in the step (f), the ferroelectric layer is protected by the second conductive layer. Therefore, the structure of the surface of the ferroelectric layer is not disturbed, and deterioration of characteristics can be suppressed. That is, the damage to the capacitor can be suppressed.

A method of manufacturing a memory cell array according to the present invention is
The following modes can be adopted.

(1) The first conductive layer is formed in the step (d).
Can be patterned with. In this case, the first conductive layer, the ferroelectric layer and the second conductive layer can be collectively patterned. Further, since the ferroelectric layer is formed on the unpatterned first conductive layer, it is easy to form the ferroelectric layer.

(2) A step of patterning the first conductive layer may be included before the step (b).

(3) For the step (d), a step of forming a mask layer having a predetermined pattern on the second conductive layer is included, and in the step (f), the insulating layer and the The step of removing the mask layer may be included.

(4) The mask may be made of silicon nitride, silicon oxide or titanium nitride.

(5) After the step (g), the second conductive layer and the ferroelectric layer can be patterned. Thereby, the ferroelectric layer can be formed only in the intersecting region between the first conductive layer and the second conductive layer.

(6) The insulating layer may include a hydrogen barrier film.

3. Ferroelectric Memory Device The ferroelectric memory device of the present invention includes the memory cell array of the present invention.

[0021]

BEST MODE FOR CARRYING OUT THE INVENTION Preferred embodiments of the present invention will be described below with reference to the drawings.

1. First Embodiment 1.1 Device Structure FIG. 1 is a plan view schematically showing a ferroelectric memory device according to the first embodiment, and FIG. 2 is a line AA of FIG. FIG. 6 is a cross-sectional view schematically showing a part of the ferroelectric memory device along the line. FIG. 3 is a sectional view schematically showing a part of the ferroelectric memory device taken along the line BB of FIG. FIG. 4 is an enlarged schematic sectional view of the memory cell array in FIG. FIG. 5 is an enlarged schematic cross-sectional view of the memory cell array in FIG.

The ferroelectric memory device 100 of the present embodiment
0 has a memory cell array 100 and a peripheral circuit section 200. The memory cell array 100 and the peripheral circuit section 200 are formed in different layers. The peripheral circuit section 200 is formed in a region outside the memory cell array 100. Specifically, the peripheral circuit section formation region A200 is provided in a region outside the memory cell array formation region A100. In this example, the peripheral circuit section 200 is formed in the lower layer and the memory cell array 100 is formed in the upper layer. As a specific example of the peripheral circuit section 200,
It may be a Y gate, a sense amplifier, an input / output buffer, an X address decoder, a Y address decoder or an address buffer.

In the memory cell array 100, a lower electrode (word line) 12 for selecting a row and an upper electrode (bit line) 16 for selecting a column are arranged orthogonal to each other. That is, the lower electrodes 12 are arranged at a predetermined pitch along the X direction, and the upper electrodes 16 are arranged at a predetermined pitch along the Y direction orthogonal to the X direction. The lower electrode 12 may be a bit line and the upper electrode 16 may be a word line.

Memory cell array 10 according to the present embodiment
0 represents the first interlayer insulating layer 1 as shown in FIGS. 2 and 3.
It is provided above 0. The memory cell array 100 is
As shown in FIGS. 4 and 5, on the first interlayer insulating layer 10, a lower electrode 12, a ferroelectric portion 14 forming a ferroelectric capacitor, an intermediate electrode 18, and an upper electrode (upper electrode) 1 are formed.
6 are laminated and configured. The ferroelectric portion 14 and the intermediate electrode 18 are provided in the intersection region of the lower electrode 12 and the upper electrode 16. That is, in the intersection region of the lower electrode 12 and the upper electrode 16, the ferroelectric capacitor 2
A memory cell of 0s is formed.

As shown in FIG. 5, the ferroelectric capacitor 2
An insulating layer 70 is formed so as to cover at least the lower electrode 12 of 0. The insulating layer 70 is provided below the upper electrode 16 and between adjacent ferroelectric capacitors. By providing the insulating layer 70, a short circuit between the lower electrode 12 and the intermediate electrode 18 or the upper electrode 16 is prevented. The insulating layer 70 can have, for example, a laminated structure of the first hydrogen barrier film 40 having an insulating property and the first insulating layer 72. By forming the first hydrogen barrier film 40, reduction of the ferroelectric portion 14 of the ferroelectric capacitor 20 can be suppressed. It should be noted that the insulating layer 70 may be composed of only the insulating layer 72.

Further, as shown in FIGS. 4 and 5, the second hydrogen barrier film 4 is formed so as to cover the ferroelectric capacitor 20.
2 may be formed. By forming the second hydrogen barrier film 42, reduction of the ferroelectric portion 14 of the ferroelectric capacitor 20 can be suppressed.

Further, as shown in FIGS. 2 and 3, the first interlayer insulating layer 10 is formed so as to cover the memory cell array 100.
A first protective layer 36 is formed on the above. A third hydrogen barrier film 44 is formed on the first protective layer 36, if necessary. The third hydrogen barrier film 44 may be formed in the memory cell array region A100. That is,
First, second and third hydrogen barrier films 40, 42, 44
Can be configured not to be formed in the peripheral circuit area A200. As a result, the peripheral circuit portion A200 can be recovered by hydrogen by performing heat treatment in the subsequent process, and at the same time, reduction of the memory cell array 100 by hydrogen can be suppressed. Furthermore, the second
An insulating second protective layer 38 is formed on the first protective layer 36 so as to cover the wiring layer 40. By providing this third hydrogen barrier film 44, it is possible to suppress damage to the ferroelectric capacitor in the process of forming the second protective film 38.

The peripheral circuit section 200, as shown in FIG.
A first drive circuit 50 including various circuits for selectively writing or reading information to or from the memory cell, for example, for selectively controlling the lower electrode 12.
A second drive circuit 52 for selectively controlling the upper electrode 34, and a signal detection circuit (not shown) such as a sense amplifier.

The peripheral circuit section 200 also includes a MOS transistor 112 formed on a semiconductor substrate 110, as shown in FIG. The MOS transistor 112 includes a gate insulating layer 112a, a gate electrode 112b and a source / source electrode.
It has a drain region 112c. Each MOS transistor 112 is isolated by an element isolation region 114.
Semiconductor substrate 11 on which MOS transistor 112 is formed
A first interlayer insulating layer 10 is formed on the surface 0. The peripheral circuit section 200 and the memory cell array 100 are
It is electrically connected by the first wiring layer 40.

Next, an example of writing and reading operations in the ferroelectric memory device 1000 of this embodiment will be described.

First, in the read operation, the read voltage "V ₀ " is applied to the capacitor of the selected cell. This also serves as a write operation of "0". At this time, the current flowing through the selected bit line or the potential when the bit line is set to high impedance is read by the sense amplifier. At this time, a predetermined voltage is applied to the capacitors of the non-selected cells in order to prevent crosstalk during reading.

In the write operation, in the case of writing " ₁ ", the voltage "-V ₀ " is applied to the capacitor of the selected cell. In the case of writing "0", a voltage that does not invert the polarization of the selected cell is applied to the capacitor of the selected cell, and the "0" state written during the read operation is held. At this time, a predetermined voltage is applied to the capacitors of the non-selected cells in order to prevent crosstalk during writing.

1.2 Functions and Effects Below, the ferroelectric memory device 1000 according to the present embodiment will be described.
The action and effect of will be described.

The ferroelectric portion 14 is formed in the intersection region of the upper electrode 12 and the lower electrode 16. Therefore, it is possible to prevent the lines of electric force from protruding from the capacitor to the outside. As a result, the region of the ferroelectric portion 14 to which the weak electric field is applied when the voltage is applied is removed. Therefore, the squareness of the hysteresis loop can be improved. That is, the hysteresis loop can be approximated to a square. As a result, according to the ferroelectric memory device 1000 of the present embodiment, the ferroelectric capacitor 2
The operating characteristic of 0 can be improved.

2. Second Embodiment 2.1 Process Next, an example of a method of manufacturing the above-mentioned ferroelectric memory device will be described. 6 to 14 show a ferroelectric memory device 1
000 is a cross-sectional view schematically showing the manufacturing process. In addition,
7 to 14 are sectional views showing only the memory cell array region.

As shown in FIG. 6, the peripheral circuit 200 is formed by using a known LSI process. Specifically, the MOS transistor 112 is formed on the semiconductor substrate 110. For example, a device isolation region 114 is formed in a predetermined region on the semiconductor substrate 110 by using a trench isolation method, a LOCOS method or the like.
Then, the gate insulating layer 112a and the gate electrode 112b are formed, and then the semiconductor substrate 110 is doped with impurities to form the source / drain regions 112c. In this way, the peripheral circuit section 200 including various circuits such as the drive circuits 50 and 52 and the signal detection circuit 54.
Is formed. Then, the first interlayer insulating layer 10 is formed by a known method.

Next, the memory cell array region A100 is formed on the first interlayer insulating layer 10. Hereinafter, FIG. 7 to FIG.
A method of forming the memory cell array 100 will be described with reference to FIG.

First, as shown in FIG. 7, the first interlayer insulating layer is formed.
10 on top of the first conductive layer 12a for the lower electrode 12
Form. The material of the first conductive layer 12a is a ferroelectric material.
There is no particular limitation as long as it can be an electrode of a capacitor.
Absent. The material of the first conductive layer 12a is, for example, I
r, IrO_x, Pt, RuO_x, SrRuO_x, LaSr
CoO_xCan be mentioned. In addition, the first conductive layer 12
For a, use a single layer or a laminate of a plurality of layers.
You can For example, if TiO _xEtc.
An adhesion layer can also be formed. Shape of the first conductive layer 12a
As the forming method, sputtering, vacuum deposition, CVD, etc.
Methods are available.

Next, the ferroelectric layer 14a for the ferroelectric portion 14 is formed on the first conductive layer 12a. As a material of the ferroelectric layer 14a, any composition can be applied as long as it exhibits ferroelectricity and can be used as a capacitor insulating layer. Examples of such a ferroelectric include PZT (PbZr _z Ti _1-z O ₃ ), SBT (Sr
Bi ₂ Ta ₂ O ₉ ), and materials obtained by adding a metal such as niobium, nickel or magnesium to these materials can be used. The ferroelectric layer 14a may be formed by, for example, a spin coating method using a sol-gel material or a MOD material, a dipping method, a sputtering method, an M method.
The OCVD method and the laser ablation method can be mentioned.

Next, a second conductive layer 18a for the intermediate electrode 18 is formed on the ferroelectric layer 14a. As the material and forming method of the second conductive layer 18a, the same material as that of the first conductive layer 12a can be applied.

Next, a mask layer 60 is formed on the entire surface, and the mask layer 60 having a predetermined pattern is patterned by lithography and etching. That is, the mask layer 60 is formed on the region where the lower electrode 12 is to be formed. The material of the mask layer 60 is the second conductive layer 18a,
The material is not particularly limited as long as it is a material that can function as a mask when etching the ferroelectric layer 14a and the first conductive layer 12a, and examples thereof include silicon nitride, silicon oxide, and titanium nitride. The mask layer 60 can be formed by, for example, a CVD method.

Next, as shown in FIG. 8, the second conductive layer 18a, the ferroelectric layer 14a and the first conductive layer 12a are etched using the mask layer 60 as a mask to etch the second conductive layer 18a.
a, the ferroelectric layer 14a and the first conductive layer 12a are patterned. The lower electrode 12 having a predetermined pattern is formed by patterning the first conductive layer 12a. Examples of the etching method include RIE, ion milling, high density plasma etching such as ICP (Inductively Coupled Plasma), and the like.

Next, if necessary, as shown in FIG.
The first hydrogen barrier film 40 is formed on the entire surface. The material of the first hydrogen barrier film 40 is not particularly limited as long as it is a material that can prevent the ferroelectric layer 14a from being reduced by hydrogen, and examples thereof include aluminum oxide, titanium oxide, and magnesium oxide. it can. As the method of forming the first hydrogen barrier film 40, sputtering method, CVD
Method and laser ablation method.

Next, the first insulating layer 72 is formed on the entire surface.
The material of the first insulating layer 72 is not particularly limited as long as it can be the same etching rate as that of the mask layer in the later etching back step of the first insulating layer, and is made of, for example, silicon oxide or aluminum oxide. . First insulating layer 72
As a method of forming the, for example, a CVD method can be cited. The first insulating layer 72 is formed so as to fill the space between the lower electrode 12, the ferroelectric layer 14a, the second conductive layer 18a, and the laminated body of the mask layer 60 (hereinafter referred to as “laminated body”).

Next, as shown in FIG. 10, the first insulating layer 7
A resist layer R1 is formed on top of 2. Resist layer R1
Is formed so that its upper surface is flat. When the first insulating layer 72 having a flat upper surface is formed by using the coating method, the resist layer R1 may not be formed. Specifically, when the first insulating layer 72 is made of an SOG (Spin On Glass) layer, the resist layer R1 may not be formed.

Next, as shown in FIG. 11, the first insulating layer 7
2 and the resist layer R1 are etched back. Simultaneously with this etch back, the mask layer 60 is removed to expose the upper surface of the second conductive layer 18a. A known method can be used as the etch back method. During this etch back,
The insulating layer 70 including the first insulating layer 72 and the first hydrogen barrier film 40 is formed so as to cover at least the sidewall of the lower electrode 12.

Next, as shown in FIG.
The conductive layer 16a is deposited. The material and forming method of the third conductive layer 16 can be the same as, for example, the material and forming method of the first conductive layer 12a.

Next, a resist layer R2 having a predetermined pattern is formed on the third conductive layer 16a. The resist layer R2 is formed on the region where the upper electrode 16 is to be formed.

Next, using the resist layer R2 as a mask, the third conductive layer 16a, the second conductive layer 18a, and the ferroelectric layer 14 are formed.
a, the first insulating layer 72 and the first hydrogen barrier film 40 are etched. Thus, the upper electrode 16 is formed by patterning the third conductive layer 16a. Also,
By patterning the second conductive layer 18a and the ferroelectric layer 14a, the intermediate electrode layer 18 and the ferroelectric portion 14 are formed in the intersection region between the upper electrode 16 and the lower electrode 12. In addition, the first insulating layer 72 and the first hydrogen barrier film 40 are left under the upper electrode 16 other than the intersection region of the upper electrode 16 and the lower electrode 12. Thus, the memory cell array 100 is formed.

Next, as shown in FIGS. 1 and 14, if necessary, a second hydrogen barrier film 42 is formed on the memory cell array 100. As the material and forming method of the second hydrogen barrier film 42, those described for the first hydrogen barrier film 40 can be applied.

Next, the first protective layer 36 is formed on the second hydrogen barrier film 42 by a known method. Next, the 1st protective layer 36 is planarized as needed. Next, on the first protective layer, if necessary, the memory cell array region A1
00, the third hydrogen barrier film 44 is formed. Then, the second protective layer 36 and the third hydrogen barrier film 44 are formed on the second protective layer 36.
The protective layer 38 is formed.

2.2 Functions and Effects The functions and effects of the method of manufacturing the ferroelectric memory device according to this embodiment will be described below.

1) In the present embodiment, the second conductive layer 18a is formed on the ferroelectric layer 14a. Therefore, in the etch back process of the first insulating layer 72 and the mask layer 60, the ferroelectric layer 14a becomes the second conductive layer 18a.
The ferroelectric layer 14a does not come into contact with the etchant because it is covered with. Therefore, the structure of the surface of the ferroelectric layer 14a is not disturbed, and the deterioration of the characteristics can be suppressed.
That is, the damage to the capacitor can be suppressed.

2) The ferroelectric layer 14a is formed on the first conductive layer 12a before patterning. This allows
Since the ferroelectric layer 14a can be formed on the flat first conductive layer 12a, it is easy to form the ferroelectric layer 14a and the degree of freedom of the ferroelectric film forming method is increased.

3) Generally, it is necessary to control the etching so that a fence made of a reaction product does not occur on the side wall of the mask when the conductive layer or the ferroelectric layer constituting the ferroelectric capacitor is etched. . For example, if the substrate temperature is 3
It is necessary to carry out etching while maintaining a high temperature of about 00 ° C. or to carry out etching so that the cross section has a tapered shape.

However, in the present embodiment, the mask layer 60 is used as a mask for the first conductive layer 12a and the ferroelectric layer 1.
4a and the second conductive layer 18a are etched. Then, the mask layer 60 is removed in the etch back process of the first insulating layer 72. When removing the mask layer 60,
Even if the side wall of the mask layer 60 has a fence,
The fence will be removed. Therefore, the second
When the conductive layer 18a and the like are etched, even if etching is performed so that a fence is formed, the generated fence is removed, so that the problem caused by the fence does not occur. Therefore, it is not necessary to etch the second conductive layer 18a or the like so that the cross section has a tapered shape so that a fence is not formed, and thus a laminate having a cross-sectional shape close to vertical can be formed. Moreover, since it is not necessary to keep the substrate at a high temperature during etching, the second conductive layer 18a and the like can be etched by a normal etching apparatus.

4) Using the mask layer 60, the second conductive layer 1
8a, the ferroelectric layer 14a and the first conductive layer 12a are etched. Further, since the selection ratio between the second conductive layer 18a and the ferroelectric layer 14a is larger than that of the resist, the mask layer can be made thin, so that the mask size can be easily controlled. Since there is no receding during etching like the resist layer, it is possible to perform fine processing to a pattern width of 0.35 μm or less.

3. Modification 3.1 First Modification The first modification is the first conductive layer 12a and the ferroelectric layer 14a.
And a modified example of the method for forming the first insulating layer 72 filling the space between the stacked bodies of the second conductive layer 18a.

First, as shown in FIG. 17, the surface of the first interlayer insulating layer 10 including the laminated body is surface-treated. In this surface treatment, the surface of the first interlayer insulating layer 10 including the laminated body is
This is performed so as to have an affinity with the material liquid (for example, mist) of the insulating layer 72. Examples of the surface treatment method include the following methods.

A surface modification layer 80 is formed on the entire surface of the first interlayer insulating layer 10. The surface modification layer 80 has an affinity with the material liquid (mist) of the first insulating layer 72.

The material of the surface modification layer 80 is the first insulating layer 72.
There is no particular limitation as long as it is a material having an affinity with the material liquid (mist), and, for example, hexamethyldisilazane, tetrahydrafuran, methanol, methyl ethyl ketone and the like can be used.

The surface modification layer 80 may be formed by a method using a liquid phase such as a spin coating method, a dipping method and a mist deposition method.

Next, a first insulating layer 72 is formed between the stacked bodies by a process that does not generate hydrogen, as shown in FIG. Specifically, the first insulating layer 7 is formed as follows.
2 can be formed.

The material liquid (mist) for the first insulating layer 72 is first
It is applied on the interlayer insulating layer 10. Since the surface modification layer 80 is formed on the surface of the first interlayer insulating layer 10 including the laminated body, the wettability between the material liquid of the first insulating layer 72 and the first interlayer insulating layer 10 is enhanced, and the mutual mutual effect of the laminated body is improved. The material liquid of the first insulating layer 72 easily flows in between. The method for depositing the material liquid for the first insulating layer 72 is not particularly limited, and may be, for example, LSMCD (Li
quid Source Mist Chemical Deposition) method. According to the LSMCD method, the material liquid of the first insulating layer 72 is likely to flow between the stacked bodies. As a material liquid for the first insulating layer 72, a liquid raw material of silicon oxide can be cited. Next, the material liquid for the first insulating layer 72 is heat-treated to form the first insulating layer.

According to this modification, the following operational effects can be obtained.

1) The insulating layer is formed by a process that does not generate hydrogen. Specifically, the first insulating layer 72
The material liquid (mist) is applied onto the first interlayer insulating layer 10 and heat-treated to form the insulating layer. Therefore, reduction of the ferroelectric layer 14a can be suppressed.

2) Further, surface treatment is performed so that the surface of the first interlayer insulating layer 10 and the material liquid of the first insulating layer have an affinity. Therefore, the material liquid of the first insulating layer can be easily flowed between the stacked bodies.

In this modification, the surface treatment process may be omitted. The first hydrogen barrier layer 40 is formed on the surfaces of the first interlayer insulating layer 10 and the ferroelectric capacitor 20.
The present manufacturing method may be applied in the state where is formed.

3.2 Second Modification 1) In the present embodiment, the mask layer 60 is used as a mask to form the second conductive layer 18a, the ferroelectric layer 14a and the first layer.
The conductive layer 12a was etched. However, the present invention is not limited to this, and without forming the mask layer 60, the second conductive layer 18a, the ferroelectric layer 14a, and the first conductive layer 18a are formed using the resist layer as a mask.
The conductive layer 12a may be etched.

2) The planarization of the first insulating layer 72 can be performed by the CMP method.

3) The insulating layer 70 is at least the lower electrode 1.
If the insulating layer 70 covers the second insulating layer 70, the insulating layer 70 in the central portion between the laminated bodies as shown in FIG. 15 may be completely removed. As shown in FIG. Of the first conductive layer 12 is lower than the upper surface of the second conductive layer 18a.
It may be higher than the upper surface of a.

4) In the above embodiment, the second conductive layer 18a, the ferroelectric layer 14a, and the first conductive layer 12a are collectively patterned. However, the present invention is not limited to this, and the ferroelectric layer 14a and the first conductive layer 12a may be formed after the first conductive layer 12a is patterned.

5) The peripheral circuit section 200 may be provided below the memory cell array.

4. Experimental Example It was examined how the hysteresis loops differ between the example and the comparative example. FIG. 18 is a diagram showing a hysteresis loop according to the example. FIG. 19 is a diagram showing a hysteresis loop according to a comparative example.

In the embodiment, the structure shown in FIGS. 2 to 5 is adopted as the structure of the memory cell array. In addition, in the examples, the hysteresis loops with and without the formation of the first hydrogen barrier film (aluminum oxide film) 40 shown in FIGS. In the comparative example, the memory cell array has a structure in which a continuous ferroelectric layer is formed on a base body including a lower electrode, and an upper electrode is formed on the ferroelectric layer.

As shown in FIGS. 18 and 19, according to the example, it is found that the tangent slope of the hysteresis loop at the polarization value of 0 is larger than that of the comparative example. Therefore, it can be said that the example has improved squareness as compared with the comparative example.

Further, it can be seen that the absolute value of the Pr (residual polarization) value is increased by forming the second hydrogen barrier film.

The present invention is not limited to the above-mentioned embodiments, and various modifications can be made within the scope of the present invention.

[Brief description of drawings]

FIG. 1 is a plan view schematically showing a ferroelectric memory device according to a first embodiment.

FIG. 2 is a cross-sectional view schematically showing a part of the ferroelectric memory device taken along the line AA of FIG.

FIG. 3 is a cross-sectional view schematically showing a part of the ferroelectric memory device taken along the line BB of FIG.

FIG. 4 is an enlarged schematic cross-sectional view of the memory cell array in FIG.

5 is an enlarged schematic cross-sectional view of the memory cell array in FIG.

FIG. 6 is a cross-sectional view schematically showing the manufacturing process of the ferroelectric memory device.

FIG. 7 is a cross-sectional view schematically showing the manufacturing process of the ferroelectric memory device.

FIG. 8 is a cross-sectional view schematically showing the manufacturing process of the ferroelectric memory device.

FIG. 9 is a cross-sectional view schematically showing the manufacturing process of the ferroelectric memory device.

FIG. 10 is a cross-sectional view schematically showing the manufacturing process of the ferroelectric memory device.

FIG. 11 is a cross-sectional view schematically showing the manufacturing process of the ferroelectric memory device.

FIG. 12 is a cross-sectional view schematically showing the manufacturing process of the ferroelectric memory device.

FIG. 13 is a cross-sectional view schematically showing the manufacturing process of the ferroelectric memory device.

FIG. 14 is a cross-sectional view schematically showing the manufacturing process of the ferroelectric memory device.

FIG. 15 is a cross-sectional view schematically showing a modification of the second embodiment.

FIG. 16 is a cross-sectional view schematically showing a modification of the second embodiment.

FIG. 17 is a cross-sectional view schematically showing a main part of a manufacturing process according to a first modification.

FIG. 18 is a diagram showing a hysteresis loop according to an example.

FIG. 19 is a diagram showing a hysteresis loop according to a comparative example.

[Explanation of symbols]

10 First interlayer insulating layer 12 Lower electrode 14 Ferroelectric part 16 Upper electrode 18 Intermediate electrode layer 36 First protective layer 38 Second protective layer 40 First hydrogen barrier film 42 Second hydrogen barrier film 44 Third Hydrogen Barrier Film 50 First drive circuit 52 Second drive circuit 60 mask layer 70 Insulation layer 72 First insulating layer 80 Surface modification layer 90 precursor layer 92 Charge layer 100 memory cell array 110 Semiconductor substrate 112 MOS transistor 112a gate insulating layer 112b gate electrode 112c Source / drain region 114 element isolation region 200 peripheral circuits 1000 Ferroelectric memory device

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Masao Nakayama             Seiko, 3-3-3 Yamato, Suwa City, Nagano Prefecture             -In Epson Corporation (72) Inventor Tatsuo Sawasaki             Seiko, 3-3-3 Yamato, Suwa City, Nagano Prefecture             -In Epson Corporation (72) Inventor Hiroaki Tamura             Seiko, 3-3-3 Yamato, Suwa City, Nagano Prefecture             -In Epson Corporation F-term (reference) 5F083 FR00 FR01 JA02 JA15 JA17                       JA19 JA38 JA40 JA42 JA43                       JA44 LA12 LA16 PR03 PR23                       PR39

Claims (21)

[Claims] 1. Memory cells comprising ferroelectric capacitors are arranged in a matrix, wherein the ferroelectric capacitors include a lower electrode, an upper electrode, and
A ferroelectric part provided between the lower electrode and the upper electrode, wherein the ferroelectric part is provided in an intersecting region between the lower electrode and the upper electrode, and the ferroelectric part A memory cell array having a ferroelectric capacitor, wherein an intermediate electrode is provided between the upper electrode and the upper electrode. 2. The memory cell array according to claim 1, wherein an insulating layer is provided so as to cover at least a side surface of the lower electrode in the ferroelectric capacitor. 3. The ferroelectric capacitor according to claim 2, wherein the insulating layer is provided so as to cover side surfaces of the lower electrode, the ferroelectric layer and the intermediate electrode in the ferroelectric capacitor. A memory cell array having. 4. The memory cell array according to claim 2, wherein the insulating layer has a ferroelectric capacitor provided under the upper electrode. 5. The memory cell array according to claim 1, wherein at least a part of the insulating layer is composed of a hydrogen barrier film and has a ferroelectric capacitor. 6. The ferroelectric memory device according to claim 1, wherein a hydrogen barrier film is formed at a position above at least the plurality of ferroelectric capacitors to cover the plurality of ferroelectric capacitors. 7. The method according to claim 6, further comprising a peripheral circuit section for selectively writing or reading information to or from the memory cell, wherein the hydrogen barrier film is provided on the peripheral circuit section. An unformed ferroelectric memory device. 8. The interlayer insulating layer provided on the memory cell array according to claim 6, wherein the hydrogen barrier film is provided between the interlayer insulating layer and the memory cell array. Ferroelectric memory device. 9. The ferroelectric memory device according to claim 6, wherein the hydrogen barrier film is provided on the interlayer insulating layer. 10. The ferroelectric memory device according to claim 6, wherein the hydrogen barrier film functions as an interlayer insulating layer. 11. A method of manufacturing a memory cell array in which memory cells each composed of a ferroelectric capacitor are arranged in a matrix, the method including the steps of: (A) a step of forming a first conductive layer on a substrate, (b)
Forming a ferroelectric layer on the first conductive layer;
(C) forming a second conductive layer on the ferroelectric layer, and (d) at least the ferroelectric layer and the second layer.
Patterning a conductive layer, (e) forming an insulating layer on the base so as to cover a laminate including the first conductive layer, the ferroelectric layer and the second conductive layer,
(F) removing the insulating layer until the upper surface of the second conductive layer is exposed, and (g) forming a third conductive layer having a predetermined pattern so as to partially overlap with the second conductive layer. Forming process. 12. The method of manufacturing a memory cell array according to claim 11, wherein the first conductive layer is patterned in the step (d). 13. The method of manufacturing a memory cell array according to claim 11, including a step of patterning the first conductive layer before the step (b). 14. The method of manufacturing a ferroelectric memory according to claim 11, including the step of forming an insulating layer by a method that does not generate hydrogen in the manufacturing step (e). 15. The method of manufacturing a ferroelectric memory according to claim 14, wherein the step of forming the insulating layer is performed by an LSMCD method. 16. The method according to claim 11, further comprising the step of forming a mask layer having a predetermined pattern on the second conductive layer for the step (d), and in the step (f), A method of manufacturing a memory cell array, comprising: removing an insulating layer and the mask layer. 17. The method of manufacturing a memory cell array according to claim 16, wherein the mask layer is made of any one of silicon nitride, silicon oxide, and titanium nitride. 18. The method of manufacturing a memory cell array according to claim 16, wherein the mask layer is made of a material that can have substantially the same etching rate as the insulating layer. 19. The method of manufacturing a memory cell array according to claim 11, wherein after the step (g), the second conductive layer and the ferroelectric layer are patterned. 20. The method of manufacturing a memory cell array according to claim 11, wherein the insulating layer includes a hydrogen barrier film. 21. A ferroelectric memory device including the memory cell array according to claim 1.