JP2003243552A - Package for accommodating semiconductor device and semiconductor device - Google Patents

Package for accommodating semiconductor device and semiconductor device

Info

Publication number
JP2003243552A
JP2003243552A JP2002044376A JP2002044376A JP2003243552A JP 2003243552 A JP2003243552 A JP 2003243552A JP 2002044376 A JP2002044376 A JP 2002044376A JP 2002044376 A JP2002044376 A JP 2002044376A JP 2003243552 A JP2003243552 A JP 2003243552A
Authority
JP
Japan
Prior art keywords
lead terminal
semiconductor element
package
base body
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2002044376A
Other languages
Japanese (ja)
Inventor
Takahiro Kihara
隆裕 木原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP2002044376A priority Critical patent/JP2003243552A/en
Publication of JP2003243552A publication Critical patent/JP2003243552A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item

Landscapes

  • Semiconductor Lasers (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a package for semiconductor device accommodation that can input and output a high-frequency signal having a high-frequency band of approximately 2 to 25 GHz with low loss. <P>SOLUTION: The package has a substrate 1 composed of an insulating material where a mounting section for mounting a semiconductor device 2 on the bottom surface of a recess 1a on an upper surface is provided and is set to be a nearly rectangular parallelepiped, a metallized layer 1c formed at the outer periphery of the lower surface of the substrate 1, and a lead terminal 5 that comprises an upper end joined to the metallized layer 1c, a middle section 5a slantingly extending from the upper end to a lower portion outside the substrate 1, and a lower end nearly in parallel with the upper end. In the lead terminal 5, the upper end and the middle section 5a are provided inside of an extended surface on the side of the substrate 1. <P>COPYRIGHT: (C)2003,JPO

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、高周波信号で作動
する半導体素子を収納するための半導体素子収納用パッ
ケージおよび半導体装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor element housing package for housing a semiconductor element that operates with a high frequency signal, and a semiconductor device.

【0002】[0002]

【従来の技術】従来の半導体素子収納用パッケージ(以
下、半導体パッケージともいう)を図3に断面図で示
す。この半導体パッケージは、上面に凹部101aを有す
るとともに凹部101aの底面に半導体素子102を載置する
載置部を有する絶縁材料から成る略直方体の基体101
と、基体101の下面の外周部に形成されたリード端子接
続用の第二のメタライズ層101cと、第二のメタライズ
層101cに接合された上端部および上端部から基体101の
外側下方に傾斜するように延設された中間部105aなら
びに上端部に略平行な下端部から成るリード端子105と
を具備している。基体101の上面には、蓋体104をシーム
溶接するための金属製のシールリング103が接合されて
いる。なお、リード端子105の中間部(傾斜部)105aは
基体101の側面の延長面から外側に位置している。
2. Description of the Related Art A conventional semiconductor element housing package (hereinafter, also referred to as a semiconductor package) is shown in a sectional view in FIG. This semiconductor package is a substantially rectangular parallelepiped base 101 made of an insulating material having a recess 101a on the upper surface and a mounting portion for mounting the semiconductor element 102 on the bottom of the recess 101a.
And a second metallization layer 101c for connecting lead terminals formed on the outer peripheral portion of the lower surface of the base body 101, an upper end portion joined to the second metallization layer 101c, and an inclination downward to the outside of the base body 101 from the upper end portion. Thus, there is provided the intermediate portion 105a extended and the lead terminal 105 having a lower end portion substantially parallel to the upper end portion. A metal seal ring 103 for seam-welding the lid 104 is joined to the upper surface of the base body 101. The intermediate portion (inclined portion) 105 a of the lead terminal 105 is located outside from the extended surface of the side surface of the base body 101.

【0003】なお、第二のメタライズ層101cは貫通導
体101dを介して、凹部101aに形成された第一のメタラ
イズ層101bに電気的に接続され、第一のメタライズ層10
1bと半導体素子102とがボンディングワイヤ106により電
気的に接続されている。リード端子105を外部電気回路
基板107の線路導体(図示せず)に接続させ、リード端
子105に高周波信号を入出力させることによって、半導
体素子102と外部電気回路基板107との間で高周波信号の
伝送が可能となる。
The second metallization layer 101c is electrically connected to the first metallization layer 101b formed in the recess 101a through the through conductor 101d, and the first metallization layer 10c is formed.
1b and the semiconductor element 102 are electrically connected by a bonding wire 106. By connecting the lead terminal 105 to a line conductor (not shown) of the external electric circuit board 107 and inputting / outputting a high frequency signal to / from the lead terminal 105, a high frequency signal between the semiconductor element 102 and the external electric circuit board 107 is transmitted. Transmission becomes possible.

【0004】また、リード端子105が折り曲げられて傾
斜した中間部105aを有することにより、リード端子105
を介して半導体パッケージを外部電気回路基板107に実
装しても、基体101と外部電気回路基板107との熱膨張差
を中間部105aが吸収し、基体101に外部電気回路基板107
との熱膨張差による大きな応力が加わるのを防止でき
る。
Further, since the lead terminal 105 has the intermediate portion 105a which is bent and inclined, the lead terminal 105
Even when the semiconductor package is mounted on the external electric circuit board 107 via the intermediate circuit 105a, the intermediate portion 105a absorbs the difference in thermal expansion between the base body 101 and the external electric circuit board 107, and the base body 101 is mounted on the external electric circuit board 107.
It is possible to prevent a large stress from being applied due to a difference in thermal expansion between the two.

【0005】[0005]

【発明が解決しようとする課題】しかしながら、2〜25
GHz程度の高周波帯域の高周波信号を半導体パッケー
ジに入出力させる場合、中間部105aのインダクタンス
に加えて第二のメタライズ層101cの長さの分だけ抵抗
が増加するため、これらの部分でインピーダンスを整合
させることが困難になり、中間部105aおよび第二のメ
タライズ層101cで高周波信号の反射損失や透過損失が
大きくなるという問題点があった。
[Problems to be Solved by the Invention] However, 2 to 25
When a high frequency signal in the high frequency band of about GHz is input to or output from the semiconductor package, the resistance increases by the length of the second metallization layer 101c in addition to the inductance of the intermediate portion 105a, so that impedance is matched at these portions. However, there is a problem in that the reflection loss and the transmission loss of the high frequency signal increase in the intermediate portion 105a and the second metallization layer 101c.

【0006】従って、本発明は上記従来の問題点に鑑み
完成されたものであり、その目的は、2〜25GHz程度
の高周波帯域の高周波信号を低損失で入出力できる半導
体パッケージを提供することにある。
Therefore, the present invention has been completed in view of the above conventional problems, and an object thereof is to provide a semiconductor package capable of inputting and outputting a high frequency signal in a high frequency band of about 2 to 25 GHz with low loss. is there.

【0007】[0007]

【課題を解決するための手段】本発明の半導体素子収納
用パッケージは、上面に形成された凹部の底面に半導体
素子を載置する載置部が設けられている絶縁材料から成
る略直方体の基体と、該基体の下面の外周部に形成され
たメタライズ層と、該メタライズ層に接合された上端部
および該上端部から前記基体の外側下方に傾斜するよう
に延設された中間部ならびに前記上端部に略平行な下端
部から成るリード端子とを具備した半導体素子収納用パ
ッケージにおいて、前記リード端子は、前記上端部およ
び前記中間部が前記基体の側面の延長面より内側に設け
られていることを特徴とする。
A semiconductor element housing package of the present invention is a substantially rectangular parallelepiped base body made of an insulating material in which a mounting portion for mounting a semiconductor element is provided on the bottom surface of a recess formed on the upper surface. A metallization layer formed on the outer peripheral portion of the lower surface of the base, an upper end joined to the metallization layer, an intermediate part extending from the upper end so as to incline downward to the outside of the base, and the upper end. In a package for housing a semiconductor element, comprising: a lead terminal having a lower end portion substantially parallel to the portion, the lead terminal has the upper end portion and the intermediate portion provided inside an extension surface of a side surface of the base body. Is characterized by.

【0008】本発明の半導体素子収納用パッケージは、
上記の構成により、中間部がメタライズ層の下方に位置
していることから、中間部とメタライズ層との間に電気
的な容量成分が生じ、この容量成分が中間部のインダク
タンス成分によるインピーダンスの増加を打ち消すよう
に作用してインピーダンスのずれが解消される。また、
リード端子の上端部はメタライズ層の内周側に接合され
るので、メタライズ層の長さによる抵抗を小さくするこ
とができる。その結果、インピーダンスが整合されて、
2〜25GHz程度の高周波帯域の高周波信号を半導体素
子収納用パッケージに入出力させても、反射損失や透過
損失を小さくして効率よく伝送させることができる。従
って、2〜25GHz程度の高周波帯域で作動する半導体
素子を問題なく収納することが可能となる。
The package for housing a semiconductor device of the present invention is
With the above configuration, since the intermediate portion is located below the metallized layer, an electrical capacitance component is generated between the intermediate portion and the metallized layer, and this capacitance component increases the impedance due to the inductance component of the intermediate portion. The effect of canceling out is to eliminate the impedance deviation. Also,
Since the upper ends of the lead terminals are joined to the inner circumference side of the metallized layer, the resistance due to the length of the metallized layer can be reduced. As a result, the impedance is matched,
Even if a high frequency signal in a high frequency band of about 2 to 25 GHz is input to and output from the semiconductor element housing package, it is possible to reduce reflection loss and transmission loss and efficiently transmit. Therefore, it is possible to accommodate a semiconductor element operating in a high frequency band of about 2 to 25 GHz without any problem.

【0009】また、リード端子が折り曲げられて傾斜し
た中間部を有することにより、リード端子を介して半導
体素子収納用パッケージを外部電気回路基板に実装する
際に基体と外部電気回路基板との間で熱膨張差が生じて
も、熱膨張差を中間部が吸収するため、基体に外部電気
回路基板との熱膨張差による大きな応力が加わるのを防
止できる。
Further, since the lead terminal has the intermediate portion which is bent and inclined, when the semiconductor element housing package is mounted on the external electric circuit board via the lead terminal, it is provided between the base body and the external electric circuit board. Even if there is a difference in thermal expansion, the intermediate portion absorbs the difference in thermal expansion, so that it is possible to prevent a large stress from being applied to the base body due to the difference in thermal expansion from the external electric circuit board.

【0010】本発明の半導体装置は、上記本発明の半導
体素子収納用パッケージと、前記載置部に載置固定され
るとともに前記メタライズ層を介して前記リード端子に
電気的に接続された半導体素子と、前記基体の上面に接
合された蓋体とを具備したことを特徴とする。
A semiconductor device according to the present invention is a semiconductor device which is mounted on and fixed to the above-mentioned package for housing a semiconductor device according to the present invention and which is electrically connected to the lead terminal through the metallized layer. And a lid joined to the upper surface of the base body.

【0011】本発明の半導体装置は、上記の構成によ
り、高周波信号を効率よく入出力させることができると
ともに半導体素子を長期にわたり正常かつ安定に作動さ
せ得る信頼性の高いものとなる。
With the above structure, the semiconductor device of the present invention is capable of efficiently inputting and outputting a high frequency signal, and has a high reliability capable of operating the semiconductor element normally and stably for a long period of time.

【0012】[0012]

【発明の実施の形態】本発明の半導体素子収納用パッケ
ージについて以下に詳細に説明する。図1は本発明の半
導体パッケージについて実施の形態の例を示す断面図で
ある。同図において、1は、上面に凹部1aを有すると
ともに凹部1aの底面に半導体素子2を載置する載置部
を有し、また下面に第二のメタライズ層1cが被着され
た絶縁材料から成る略直方体の基体である。3は、基体
1の上面に蓋体4をシーム溶接するための金属製のシー
ルリング、5は、上端部および中間部5aが基体1の側
面の延長面より内側に設けられているリード端子であ
り、第二のメタライズ層1cに上端部が接合されてい
る。これら基体1、シールリング3およびリード端子5
で半導体パッケージが主に構成される。
BEST MODE FOR CARRYING OUT THE INVENTION The semiconductor element housing package of the present invention will be described in detail below. FIG. 1 is a sectional view showing an example of an embodiment of a semiconductor package of the present invention. In the figure, reference numeral 1 denotes an insulating material having a recess 1a on the upper surface, a mounting portion for mounting the semiconductor element 2 on the bottom surface of the recess 1a, and a second metallized layer 1c deposited on the lower surface. It is a substantially rectangular parallelepiped base body. 3 is a metal seal ring for seam-welding the lid 4 on the upper surface of the base body 1, and 5 is a lead terminal in which the upper end portion and the intermediate portion 5a are provided inside the extension surface of the side surface of the base body 1. And the upper end is joined to the second metallization layer 1c. These base 1, seal ring 3 and lead terminal 5
The semiconductor package is mainly composed of.

【0013】本発明の基体1の材料は、アルミナ(Al
23)セラミックスや窒化アルミニウム(AlN)セラ
ミックス等のセラミックス、樹脂等の絶縁材料であり、
その誘電率や熱膨張係数等の特性と半導体素子2の特性
に応じて適宜選定される。
The material of the substrate 1 of the present invention is alumina (Al
2 O 3 ) Ceramics such as aluminum nitride (AlN) ceramics, insulating materials such as resin,
It is appropriately selected according to the characteristics such as the dielectric constant and the thermal expansion coefficient and the characteristics of the semiconductor element 2.

【0014】また、基体1の凹部1aの内面には第一の
メタライズ層1bが被着され、第一のメタライズ層1b
と第二のメタライズ層1cとは貫通導体1dを介して電
気的に接続され、第二のメタライズ層1cにはリード端
子5の上端部が銀(Ag)ロウ等のロウ材で接合され
る。そして、リード端子5の下端部が外部電気回路基板
7の線路導体(図示せず)に半田等によって接合され
る。リード端子5の下端部は、半田等により外部電気回
路基板7に強固に接合するために、好ましくは基体1の
下面と略平行な平坦面であるのが良い。その場合、外部
電気回路基板7上面に基体1下面を平行にして接合でき
るため基体1が外部電気回路基板7に安定に接合され
る。
A first metallization layer 1b is deposited on the inner surface of the recess 1a of the substrate 1, and the first metallization layer 1b is formed.
And the second metallization layer 1c are electrically connected to each other through the through conductor 1d, and the upper end portion of the lead terminal 5 is joined to the second metallization layer 1c by a brazing material such as silver (Ag) brazing. Then, the lower end portion of the lead terminal 5 is joined to a line conductor (not shown) of the external electric circuit board 7 by soldering or the like. The lower end portion of the lead terminal 5 is preferably a flat surface substantially parallel to the lower surface of the base 1 in order to firmly bond it to the external electric circuit board 7 by soldering or the like. In that case, since the lower surface of the base 1 can be parallel to the upper surface of the external electric circuit board 7, the base 1 can be stably bonded to the external electric circuit board 7.

【0015】そして、リード端子5の下端部は、外部電
気回路基板7の線路導体に半田等によって接続されるこ
とによって、半導体パッケージが外部電気回路基板7に
実装されることとなる。このリード端子5は、基体1と
の熱膨張係数差による熱歪みを有効に防止するとともに
高周波信号の伝送を可能とするために、基体1の熱膨張
係数に近似した金属から成るのが良い。その金属として
は、Fe−Ni合金やFe−Ni−Co合金等が良く、
例えばFe−Ni−Co合金のインゴット(塊)に圧延
加工法や打ち抜き加工法等の従来周知の金属加工法を施
すことによって所定形状に形成される。
The lower end of the lead terminal 5 is connected to the line conductor of the external electric circuit board 7 by soldering or the like, so that the semiconductor package is mounted on the external electric circuit board 7. The lead terminal 5 is preferably made of a metal having a coefficient of thermal expansion close to that of the substrate 1 in order to effectively prevent thermal strain due to a difference in thermal expansion coefficient with the substrate 1 and to enable transmission of high frequency signals. As the metal, an Fe-Ni alloy, an Fe-Ni-Co alloy, or the like is preferable,
For example, an Fe-Ni-Co alloy ingot (lump) is formed into a predetermined shape by subjecting the ingot (lump) to a conventionally known metal working method such as a rolling working method or a punching working method.

【0016】リード端子5は、図2に部分拡大断面図を
示すように、その中間部5aが、基体1の下面に対して
θ=30〜60°で傾斜しているのが良い。これにより、半
導体パッケージを外部電気回路基板7に実装し、基体1
と外部電気回路基板7との間で熱膨張差が生じても、熱
膨張差を中間部5aが適度に変形して吸収し、基体1に
外部電気回路基板7との熱膨張差による大きな応力が加
わるのを防止できる。θ<30°の場合、中間部5aの折
り曲げ角度が小さいため、基体1と外部電気回路基板7
との間で熱膨張差が生じた際、中間部5aが変形して熱
膨張差を吸収するのが困難になり、基体1の下面に大き
な応力が加わり易くなる。θ>60°の場合、中間部5a
の上端側で第二のメタライズ層1cとの間に良好なロウ
材のメニスカスを形成できなくなり、基体1とリード端
子5との接合強度が低下し易くなる。
As shown in a partially enlarged sectional view of FIG. 2, the lead terminal 5 preferably has an intermediate portion 5a inclined with respect to the lower surface of the base body 1 by θ = 30 to 60 °. As a result, the semiconductor package is mounted on the external electric circuit board 7 and the base 1
Even if there is a difference in thermal expansion between the external electric circuit board 7 and the external electric circuit board 7, the intermediate portion 5a appropriately deforms and absorbs the difference in thermal expansion, and the base 1 has a large stress due to the difference in thermal expansion with the external electric circuit board 7. Can be prevented. When θ <30 °, since the bending angle of the intermediate portion 5a is small, the base 1 and the external electric circuit board 7
When a difference in thermal expansion occurs between and, it becomes difficult for the intermediate portion 5a to deform and absorb the difference in thermal expansion, and a large stress is likely to be applied to the lower surface of the substrate 1. When θ> 60 °, middle part 5a
A good meniscus of a brazing material cannot be formed between the upper end of the base metal 1 and the second metallized layer 1c, and the bonding strength between the base 1 and the lead terminal 5 is likely to decrease.

【0017】またリード端子5は、2〜25GHz帯域で
の高周波信号を効率良くさせるためには、中間部5aの
下端と基体1の側面の延長面との間の距離Xおよびリー
ド端子5の高さYについて、X≧0.2mm、0.5mm≦Y
≦1mmが良い。X<0.2mmの場合、Xが短いため、基
体1と外部電気回路基板7との間で熱膨張差が生じた際
に中間部5aの下端が基体1より外側に飛び出し、中間
部5aの基体1より外側に飛び出した部位でインダクタ
ンス成分が大きくなってインピーダンス整合ができなく
なり、その結果、中間部5aを伝送する高周波信号に反
射損失や透過損失が生じて、中間部5aでの伝送特性が
劣化し易くなる。また、Y<0.5mmの場合、中間部5
aが短いため、基体1と外部電気回路基板7との間で熱
膨張差が生じた際、中間部5aで熱膨張差を吸収できず
に基体1の下面に大きな応力が加わって、基体1にクラ
ックを生ずる場合がある。Y>1mmの場合、中間部5
aが長くなりすぎて、中間部5aを伝送する高周波信号
の透過損失が大きくなり易い。
In order to make the high frequency signal in the 2 to 25 GHz band efficient, the lead terminal 5 has a distance X between the lower end of the intermediate portion 5a and the extended surface of the side surface of the substrate 1 and a height of the lead terminal 5. Regarding Y, X ≧ 0.2mm, 0.5mm ≦ Y
≦ 1mm is good. In the case of X <0.2 mm, since X is short, the lower end of the intermediate portion 5a jumps out from the substrate 1 when a difference in thermal expansion occurs between the substrate 1 and the external electric circuit board 7, and the substrate of the intermediate portion 5a The impedance component becomes large at the portion protruding outside 1 and impedance matching cannot be performed. As a result, a reflection loss and a transmission loss occur in the high frequency signal transmitted through the intermediate portion 5a, and the transmission characteristics at the intermediate portion 5a deteriorate. Easier to do. When Y <0.5 mm, the middle part 5
Since a is short, when a difference in thermal expansion occurs between the base body 1 and the external electric circuit board 7, the intermediate portion 5a cannot absorb the difference in thermal expansion, and a large stress is applied to the lower surface of the base body 1. May cause cracks in. If Y> 1 mm, middle part 5
Since a becomes too long, the transmission loss of the high frequency signal transmitted through the intermediate portion 5a tends to increase.

【0018】本発明の第一のメタライズ層1b,第二の
メタライズ層1cは、タングステン(W),モリブデン
(Mo),マンガン(Mn)等の高融点金属粉末に適当
な有機バインダ、溶剤等を添加混合して得た金属ペース
トを、基体1となるセラミックグリーンシートの多層積
層体に、従来周知のスクリーン印刷法により所定パター
ンで印刷塗布し、その後焼成することによって、基体1
に被着形成される。または、基体1となるセラミックグ
リーンシートの多層積層体を焼成した後に、その焼成体
に金属ペーストを所定パターンで印刷塗布し金属ペース
トを焼成することによって、基体1に被着形成される。
The first metallized layer 1b and the second metallized layer 1c of the present invention are made of a refractory metal powder such as tungsten (W), molybdenum (Mo), manganese (Mn), or the like, and an appropriate organic binder, solvent or the like. The metal paste obtained by the addition and mixing is printed and applied in a predetermined pattern on a multilayer laminate of ceramic green sheets to be the substrate 1 by a conventionally known screen printing method, and then baked to obtain the substrate 1.
It is deposited on. Alternatively, after firing the multilayer laminate of the ceramic green sheets to be the base 1, the fired body is printed and coated with a metal paste in a predetermined pattern, and the metal paste is fired to form a coating on the base 1.

【0019】貫通導体1dは、ビアホール,スルーホー
ル等から成り、各セラミックグリーンシートの所望の位
置に貫通導体となる貫通孔を形成し、この貫通孔に、
W,Mo,Mn等の粉末に有機溶剤,溶媒を添加混合し
て得た金属ペーストを充填し、第一のメタライズ層1
b,第二のメタライズ層1cとなる金属ペーストと同時
に焼結することにより製作される。
The through conductor 1d is composed of a via hole, a through hole, etc., and a through hole serving as a through conductor is formed at a desired position of each ceramic green sheet.
The first metallized layer 1 is filled with an organic solvent and a metal paste obtained by adding and mixing a solvent to powders of W, Mo, Mn, etc.
b, it is manufactured by sintering at the same time as the metal paste to be the second metallized layer 1c.

【0020】また、基体1の上面には、基体1との熱膨
張係数差による熱歪みを有効に防止するとともに基体1
の上面に接合されて蓋体4のシーム溶接を可能とする金
属製のシールリング3が、Agロウ等のロウ材を介して
接合される。その金属としてはFe−Ni合金やFe−
Ni−Co合金等がよく、例えばFe−Ni−Co合金
のインゴット(塊)に圧延加工法や打ち抜き加工法等の
従来周知の金属加工法を施すことによって所定形状に形
成される。
On the upper surface of the substrate 1, thermal strain due to the difference in thermal expansion coefficient from the substrate 1 is effectively prevented, and the substrate 1 is
The metal seal ring 3 that is joined to the upper surface of the above and enables seam welding of the lid body 4 is joined via a brazing material such as Ag brazing. As the metal, Fe-Ni alloy or Fe-
Ni-Co alloy or the like is preferable, and for example, it is formed into a predetermined shape by subjecting an ingot (lump) of Fe-Ni-Co alloy to a conventionally known metal working method such as a rolling working method or a punching working method.

【0021】かくして、本発明の半導体パッケージは、
上面に形成された凹部1aの底面に半導体素子2を載置
する載置部が設けられている絶縁材料から成る略直方体
の基体1と、基体1の下面の外周部に形成されたメタラ
イズ層1cと、メタライズ層1cに接合された上端部お
よび上端部から基体1の外側下方に傾斜するように延設
された中間部5aならびに上端部に略平行な下端部から
成るリード端子5とを具備し、リード端子5は、上端部
および中間部5aが基体1の側面の延長面より内側に設
けられている。
Thus, the semiconductor package of the present invention is
A substantially rectangular parallelepiped base body 1 made of an insulating material in which a mounting portion for mounting the semiconductor element 2 is provided on the bottom surface of the concave portion 1a formed on the upper surface, and a metallized layer 1c formed on the outer peripheral portion of the lower surface of the base body 1. And a lead terminal 5 including an upper end portion joined to the metallized layer 1c, an intermediate portion 5a extending from the upper end portion so as to incline downward to the outside of the base 1, and a lower end portion substantially parallel to the upper end portion. The lead terminal 5 has an upper end portion and an intermediate portion 5 a provided inside the extension surface of the side surface of the base body 1.

【0022】本発明の半導体装置は、本発明の半導体パ
ッケージと、載置部に載置固定されるとともに第一のメ
タライズ層1b、貫通導体1dおよび第二のメタライズ
層1cを介してリード端子5に電気的に接続された半導
体素子2と、基体1の上面に接合された蓋体4とを具備
している。具体的には、基体1の載置部に半導体素子2
をガラス,樹脂,ロウ材等の接着剤を介して接着固定
し、半導体素子2の各電極をボンディングワイヤ6で第
一のメタライズ層1bに接続し、しかる後、基体1上面
にシールリング3を介して蓋体4をシーム溶接等により
接合して封止することにより、半導体素子2を内部に気
密に封止した半導体装置となる。そして、半導体素子2
と外部電気回路基板7とは、リード端子5を介して電気
的に接続されることになる。
The semiconductor device of the present invention is mounted on the mounting portion of the semiconductor package of the present invention and fixed, and the lead terminal 5 is provided via the first metallization layer 1b, the through conductor 1d and the second metallization layer 1c. The semiconductor element 2 electrically connected to the base 1 and the lid 4 bonded to the upper surface of the base 1. Specifically, the semiconductor element 2 is mounted on the mounting portion of the base 1.
Are bonded and fixed via an adhesive such as glass, resin or brazing material, each electrode of the semiconductor element 2 is connected to the first metallization layer 1b by the bonding wire 6, and then the seal ring 3 is attached to the upper surface of the substrate 1. The lid 4 is joined by seam welding or the like to seal the semiconductor element 2 in a hermetically sealed state. Then, the semiconductor element 2
And the external electric circuit board 7 are electrically connected via the lead terminal 5.

【0023】[0023]

【実施例】本発明の半導体素子収納用パッケージの実施
例を以下に説明する。
EXAMPLE An example of a package for housing a semiconductor device according to the present invention will be described below.

【0024】図1の半導体パッケージを以下のように構
成した。上面の凹部1aの底面にMo−Mnから成る第
一のメタライズ層1bが形成され、下面の外周部にMo
−Mnから成る第二のメタライズ層1cが形成され、第
一のメタライズ層1bと第二のメタライズ層1cとがM
o−Mnを充填して成る貫通導体1dによって接続され
たアルミナセラミックスから成る直方体の基体1を用意
した。基体1の下面の第二のメタライズ層1cに上端部
がAgロウで接合されるとともに上端部および中間部5
aが基体1の側面の延長面から内側に設けられたFe−
Ni−Co合金から成るリード端子5を基体1下面に20
本設けることにより、半導体パッケージを作製した。こ
の本発明の半導体パッケージをサンプルAとした。サン
プルAは、中間部5aが基体1の側面の延長面よりも内
側にあり、具体的には図2のX,YについてX=0.25m
m,Y=0.5mmとした。
The semiconductor package shown in FIG. 1 was constructed as follows. A first metallization layer 1b made of Mo-Mn is formed on the bottom surface of the recess 1a on the upper surface, and Mo is formed on the outer peripheral portion of the lower surface.
A second metallization layer 1c made of —Mn is formed, and the first metallization layer 1b and the second metallization layer 1c are M.
A rectangular parallelepiped substrate 1 made of alumina ceramics connected by a through conductor 1d filled with o-Mn was prepared. The upper end portion is joined to the second metallized layer 1c on the lower surface of the base body 1 by Ag solder, and the upper end portion and the intermediate portion 5 are formed.
a is Fe- provided inside from the extended surface of the side surface of the substrate 1.
A lead terminal 5 made of a Ni-Co alloy is provided on the lower surface of the base body 20.
A semiconductor package was manufactured by providing this. This semiconductor package of the present invention is referred to as Sample A. In the sample A, the intermediate portion 5a is inside the extended surface of the side surface of the substrate 1, and specifically, X = 0.25 m for X and Y in FIG.
m, Y = 0.5 mm.

【0025】また、比較例として、リード端子5の中間
部5aが基体1の側面の延長面より外側に0.75mm飛び
出しており、Y=0.5mmとしたものを上記実施例と同
様に作製した。これをサンプルBとした。
Further, as a comparative example, the intermediate portion 5a of the lead terminal 5 was projected 0.75 mm outward from the extended surface of the side surface of the base body 1, and Y = 0.5 mm was prepared in the same manner as in the above embodiment. This was designated as Sample B.

【0026】そして、サンプルA,Bについて、リード
端子5に2〜25GHzの高周波信号を入力してその反射
損失を測定した結果を図4に示す。図4より、サンプル
AはサンプルBに比べて5〜17GHz,19〜25GHzで
反射損失が小さく、特に5〜17GHzでは大幅に反射損
失が改善された。
FIG. 4 shows the results of measuring the reflection loss of samples A and B by inputting a high frequency signal of 2 to 25 GHz to the lead terminal 5. As shown in FIG. 4, the sample A has a smaller reflection loss at 5 to 17 GHz and 19 to 25 GHz than the sample B, and particularly the reflection loss is significantly improved at 5 to 17 GHz.

【0027】なお、本発明は上記実施の形態および実施
例に限定されず、本発明の要旨を逸脱しない範囲内で種
々の変更を施すことは何等差し支えない。
The present invention is not limited to the above embodiments and examples, and various modifications may be made without departing from the scope of the present invention.

【0028】[0028]

【発明の効果】本発明の半導体素子収納用パッケージ
は、上面に形成された凹部の底面に半導体素子を載置す
る載置部が設けられている絶縁材料から成る略直方体の
基体と、基体の下面の外周部に形成されたメタライズ層
と、メタライズ層に接合された上端部および上端部から
基体の外側下方に傾斜するように延設された中間部なら
びに上端部に略平行な下端部から成るリード端子とを具
備し、リード端子は、上端部および中間部が基体の側面
の延長面より内側に設けられていることにより、中間部
がメタライズ層の下方に位置していることから、中間部
とメタライズ層との間に電気的な容量成分が生じ、この
容量成分が中間部のインダクタンス成分によるインピー
ダンスの増加を打ち消すように作用してインピーダンス
のずれが解消される。また、リード端子の上端部はメタ
ライズ層の内周側に接合されるので、メタライズ層の長
さによる抵抗を小さくすることができる。その結果、イ
ンピーダンスが整合されて、2〜25GHz程度の高周波
帯域の高周波信号を半導体素子収納用パッケージに入出
力させても、反射損失や透過損失を小さくして効率よく
伝送させることができる。従って、2〜25GHz程度の
高周波帯域で作動する半導体素子を問題なく収納するこ
とが可能となる。
The package for housing a semiconductor element of the present invention comprises a base of a substantially rectangular parallelepiped made of an insulating material, and a base on which a semiconductor element is mounted is provided on the bottom surface of a recess formed on the top surface of the base. It is composed of a metallization layer formed on the outer peripheral portion of the lower surface, an upper end portion joined to the metallization layer, an intermediate portion extending so as to incline downward from the upper end portion to the outside of the base body, and a lower end portion substantially parallel to the upper end portion. The lead terminal is provided with the upper end portion and the intermediate portion inside the extension surface of the side surface of the base body, so that the intermediate portion is located below the metallization layer. An electrical capacitance component is generated between the metallization layer and the metallization layer, and this capacitance component acts to cancel the increase in impedance due to the inductance component in the middle portion, and the shift in impedance is eliminated. Further, since the upper end portion of the lead terminal is joined to the inner peripheral side of the metallized layer, the resistance due to the length of the metallized layer can be reduced. As a result, even if the impedance is matched and a high frequency signal in a high frequency band of about 2 to 25 GHz is input to and output from the semiconductor element housing package, the reflection loss and the transmission loss can be reduced and the transmission can be efficiently performed. Therefore, it is possible to accommodate a semiconductor element operating in a high frequency band of about 2 to 25 GHz without any problem.

【0029】また、リード端子が折り曲げられて傾斜し
た中間部を有することにより、リード端子を介して半導
体素子収納用パッケージを外部電気回路基板に実装する
際に基体と外部電気回路基板との間で熱膨張差が生じて
も、熱膨張差を中間部が吸収するため、基体に外部電気
回路基板との熱膨張差による大きな応力が加わるのを防
止できる。
Further, since the lead terminal has the intermediate portion which is bent and inclined, when the semiconductor element housing package is mounted on the external electric circuit board via the lead terminal, the lead terminal is provided between the base body and the external electric circuit board. Even if there is a difference in thermal expansion, the intermediate portion absorbs the difference in thermal expansion, so that it is possible to prevent a large stress from being applied to the base body due to the difference in thermal expansion from the external electric circuit board.

【0030】本発明の半導体装置は、上記本発明の半導
体素子収納用パッケージと、載置部に載置固定されると
ともにメタライズ層を介してリード端子に電気的に接続
された半導体素子と、基体の上面に接合された蓋体とを
具備したことにより、高周波信号を効率よく入出力させ
ることができるとともに半導体素子を長期にわたり正常
かつ安定に作動させ得る信頼性の高いものとなる。
The semiconductor device of the present invention comprises the above-mentioned package for accommodating a semiconductor element of the present invention, a semiconductor element mounted and fixed on a mounting portion and electrically connected to a lead terminal through a metallization layer, and a substrate. By including the lid body joined to the upper surface of the above, it becomes possible to efficiently input and output a high frequency signal and to operate the semiconductor element normally and stably for a long time with high reliability.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の半導体素子収納用パッケージについて
実施の形態の例を示す断面図である。
FIG. 1 is a cross-sectional view showing an example of an embodiment of a package for housing a semiconductor element of the present invention.

【図2】図1の半導体素子収納用パッケージにおけるリ
ード端子周辺部の部分拡大断面図である。
FIG. 2 is a partial enlarged cross-sectional view of a peripheral portion of a lead terminal in the semiconductor element housing package of FIG.

【図3】従来の半導体素子収納用パッケージの断面図で
ある。
FIG. 3 is a cross-sectional view of a conventional semiconductor element housing package.

【図4】本発明の半導体素子収納用パッケージと従来の
半導体素子収納用パッケージについて高周波信号の反射
損失を測定した結果のグラフである。
FIG. 4 is a graph showing the results of measuring the reflection loss of a high-frequency signal for the semiconductor device housing package of the present invention and the conventional semiconductor device housing package.

【符号の説明】[Explanation of symbols]

1:基体 1a:凹部 1c:メタライズ層 2:半導体素子 5:リード端子 5a:中間部 1: Base 1a: recess 1c: Metallized layer 2: Semiconductor element 5: Lead terminal 5a: middle part

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 上面に形成された凹部の底面に半導体素
子を載置する載置部が設けられている絶縁材料から成る
略直方体の基体と、該基体の下面の外周部に形成された
メタライズ層と、該メタライズ層に接合された上端部お
よび該上端部から前記基体の外側下方に傾斜するように
延設された中間部ならびに前記上端部に略平行な下端部
から成るリード端子とを具備した半導体素子収納用パッ
ケージにおいて、前記リード端子は、前記上端部および
前記中間部が前記基体の側面の延長面より内側に設けら
れていることを特徴とする半導体素子収納用パッケー
ジ。
1. A substantially rectangular parallelepiped base body made of an insulating material, in which a mounting portion for mounting a semiconductor element is provided on the bottom surface of a recess formed on the upper surface, and a metallization formed on the outer peripheral portion of the lower surface of the base body. And a lead terminal having an upper end joined to the metallized layer, an intermediate part extending from the upper end so as to incline downward to the outside of the base, and a lower end substantially parallel to the upper end. In the semiconductor element storage package described above, the lead terminal has the upper end portion and the intermediate portion provided inside an extension surface of a side surface of the base body.
【請求項2】 請求項1記載の半導体素子収納用パッケ
ージと、前記載置部に載置固定されるとともに前記メタ
ライズ層を介して前記リード端子に電気的に接続された
半導体素子と、前記基体の上面に接合された蓋体とを具
備したことを特徴とする半導体装置。
2. The package for accommodating a semiconductor element according to claim 1, a semiconductor element mounted and fixed on the mounting portion and electrically connected to the lead terminal through the metallization layer, and the base body. And a lid joined to the upper surface of the semiconductor device.
JP2002044376A 2002-02-21 2002-02-21 Package for accommodating semiconductor device and semiconductor device Pending JP2003243552A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2002044376A JP2003243552A (en) 2002-02-21 2002-02-21 Package for accommodating semiconductor device and semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002044376A JP2003243552A (en) 2002-02-21 2002-02-21 Package for accommodating semiconductor device and semiconductor device

Publications (1)

Publication Number Publication Date
JP2003243552A true JP2003243552A (en) 2003-08-29

Family

ID=27783783

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002044376A Pending JP2003243552A (en) 2002-02-21 2002-02-21 Package for accommodating semiconductor device and semiconductor device

Country Status (1)

Country Link
JP (1) JP2003243552A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014179432A (en) * 2013-03-14 2014-09-25 Kyocera Corp Package for mounting electronic component and electronic device using the same
WO2015088028A1 (en) * 2013-12-13 2015-06-18 京セラ株式会社 Element housing package and mounting structure

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014179432A (en) * 2013-03-14 2014-09-25 Kyocera Corp Package for mounting electronic component and electronic device using the same
WO2015088028A1 (en) * 2013-12-13 2015-06-18 京セラ株式会社 Element housing package and mounting structure

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