JP2003243543A - Semiconductor storage and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent residues from being remained on the side of an element separation trench in an etching process for removing a trap film in a logic circuit region in a method for manufacturing a semiconductor storage that has a memory element for storing information by accumulating charges in the trap film and a logic circuit on a semiconductor substrate. <P>SOLUTION: A trap film 103 is deposited on a semiconductor substrate 100, and then a portion that is deposited on a logic circuit region in the trap film 103 is removed. After that, a first conductive film 106 is deposited onto the semiconductor substrate 100. Then, the first conductive film 106 and the semiconductor substrate 100 are selectively etched, an element separation groove is formed in the logic circuit region, an insulating film is buried in the element separation groove, and the element separation trench 108 is formed. A second conductive film is deposited onto the semiconductor substrate 100, and the first conductive films 106 that are mutually separated are electrically connected by a second conductive film 109. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device in which a memory element and a logic circuit are provided on one semiconductor substrate, and a manufacturing method thereof.

[0002]

2. Description of the Related Art In recent years, a semiconductor memory device (so-called mixed device) in which a memory element and a logic circuit are provided on one semiconductor substrate has been actively developed for the purpose of increasing the speed and increasing the functionality of the semiconductor memory device. Has been done in.

As a memory device, for example, Japanese Patent Laid-Open No. 05-326
As shown in 893, the method of trapping charges in the gate insulating film is attracting attention as a device that is unlikely to cause information change due to charge leakage.

Further, in the logic circuit area, many devices employing trench element isolation which can promote miniaturization have been developed.

A conventional example of a mixed device using a method of trapping charges in a gate insulating film as a memory element and using trench element isolation in a logic circuit area will be described below.
19 (a)-(d), 20 (a)-(d) and 21 (a)-
Explanation will be given with reference to (d). Incidentally, FIGS. 19 (a) to (d),
20 (a) to 20 (d) and 21 (a) to 21 (d), the left side of the break line shows the cross-sectional structure of the memory element region, and the right side of the break line shows the cross-sectional structure of the logic circuit section. Is shown.
In addition, an n-channel type transistor and a p-channel type transistor are usually formed in the logic circuit region, but these are different only in the kind of impurities. ing.

First, as shown in FIG. 19A, a pad oxide film 11 and a silicon nitride film 12 are sequentially deposited on a silicon substrate 10, and then a first resist is formed as shown in FIG. 19B. Using the pattern 13 as a mask, the silicon nitride film 12, the pad oxide film 11 and the silicon substrate 10 are sequentially selectively etched to form a trench groove 14
To form.

Next, as shown in FIG. 19C, an insulating film is buried in the trench groove 14 to form a trench element isolation 15, and then, as shown in FIG. 19D, the silicon nitride film 12 and the pad are formed. The oxide film 11 is removed.

Next, as shown in FIG. 20A, a trap film 16 made of, for example, a silicon nitride film is deposited over the entire surface of the silicon substrate 10.

Next, as shown in FIG. 20B, in the memory element region, impurities are implanted into the silicon substrate 10 using the second resist pattern 17 as a mask, and the impurity diffusion layer 18 to be a bit line is formed. Then, the trap film 16 is selectively etched using the second resist pattern 17 as a mask to remove the upper region of the trap film 16 above the impurity diffusion layer 18.

Next, as shown in FIG. 20 (c), after removing the second resist pattern 17, in the memory element region,
The LOCOS isolation region 19 is formed by the thermal oxidation method.

Next, as shown in FIG. 20 (d), the trap film 16 is selectively etched by using the third resist pattern 20 as a mask to remove the trap film 16 in the logic circuit region. In this case, a residue 16A made of the trap film 16 is formed on the side surface of the portion of the trench isolation 15 protruding from the silicon substrate 10.

Next, as shown in FIG. 21 (a), after removing the third resist pattern 20, as shown in FIG. 22 (b), the entire surface of the silicon substrate 10 is covered by thermal oxidation. A polysilicon film 22 is deposited all over.

Next, as shown in FIG. 21 (c), the polysilicon film 22 is selectively etched using the fourth resist pattern 23 as a mask to form a memory as shown in FIG. 22 (d). A first gate electrode 22A is formed in the element region and a second gate electrode 22B is formed in the logic circuit region.

[0014]

However, in the conventional semiconductor memory device, as shown in FIGS. 21 (c) and 21 (d), the side surface of the trench element isolation 15 below the second gate electrode 22B is formed. Since the residue 16A made of the silicon nitride film is present, there is a problem that the transistor characteristics in the logic circuit region are changed.

However, the trap film 16 in the logic circuit area
If the trap film 16 is over-etched in the etching step of removing the residue, it is possible to prevent the residue 16A from remaining. However, in this case, the trench element isolation 15 is etched, and the trench element isolation 15 is dug below the surface of the silicon substrate 10.
There is a problem that the gate electric field concentration occurs on the side of the gate and the transistor characteristics change. Therefore, the trap film 1
It is not preferable to perform overetching on No. 6.

In view of the above, it is an object of the present invention to prevent residue from being generated on the side surface of trench element isolation in the etching process for removing the trap film in the logic circuit region without performing overetching.

[0017]

In order to achieve the above object, a semiconductor memory device according to the present invention comprises:
A semiconductor memory device including a memory element that stores information by accumulating charges in a trap film and a logic circuit is targeted, and a gate electrode forming the logic circuit is a trench element isolation formed in a logic circuit region. A plurality of first conductive films which are separated from each other by a top surface of each of the first conductive films whose height positions are substantially the same as the height positions of the top surfaces of the trench element isolations. And a second conductive film that electrically connects the plurality of first conductive films to each other.

According to the semiconductor memory device of the present invention, the gate electrodes forming the logic circuit are separated from each other by the trench element isolation formed in the logic circuit region, and the height position of each upper surface is the trench. A plurality of first conductive films that are substantially equal to the height position of the upper surface of element isolation,
Since the trench element isolation and the second conductive film which is formed over the plurality of first conductive films and electrically connects the plurality of first conductive films to each other are formed in the logic circuit region in the trap film. After removing the deposited portion, depositing the first conductive film, and then performing selective etching on the first conductive film and the semiconductor substrate to form an element isolation groove in the logic circuit region. You can For this reason, no residue consisting of the trap film is generated on the side surface of the trench element isolation, and the transistor characteristics in the logic circuit region are stabilized.

In the semiconductor memory device according to the present invention, the gate electrode formed in the memory element region is preferably composed of the first conductive film and the second conductive film.

In this way, the gate electrode formed in the memory element region and the gate electrode formed in the logic circuit region are formed in the same laminated structure of the lower first conductive film and the upper second conductive film. It can be composed of a membrane.

The semiconductor memory device according to the present invention preferably comprises an alignment mark provided in a region other than the logic circuit region and the memory element region on the semiconductor substrate.

In this way, the alignment mark is aligned with the photomask in the step of implanting impurities into the logic circuit area or the memory element area, or in the step of forming the element isolation groove for forming the trench element isolation. Can be used.

In order to achieve the above-mentioned object, a method of manufacturing a semiconductor memory device according to the present invention comprises a memory element for storing information by accumulating charges in a trap film and a logic circuit on a semiconductor substrate. The present invention is directed to a method for manufacturing a semiconductor memory device having the above-described structure, and a first step of depositing a trap film over the entire surface of a semiconductor substrate and a second step of removing a portion of the trap film deposited in a logic circuit region. Steps, a third step of depositing the first conductive film over the entire surface of the semiconductor substrate, and selective etching of the first conductive film and the semiconductor substrate to form element isolation trenches in the logic circuit region. A fourth step of forming the element isolation step, a fifth step of filling the element isolation trench with an insulating film to form a trench element isolation, and a second conductive film deposited over the entire surface of the semiconductor substrate. Fourth work And a sixth step of electrically connecting the first conductive film between the second conductive film are separated from each other by an isolation trench in.

According to the method for manufacturing a semiconductor memory device of the present invention, the portion of the trap film deposited in the logic circuit region is removed, the first conductive film is deposited, and then the first conductive film and Since the element isolation trench is formed in the logic circuit region by selectively etching the semiconductor substrate, the residue formed of the trap film is not generated on the side surface of the trench element isolation, so that the transistor characteristics in the logic circuit region are stabilized.

The method of manufacturing a semiconductor memory device according to the present invention comprises a step of forming an insulating film to be a gate insulating film in a logic circuit region on a semiconductor substrate between the second step and the third step. , The third step is the first step in the logic circuit area.
It is preferable to include a step of depositing the conductive film of (4) on the insulating film.

By doing so, the gate electrode made of the first conductive film and the second conductive film can be formed on the gate insulating film formed in the logic circuit region.

When the method of manufacturing a semiconductor device according to the present invention includes a step of forming an insulating film to be a gate insulating film in the logic circuit area, the first step is performed in the memory element area after the sixth step. Forming a first gate electrode composed of the conductive film and the second conductive film, and forming a second gate electrode composed of the first conductive film and the second conductive film in the logic circuit region. Preferably.

By doing so, the first gate electrode formed in the memory element region and the second gate electrode formed in the logic circuit region are connected to the lower first conductive film and the upper second conductive film. It can be configured by the same laminated film made of conductive films. The first gate electrode and the second gate electrode may be patterned in the same process or may be patterned in different processes.

When the method of manufacturing a semiconductor device according to the present invention includes a step of forming an insulating film to be a gate insulating film in a logic circuit region, the first step and the insulating film to be a gate insulating film are formed. It is preferable to include a step of implanting an impurity into the logic circuit region of the semiconductor substrate between the step and the step.

In this way, since the gate insulating film is formed in the logic circuit region after the impurity is implanted, the reliability of the gate insulating film can be secured.

The semiconductor memory device manufacturing method according to the present invention preferably comprises a step of implanting impurities into the memory element region and the logic circuit region of the semiconductor substrate before the first step.

In this way, impurities can be implanted before depositing the trap film.

The method of manufacturing a semiconductor memory device according to the present invention includes a step of forming an alignment mark on the semiconductor substrate before the first step, and the first photo aligned using the alignment mark. A step of implanting impurities into the memory element region of the semiconductor substrate using the first resist pattern formed by the mask as a mask, and a second resist pattern formed by the second photomask aligned using the alignment mark Is preferably used as a mask to implant impurities into the logic circuit region of the semiconductor substrate.

In this way, it is not necessary to use the trench element isolation as the alignment mark because the impurity can be implanted into the memory element region and the impurity into the logic circuit region by using the alignment mark. Therefore, it becomes easy to form the element isolation groove after depositing the trap film.

The method for manufacturing a semiconductor memory device according to the present invention comprises a step of forming an element isolation region in the memory element region prior to the first step, and the element isolation region is used as an alignment mark for alignment. First
Using the first resist pattern formed by the photomask as a mask, a step of implanting impurities into the memory element region of the semiconductor substrate, and the second photomask aligned by using the element isolation region as an alignment mark. It is preferable that the method further includes the step of implanting impurities into the logic circuit region of the semiconductor substrate using the second resist pattern as a mask.

In this way, the element isolation region formed in the memory element region can be used to inject impurities into the memory element region and also into the logic circuit region. Therefore, it is necessary to use trench element isolation as an alignment mark. There is no. Therefore, it becomes easy to form the element isolation groove after depositing the trap film.

The method of manufacturing a semiconductor memory device according to the present invention comprises a step of forming an alignment mark on a semiconductor substrate before the second step, and the second step is performed by using the alignment mark. It is preferable to use a resist pattern formed by a photomask.

In this way, the alignment mark can be used to remove the portion of the trap film deposited in the logic circuit region, so that it is not necessary to use trench element isolation as the alignment mark. Therefore, it becomes easy to form the element isolation groove after depositing the trap film.

The method for manufacturing a semiconductor memory device according to the present invention comprises a step of forming an element isolation region in the memory element region before the second step, and the second step is to align the element isolation region with an alignment mark. It is preferable to use a resist pattern formed by a photomask aligned as above.

In this way, the element isolation region formed in the memory element region can be used to remove the portion of the trap film deposited in the logic circuit region, so that the trench element isolation is used as an alignment mark. No need. Therefore, it becomes easy to form the element isolation groove after depositing the trap film.

[0041]

BEST MODE FOR CARRYING OUT THE INVENTION A semiconductor memory device and a method of manufacturing the same according to each embodiment of the present invention will be described below.
Normally, an n-channel transistor and p are provided in the logic circuit area.
Although a channel type transistor is formed, these are different only in the kind of impurities, and therefore, in each of the sectional views shown below, only an n channel type transistor is shown.

(First Embodiment) A semiconductor memory device according to a first embodiment of the present invention and a method of manufacturing the same will be described with reference to FIGS. 1 (a) to 1 (c) and 2 (a) to 2 (c). , Fig. 3 (a)-(c)
4 (a) to 4 (c) and FIG.
1 (a)-(c), 2 (a)-(c), 3 (a)-(c)
4 (a) to 4 (c), the drawing on the left side shows the memory device area, the drawing on the center shows the logic circuit area, and the drawing on the right side shows the alignment mark area. Shows the memory device area, and the drawing on the right shows the logic circuit area.

First, as shown in FIG. 1A, after depositing a silicon oxide film 101 having a thickness of about 200 nm on a semiconductor substrate 100 made of a silicon substrate,
As shown in (b), the silicon oxide film 101 is patterned to form the alignment mark 101A in the alignment mark region.

Next, as shown in FIG. 1C, after forming a first resist pattern 102 by a first photomask (not shown) aligned using the alignment mark 101A, The first resist pattern 102 is formed on the memory element region of the semiconductor substrate 100.
Is used as a mask to perform impurity implantation for controlling the threshold voltage of the memory element region.

Next, as shown in FIG. 2 (a), a layered film of, for example, a silicon oxide film, a silicon nitride film, and a silicon oxide film is formed over the entire surface of the semiconductor substrate 100.
A trap film 103 having a total film thickness of 0 nm is deposited.

Next, as shown in FIG. 2B, after forming a second resist pattern 104 by a second photomask (not shown) aligned using the alignment mark 101A, Impurity implantation for controlling the threshold voltage of the logic circuit region is performed on the logic circuit region of the semiconductor substrate 100 using the second resist pattern 104 as a mask.

Next, as shown in FIG. 2C, the trap film 103 is selectively etched by using the second resist pattern 104 as a mask to remove the trap film 103 in the logic circuit region. . Either the impurity implantation or the selective etching performed using the second resist pattern 104 as a mask may be performed first.

Next, as shown in FIG. 3A, the logic circuit region on the surface of the semiconductor substrate 100 is oxidized to form an insulating film 105 having a thickness of 2 nm to 25 nm and serving as a gate insulating film. After that, as shown in FIG. 3 (b), phosphorus is, for example, 1 × 10 ²⁰ over the entire surface of the semiconductor substrate 100.
cm ⁻³ to 1 × 10 ²¹ cm ⁻³ doped and for example 150
A first polycrystalline silicon film 106 having a thickness of nm to 300 nm is deposited.

Next, as shown in FIG. 3C, the semiconductor substrate 100, the trap film 103, and the first film are formed in the memory element region by using the third resist pattern 107 as a mask.
The semiconductor substrate 100, the insulating film 105, and the first polycrystalline silicon film 106 in the logic circuit region are selectively etched with respect to the polycrystalline silicon film 106 of FIG. In this way, in the memory element area and the logic circuit area, the first
The polycrystalline silicon film 106 is separated by the element separation groove 108a.

Next, as shown in FIG. 4A, an insulating film is buried in the element isolation trench 108a to form a trench element isolation 10a.
8 is formed. In this case, the height position of the upper surface of the trench element isolation 108 and the height position of the upper surface of the first polycrystalline silicon film 106 are made substantially equal.

Next, as shown in FIG. 4B, phosphorus is, for example, 1 × 10 ²⁰ cm all over the semiconductor substrate 100.
^-3 to 1 × 10 ²¹ cm ^-3 doped and for example 150 nm
Second polycrystalline silicon film 1 having a thickness of ˜300 nm
09 is deposited. In this way, the element isolation trench 108
The first polycrystalline silicon films 106 that are separated from each other by a and the trench element isolation 108 are electrically connected to each other by the second polycrystalline silicon film 109.

Next, as shown in FIG. 4C, in the memory element region, the second polycrystalline silicon film 109 and the first polycrystalline silicon film 109 are formed.
The second polycrystalline silicon film 106 and the first polycrystalline silicon film 106 which are patterned are selectively etched by using the fourth resist pattern 110 as a mask for the polycrystalline silicon film 106 and the trap film 103 of FIG. And forming a first gate electrode made of, and masking a fourth resist pattern 110 with respect to the second polycrystalline silicon film 109, the first polycrystalline silicon film 106 and the insulating film 105 in the logic circuit region. The patterned second polycrystalline silicon film 10 is formed by selectively etching the second polycrystalline silicon film 10.
A second gate electrode composed of the first polycrystalline silicon film 106 and the first polycrystalline silicon film 106 is formed.

Next, as shown in FIG. 5, by removing the fourth resist pattern 110, the semiconductor memory device according to the first embodiment is obtained.

According to the first embodiment, the trap film 10
3 is removed, the first polycrystalline silicon film 106 is deposited, and then the first polycrystalline silicon film 106 and the semiconductor substrate 10 are removed.
Since the element isolation trench 108a is formed in the logic circuit region by performing selective etching on 0, a residue composed of the trap film 103 is not generated on the side surface of the trench element isolation 108, so that the transistor characteristics in the logic circuit region are stable. To do.

Further, by using the alignment mark 101A, impurities are implanted in the memory element region and impurities in the logic circuit region, and the trap film 103 is selectively etched.
It is not necessary to use 8 as an alignment mark. Therefore, it becomes easy to form the element isolation trench 108a after depositing the trap film 103.

The first gate electrode formed in the memory element region and the second gate electrode formed in the logic circuit region are connected to the first polycrystalline silicon film 106 and the second polycrystalline silicon film. It can be configured by the same laminated film including 109.

Further, since the insulating film 105 serving as the gate insulating film is formed after the impurity is implanted in the logic circuit region, the reliability of the gate insulating film can be secured.

Incidentally, in the first embodiment, the first polycrystalline silicon film 106 and the second polycrystalline silicon film 10 are formed.
In No. 9, a polycrystalline silicon film doped with impurities is deposited, but instead of this, a polycrystalline silicon film not doped with impurities may be deposited and then doped with impurities.

In addition, the first polycrystalline silicon film 106 and the second polycrystalline silicon film 109 in the first embodiment.
Instead of this, an amorphous silicon film may be used.

Further, instead of the second polycrystalline silicon film 109 in the first embodiment, a conductive film having a metal film or a silicide film may be used.

Further, in the first embodiment, the n-type memory element is formed in the memory element region, but instead of this, a p-type memory element may be formed.

(Second Embodiment) A semiconductor memory device and a method of manufacturing the same according to a second embodiment of the present invention will be described below with reference to FIGS. 6 (a) to 6 (c) and 7 (a) to 7 (c). , Fig. 8 (a)-(c)
, FIG. 9 (a)-(c) and FIG. 10 (a)-(c). 6 (a)-(c), 7 (a)-(c), 8 (a)-(c), 9 (a)-(c), and 10 (a), (b). ), The drawing on the left side shows the memory element area, the drawing on the center shows the logic circuit area, the drawing on the right side shows the alignment mark area, and the drawing on the left side in FIG. 10 (c) shows the memory element area. And the drawing on the right side shows the logic circuit area.

First, as shown in FIG. 6A, a silicon oxide film 201 having a thickness of about 200 nm is deposited on a semiconductor substrate 200 made of a silicon substrate, and then, as shown in FIG.
As shown in (b), the silicon oxide film 201 is patterned to form an alignment mark 201A in the alignment mark region.

Next, as shown in FIG. 6C, after forming a first resist pattern 202 with a first photomask (not shown) aligned using the alignment mark 201A, The first resist pattern 202 is formed on the memory element region of the semiconductor substrate 200.
Is used as a mask to perform impurity implantation for controlling the threshold voltage of the memory element region.

Next, as shown in FIG. 7A, the entire surface of the semiconductor substrate 200 is formed of a laminated film of, for example, a silicon oxide film, a silicon nitride film, and a silicon oxide film.
A trap film 203 having a total film thickness of 0 nm is deposited.

Next, as shown in FIG. 7B, after forming a second resist pattern 204 by a second photomask (not shown) aligned using the alignment mark 201A, The second resist pattern 204 is formed on the memory element region of the semiconductor substrate 200.
Is used as a mask to remove n-type impurities, for example, 1 × 10 ¹⁵ cm
Implantation is performed at a dose of ⁻² to 1 × 10 ¹⁶ cm ⁻² to form an n-type impurity diffusion layer 205 to be a bit line. Then, the trap film 203 is selectively etched using the second resist pattern 204 as a mask to remove the upper portion of the trap film 203 above the n-type impurity diffusion layer 205. Either the impurity implantation or the selective etching performed using the second resist pattern 204 as a mask may be performed first.

Next, as shown in FIG. 7C, after removing the second resist pattern 204, a LOCOS isolation region 206 is formed in the memory element region by a thermal oxidation method.

Next, as shown in FIG. 8A, after forming a third resist pattern 207 by a third photomask (not shown) aligned using the alignment mark 201A, Impurity implantation for controlling the threshold voltage of the logic circuit region is performed using the third resist pattern 207 as a mask, and then FIG.
As shown in (b), the trap film 203 is selectively etched by using the third resist pattern 207 as a mask to remove the trap film 203 in the logic circuit region. Either the impurity implantation or the selective etching performed using the third resist pattern 207 as a mask may be performed first.

Next, as shown in FIG. 8C, the logic circuit region on the surface of the semiconductor substrate 200 is oxidized to form an insulating film 208 having a thickness of 2 nm to 25 nm and serving as a gate insulating film. Then, as shown in FIG. 9 (a), phosphorus is, for example, 1 × 10 ²⁰ over the entire surface of the semiconductor substrate 200.
cm ⁻³ to 1 × 10 ²¹ cm ⁻³ doped and for example 150
A first polycrystalline silicon film 209 having a thickness of nm to 300 nm is deposited.

Next, as shown in FIG. 9B, in the logic circuit region, the semiconductor substrate 200, the insulating film 208 and the first film are formed.
The polycrystalline silicon film 209 of is selectively etched using the fourth resist pattern 210 as a mask to form an element isolation trench 212a. By doing so, in the logic circuit region, the first polycrystalline silicon film 209 is isolated by the element isolation trench 212a.

Next, as shown in FIG. 9C, an insulating film is buried in the element isolation trench 212a to form the trench element isolation 21.
Form 2. In this case, the height position of the upper surface of the trench element isolation 212 and the height position of the upper surface of the first polycrystalline silicon film 209 are made substantially equal.

Next, as shown in FIG. 10 (a), phosphorus is, for example, 1 × 10 ²⁰ c over the entire surface of the semiconductor substrate 200.
m ⁻³ to 1 × 10 ²¹ cm ⁻³ doped and, for example, 150 n
A second polycrystalline silicon film 213 having a thickness of m to 300 nm is deposited. In this way, the element isolation groove 21
The first polycrystalline silicon films 209 which are separated from each other by 2a and the trench element isolation 212 are electrically connected to each other by the second polycrystalline silicon film 213.

Next, as shown in FIG. 10B, in the memory element region, a fifth resist is applied to the second polycrystalline silicon film 213, the first polycrystalline silicon film 209 and the trap film 203. Selective etching is performed using the pattern 214 as a mask to form a first gate electrode composed of the patterned second polycrystalline silicon film 213 and the first polycrystalline silicon film 209, and in the logic circuit region, , The second polycrystalline silicon film 213, the first polycrystalline silicon film 209, and the insulating film 208 are selectively etched using the fifth resist pattern 214 as a mask to form the patterned second polycrystalline film. Silicon film 2
A second gate electrode made of 13 and the first polycrystalline silicon film 209 is formed.

Next, as shown in FIG. 10C, the fifth resist pattern 214 is removed to obtain the semiconductor memory device according to the second embodiment.

According to the second embodiment, since the alignment mark 201A is used to implant impurities into the logic circuit region and selectively etch the trap film 203, it is necessary to use the trench element isolation 212 as an alignment mark. There is no. Therefore, the trap film 2
It becomes easy to form the element isolation groove 212a after depositing 03.

In the second embodiment, the first polycrystalline silicon film 209 and the second polycrystalline silicon film 21 are used.
In No. 3, a polycrystalline silicon film doped with impurities is deposited. However, instead of this, a polycrystalline silicon film not doped with impurities may be deposited and then the impurities may be doped.

Further, the first polycrystalline silicon film 209 and the second polycrystalline silicon film 213 in the second embodiment.
Instead of this, an amorphous silicon film may be used.

Further, a conductive film having a metal film or a silicide film may be used instead of the second polycrystalline silicon film 213 in the second embodiment.

Further, although the n-type memory element is formed in the memory element region in the second embodiment, a p-type memory element may be formed instead.

(Third Embodiment) A semiconductor memory device according to a third embodiment of the present invention and a method of manufacturing the same will be described with reference to FIGS. 11 (a) to 11 (d) and 12 (a) to 12 (d). , Fig. 13 (a)
(D) and FIG. 14 will be described. Incidentally, FIG.
In FIGS. 12A to 12D, FIGS. 12A to 12D, FIGS. 13A to 13D, and 14, the left drawing shows the memory element area and the right drawing shows the logic circuit area. Is shown.

First, as shown in FIG. 11A, after implanting an impurity for controlling the threshold voltage of the memory element region over the entire surface of the semiconductor substrate 300 made of a silicon substrate, FIG. As shown in b), a trap film 301 is deposited over the entire surface of the semiconductor substrate 300, for example, a stacked film of a silicon oxide film, a silicon nitride film, and a silicon oxide film and having a total film thickness of 30 nm. .

Next, as shown in FIG. 11C, with respect to the memory element region of the semiconductor substrate 300, using the first resist pattern 302 as a mask, n-type impurities such as 1
Implantation is performed at a dose amount of × 10 ¹⁵ cm ^-2 to 1 × 10 ¹⁶ cm ^-2 to form an n-type impurity diffusion layer 303 that will become a bit line. After that, the n-type impurity diffusion layer 303 in the trap film 301 is selectively etched by using the first resist pattern 302 as a mask for the trap film 301.
Remove the upper part of. The first resist pattern 3
Either the implantation of impurities or the selective etching performed using 02 as a mask may be performed first.

Next, as shown in FIG. 11D, after removing the first resist pattern 302, a thermal oxidation method is used.
A LOCOS isolation region 304 is formed in the memory element region.

Next, as shown in FIG. 12 (a), the LOCO
A first photomask aligned by using the S isolation region 304 as an alignment mark (not shown)
Thus, a second resist pattern 305 is formed. Next, after implanting impurities for controlling the threshold voltage of the logic circuit region into the logic circuit region of the semiconductor substrate 300 using the second resist pattern 305 as a mask, FIG. As shown in FIG. 3, the trap film 301 is selectively etched using the second resist pattern 305 as a mask to remove the trap film 30 in the logic circuit region.
Remove 1. Either the impurity implantation or the selective etching performed using the second resist pattern 305 as a mask may be performed first.

Next, as shown in FIG. 12C, the logic circuit region on the surface of the semiconductor substrate 300 is oxidized to form an insulating film 306 having a thickness of 2 nm to 25 nm and serving as a gate insulating film. After that, as shown in FIG. 12 (d), phosphorus is, for example, 1 × 1 over the entire surface of the semiconductor substrate 300.
0 ²⁰ cm ^-3 to 1 × 10 ²¹ cm ^-3 doped and for example 1
A first polycrystalline silicon film 307 having a thickness of 50 nm to 300 nm is deposited.

Next, as shown in FIG. 13 (a), the LOCO
A second photomask (not shown) aligned using the S separation region 304 as an alignment mark.
Thus, a third resist pattern 308 is formed. Next, in the logic circuit region, the semiconductor substrate 300, the insulating film 306, and the first polycrystalline silicon film 307 are formed into a third layer.
Selective etching is performed using the resist pattern 308 as a mask to form an element isolation groove 310a. By doing so, in the logic circuit region, the first polycrystalline silicon film 307 is separated by the element separation groove 310a.

Next, as shown in FIG. 13B, an insulating film is embedded in the element isolation trench 310a to form the trench element isolation 3
Form 10. In this case, the height position of the upper surface of the trench element isolation 310 and the height position of the upper surface of the first polycrystalline silicon film 307 are made substantially equal.

Next, as shown in FIG. 13 (c), phosphorus is, for example, 1 × 10 ²⁰ c over the entire surface of the semiconductor substrate 300.
m ⁻³ to 1 × 10 ²¹ cm ⁻³ doped and, for example, 150 n
A second polycrystalline silicon film 311 having a thickness of m to 300 nm is deposited. In this way, the element isolation groove 31
The first polycrystalline silicon films 307 separated by 0a and the trench element isolation 310 are electrically connected to each other by the second polycrystalline silicon film 311.

Next, as shown in FIG. 13D, in the memory element region, a fourth resist is applied to the second polycrystalline silicon film 311, the first polycrystalline silicon film 307 and the trap film 301. Selective etching is performed using the pattern 312 as a mask to form a first gate electrode composed of the patterned second polycrystalline silicon film 311 and the first polycrystalline silicon film 307, and in the logic circuit region, , The second polycrystalline silicon film 311, the first polycrystalline silicon film 307, and the insulating film 306 are selectively etched using the fourth resist pattern 312 as a mask to form a patterned second polycrystalline film. Silicon film 3
A second gate electrode made of 11 and the first polycrystalline silicon film 307 is formed.

Next, as shown in FIG. 14, by removing the fourth resist pattern 312, the semiconductor memory device according to the third embodiment is obtained.

Incidentally, in the third embodiment, the first polycrystalline silicon film 307 and the second polycrystalline silicon film 31 are used.
In No. 1, a polycrystalline silicon film doped with impurities is deposited. However, instead of this, a polycrystalline silicon film not doped with impurities may be deposited and then the impurities may be doped.

The first polycrystalline silicon film 307 and the second polycrystalline silicon film 311 in the third embodiment are also included.
Instead of this, an amorphous silicon film may be used.

Further, instead of the second polycrystalline silicon film 311 in the third embodiment, a conductive film having a metal film or a silicide film may be used.

Further, although the n-type memory element is formed in the memory element region in the third embodiment, a p-type memory element may be formed instead of the n-type memory element.

(Fourth Embodiment) A semiconductor memory device and a method of manufacturing the same according to a fourth embodiment of the present invention will be described below with reference to FIGS. 15 (a) to 15 (e) and 16 (a) to 16 (d). , Figure 17 (a)
.About. (D) and FIGS. 18 (a) to 18 (d).
15 (a) to (e), 16 (a) to 16 (d), and 17 (a)
18 (d) and 18 (a) -18 (d), the left drawing shows the memory element region and the right drawing shows the logic circuit region.

First, as shown in FIG. 15A, a pad oxide film 401 and a silicon nitride film 402 are sequentially deposited over the entire surface of a semiconductor substrate 400 made of a silicon substrate.

Next, as shown in FIG.
The first layer for the oxide film 401 and the silicon nitride film 402.
Selective etching is performed using the dist pattern 403 as a mask.
After that, for the memory device area of the semiconductor substrate 400,
Then, using the first resist pattern 403 as a mask, n
Type impurities such as 1 × 10¹⁵cm^-2~ 1 x 10¹⁶cm
^-2N-type impurity that becomes a bit line by implanting with a dose of
A substance diffusion layer 404 is formed. The first resist pattern
Selective etching and impurity using mask 403 as a mask
Either of the injection of the substance and the injection may be performed first.

Next, as shown in FIG. 15C, after removing the first resist pattern 403, as shown in FIG. 15D, the LOCOS is formed in the memory element region by the thermal oxidation method.
An isolation region 405 is formed, and then the silicon nitride film 402 is removed as shown in FIG.

Next, as shown in FIG. 16 (a), the LOCO
A first photomask (not shown) aligned using the S separation region 405 as an alignment mark.
After the second resist pattern 406 is formed by, the impurity implantation for controlling the threshold voltage of the memory element region is performed on the memory element region of the semiconductor substrate 400 by using the second resist pattern 406 as a mask. To do.

Next, as shown in FIG. 16B, after the second resist pattern 406 and the pad oxide film 401 are removed, as shown in FIG. 16C, the entire surface of the semiconductor substrate 400 is covered. As a result, for example, a trap film 407 made of a laminated film of a silicon oxide film, a silicon nitride film and a silicon oxide film and having a total film thickness of 30 nm is deposited.

Next, as shown in FIG. 16 (d), the LOCO
A second photomask aligned by using the S isolation region 405 as an alignment mark (not shown)
Thus, a third resist pattern 408 is formed. Next, after implanting impurities for controlling the threshold voltage of the logic circuit region into the logic circuit region of the semiconductor substrate 400 using the third resist pattern 408 as a mask, FIG. As shown in FIG. 3, the trap film 407 is selectively etched using the third resist pattern 408 as a mask to remove the trap film 40 in the logic circuit region.
Remove 7. Either the impurity implantation or the selective etching performed using the third resist pattern 408 as a mask may be performed first.

Next, as shown in FIG. 17B, the logic circuit region on the surface of the semiconductor substrate 400 is oxidized to form an insulating film 409 having a thickness of, for example, 2 nm to 25 nm and serving as a gate insulating film. After that, as shown in FIG. 17 (c), phosphorus is, for example, 1 × 1 over the entire surface of the semiconductor substrate 400.
0 ²⁰ cm ^-3 to 1 × 10 ²¹ cm ^-3 doped and for example 1
A first polycrystalline silicon film 410 having a thickness of 50 nm to 300 nm is deposited.

Next, as shown in FIG. 17 (d), the LOCO
A third photomask (not shown) aligned using the S separation region 405 as an alignment mark.
Thus, a fourth resist pattern 411 is formed. Next, in the logic circuit region, the semiconductor substrate 400, the insulating film 409, and the first polycrystalline silicon film 410 are formed into a fourth layer.
Selective etching is performed using the resist pattern 411 as a mask to form the element isolation trench 413a. By doing so, in the logic circuit region, the first polycrystalline silicon film 410 is separated by the element separation groove 413a.

Next, as shown in FIG. 18A, an insulating film is buried in the element isolation trench 413a to form the trench element isolation 4
13 is formed. In this case, the height position of the upper surface of the trench element isolation 413 and the height position of the upper surface of the first polycrystalline silicon film 410 are made substantially equal.

Next, as shown in FIG. 18 (b), phosphorus is, for example, 1 × 10 ²⁰ c over the entire surface of the semiconductor substrate 400.
m ⁻³ to 1 × 10 ²¹ cm ⁻³ doped and, for example, 150 n
A second polycrystalline silicon film 414 having a thickness of m to 300 nm is deposited. In this way, the element isolation groove 41
The first polycrystalline silicon films 410 separated from each other by 3a and the trench element isolation 413 are electrically connected to each other by the second polycrystalline silicon film 414.

Next, as shown in FIG. 18C, in the memory element region, a fifth resist is applied to the second polycrystalline silicon film 414, the first polycrystalline silicon film 410 and the trap film 407. Selective etching is performed using the pattern 415 as a mask to form a first gate electrode composed of the patterned second polycrystalline silicon film 414 and the first polycrystalline silicon film 410, and in the logic circuit region, , The second polycrystalline silicon film 414, the first polycrystalline silicon film 410, and the insulating film 409 are selectively etched using the fifth resist pattern 415 as a mask to form the patterned second polycrystalline film. Silicon film 4
A second gate electrode made of 14 and the first polycrystalline silicon film 410 is formed.

Next, as shown in FIG. 18D, the fifth resist pattern 415 is removed to obtain the semiconductor memory device according to the fourth embodiment.

According to the fourth embodiment, the LOCOS isolation region 405 is used as an alignment mark to inject the impurity into the memory element region and the impurity into the logic circuit region. Therefore, the trench element isolation 413 is used as the alignment mark. No need. Therefore, it becomes easy to form the element isolation groove 413a after depositing the trap film 407.

Incidentally, in the fourth embodiment, the first polycrystalline silicon film 410 and the second polycrystalline silicon film 41.
In No. 4, a polycrystalline silicon film doped with impurities is deposited, but instead of this, a polycrystalline silicon film not doped with impurities may be deposited and then doped with impurities.

In addition, the first polycrystalline silicon film 410 and the second polycrystalline silicon film 414 in the fourth embodiment.
Instead of this, an amorphous silicon film may be used.

Further, instead of the second polycrystalline silicon film 414 in the fourth embodiment, a conductive film having a metal film or a silicide film may be used.

Further, although the n-type memory element is formed in the memory element region in the fourth embodiment, a p-type memory element may be formed instead of the n-type memory element.

[0113]

According to the semiconductor memory device and the method of manufacturing the same of the present invention, the first conductive film is deposited after removing the portion of the trap film deposited in the logic circuit region, and then the first conductive film is deposited. Since the element isolation groove can be formed in the logic circuit region by performing selective etching on the conductive film and the semiconductor substrate, the residue formed of the trap film is not generated on the side surface of the trench element isolation. Stabilize.

[Brief description of drawings]

1A to 1C are cross-sectional views illustrating each step of the method for manufacturing a semiconductor memory device according to the first embodiment.

2A to 2C are cross-sectional views illustrating each step of the method for manufacturing the semiconductor memory device according to the first embodiment.

3A to 3C are cross-sectional views illustrating each step of the method for manufacturing the semiconductor memory device according to the first embodiment.

4A to 4C are cross-sectional views illustrating each step of the method for manufacturing the semiconductor memory device according to the first embodiment.

FIG. 5 is a plan view of the semiconductor memory device according to the first embodiment.

6A to 6C are cross-sectional views illustrating each step of the method for manufacturing the semiconductor memory device according to the second embodiment.

7A to 7C are cross-sectional views illustrating each step of the method for manufacturing the semiconductor memory device according to the second embodiment.

8A to 8C are cross-sectional views illustrating each step of the method for manufacturing the semiconductor memory device according to the second embodiment.

9A to 9C are cross-sectional views for explaining each step of the method for manufacturing the semiconductor memory device according to the second embodiment.

10A and 10B are cross-sectional views illustrating each step of the method for manufacturing the semiconductor memory device according to the second embodiment,
FIG. 7C is a plan view of the semiconductor memory device according to the second embodiment.

11A to 11D are cross-sectional views illustrating each step of the method for manufacturing the semiconductor memory device according to the third embodiment.

12A to 12D are cross-sectional views illustrating each step of the method for manufacturing the semiconductor memory device according to the third embodiment.

13A to 13D are cross-sectional views illustrating each step of the method for manufacturing the semiconductor memory device according to the third embodiment.

FIG. 14 is a plan view of a semiconductor memory device according to a third embodiment.

15A to 15E are cross-sectional views illustrating each step of the method for manufacturing the semiconductor memory device according to the fourth embodiment.

16A to 16D are cross-sectional views illustrating each step of the method for manufacturing the semiconductor memory device according to the fourth embodiment.

17A to 17D are cross-sectional views illustrating each step of the method for manufacturing the semiconductor memory device according to the fourth embodiment.

18A to 18C are cross-sectional views illustrating each step of the method for manufacturing the semiconductor memory device according to the fourth embodiment,
FIG. 7D is a plan view of the semiconductor memory device according to the fourth embodiment.

19A to 19D are cross-sectional views illustrating each step of a conventional method for manufacturing a semiconductor memory device.

20A to 20D are cross-sectional views illustrating each step of a conventional method for manufacturing a semiconductor memory device.

21A to 21C are cross-sectional views illustrating each step of a conventional method for manufacturing a semiconductor memory device, and FIG. 21D is a plan view of the conventional semiconductor memory device.

[Explanation of symbols]

100 semiconductor substrate 101 Silicon oxide film 101A alignment mark 102 first resist pattern 103 trap film 104 second resist pattern 105 insulating film 106 first polycrystalline silicon film 107 third resist pattern 108 trench isolation 108a Element isolation groove 109 second polycrystalline silicon film 110 Fourth resist pattern 200 Semiconductor substrate 201 Silicon oxide film 201A alignment mark 202 first resist pattern 203 trap film 204 second resist pattern 205 n-type impurity diffusion layer 206 LOCOS separation area 207 Third resist pattern 208 insulating film 209 First polycrystalline silicon film 210 Fourth resist pattern 212 trench isolation 212a Element isolation groove 213 Second polycrystalline silicon film 214 fifth resist pattern 300 semiconductor substrate 301 trap film 302 First resist pattern 303 n-type impurity diffusion layer 304 LOCOS separation area 305 Second resist pattern 306 insulating film 307 First polycrystalline silicon film 308 Third resist pattern 310 trench isolation 310a Element isolation groove 311 Second polycrystalline silicon film 312 Fourth resist pattern 400 semiconductor substrate 401 pad oxide film 402 Silicon nitride film 403 First resist pattern 404 n-type impurity diffusion layer 405 LOCOS separation area 406 second resist pattern 407 trap film 408 Third resist pattern 409 insulating film 410 First polycrystalline silicon film 411 Fourth resist pattern 413 trench isolation 413a Element isolation groove 414 Second polycrystalline silicon film 415 Fifth resist pattern

Front page continuation (51) Int.Cl. ⁷ Identification code FI theme code (reference) H01L 29/792 F term (reference) 5F046 AA20 EA13 EA14 EA15 EA19 EB01 EB05 5F083 EP17 EP18 EP23 JA33 NA01 NA02 NA06 PR01 PR43 PR53 ZA05 ZA12 5F101 BA45 BB05 BD35 BD37 BH21 BH30

Claims (12)

[Claims] 1. A semiconductor memory device comprising a memory element for storing information on a semiconductor substrate to store information in a trap film, and a logic circuit, wherein a gate electrode constituting the logic circuit comprises: A plurality of first conductive films which are separated from each other by trench element isolation formed in the logic circuit region, and whose upper surface has a height position substantially equal to the upper surface height of the trench element isolation; A semiconductor memory characterized by comprising a trench element isolation and a second conductive film which is formed over the plurality of first conductive films and electrically connects the plurality of first conductive films to each other. apparatus. 2. The semiconductor memory device according to claim 1, wherein the gate electrode formed in the memory element region is composed of the first conductive film and the second conductive film. 3. The semiconductor memory device according to claim 1, further comprising an alignment mark provided in a region other than the logic circuit region and the memory element region on the semiconductor substrate. 4. A method for manufacturing a semiconductor memory device, comprising: a semiconductor substrate; and a memory element that stores information by accumulating charges in a trap film, and a logic circuit. A first step of depositing a trap film over the entire surface, a second step of removing a portion of the trap film deposited in the logic circuit region, and a first conductivity over the entire surface of the semiconductor substrate. A third step of depositing a film; a fourth step of selectively etching the first conductive film and the semiconductor substrate to form an element isolation groove in the logic circuit region; A fifth step of burying an insulating film in the groove to form a trench element isolation, and a second conductive film is deposited over the entire surface of the semiconductor substrate, whereby the element isolation trench is formed in the fourth step By And a sixth step of electrically connecting the first conductive films separated from each other by the second conductive film. 5. A step of forming an insulating film to be a gate insulating film in the logic circuit region on the semiconductor substrate between the second step and the third step, the third step The method of manufacturing a semiconductor memory device according to claim 4, further comprising: depositing the first conductive film on the insulating film in the logic circuit region. 6. After the sixth step, a first gate electrode made of the first conductive film and the second conductive film is formed in the memory element region, and at the same time in the logic circuit region, The method for manufacturing a semiconductor device according to claim 5, further comprising a step of forming a second gate electrode made of the first conductive film and the second conductive film. 7. The method according to claim 5, further comprising a step of implanting an impurity into the logic circuit region of the semiconductor substrate between the first step and the step of forming the insulating film. A method for manufacturing the semiconductor memory device described. 8. The semiconductor according to claim 4, further comprising a step of implanting an impurity into the memory element region and the logic circuit region of the semiconductor substrate before the first step. Storage device manufacturing method. 9. A step of forming an alignment mark on the semiconductor substrate before the first step, and a first photomask formed by a first photomask aligned using the alignment mark. The step of injecting impurities into the memory element region of the semiconductor substrate using the resist pattern as a mask, and the second resist pattern formed by the second photomask aligned using the alignment mark as a mask, 5. A method of manufacturing a semiconductor memory device according to claim 4, further comprising the step of implanting an impurity into the logic circuit region of the semiconductor substrate. 10. A method of forming an element isolation region in the memory element region prior to the first step, wherein the first photomask is aligned using the element isolation region as an alignment mark. Formed by a step of implanting an impurity into the memory element region of the semiconductor substrate using the formed first resist pattern as a mask, and a second photomask aligned using the element isolation region as an alignment mark. 5. The method of manufacturing a semiconductor memory device according to claim 4, further comprising the step of implanting an impurity into the logic circuit region of the semiconductor substrate using the second resist pattern as a mask. 11. A step of forming an alignment mark on the semiconductor substrate prior to the second step, wherein the second step is formed by a photomask aligned using the alignment mark. 5. The method for manufacturing a semiconductor memory device according to claim 4, wherein the method is performed using the resist pattern. 12. A step of forming an element isolation region in the memory element region prior to the second step, wherein the second step is aligned using the element isolation region as an alignment mark. The method of manufacturing a semiconductor memory device according to claim 4, wherein the method is performed using a resist pattern formed by a photomask.