JPH09321279A - Semiconductor device, its manufacture and semiconductor device forming laminated body - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device and its manufacturing method wherein injection of an electric charge into a gate insulating film is reduced in a formation process of a gate electrode by dry etching. SOLUTION: A silicon oxide film 102, acting as gate insulating films, and a poly silicon film 13 are accumulated on a semiconductor substrate 100. An opening part 104 which penetrates each film 103 and 102 and reaches an electric charge discharging area 105 in the semiconductor substrate is opened, and a tungsten silicide film 106 is accumulated in the opening part 104 and on a poly silicon film 13a. When each film 106 and 103a are patterned by dry etching to form a gate electrode 108, an electric charge moves from the gate electrode under formation to each film 106 and 103a, and from a buried layer 106a in the opening part to the electric charge discharging area 105 of the semiconductor substrate. So that, injection of the electric charge into the gate insulating film 102 is suppressed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a laminated body for forming a semiconductor device having a MIS transistor, a semiconductor device and a method for manufacturing the same.

[0002]

2. Description of the Related Art In recent years, the degree of integration of semiconductor integrated circuits having MOS transistors has greatly advanced, and it is necessary to miniaturize the MOS transistors themselves in order to realize high integration. Further, with the miniaturization of MOS transistors and the reduction of operating voltage, the thickness of a gate insulating film interposed between a gate electrode and a channel region of a substrate has been reduced. As a result, a MOS gate of the 0.25 μm rule uses a thin gate insulating film of 6 to 8 nm.

By the way, the gate insulating film in a MOS transistor is an important member that influences the operating characteristics of the transistor, and as the gate insulating film becomes thinner as described above, its deterioration adversely affects the characteristics of the MOS transistor. Is becoming more serious. Therefore, not only deterioration in use of the semiconductor device after manufacturing but also deterioration of the gate insulating film due to damage given in the manufacturing process of the semiconductor device has become a problem. In particular, the dry etching process for forming the gate electrode is a process in which ion particles collide with a film (generally a polysilicon film) forming the gate electrode to selectively remove the film. At that time, charges are injected into the film by the ion flux. In addition, since the etching process is a process of breaking the bonds between the atoms that form the film,
A charge is also generated by the breaking of the interatomic bond. The breakdown and deterioration of the gate insulating film caused by such charges being injected into the gate insulating film from the polysilicon film or the like cannot be ignored.

In order to solve such a problem, it has been conventionally practiced to suppress the amount of charges injected into the gate electrode in the dry etching process. In the dry etching process, the ion flux incident on the wafer from the plasma and the reliability life of the gate insulating film (QBD
As shown in FIG. 15, the relationship between the value and the total charge amount for dielectric breakdown is such that the reliability life decreases as the amount of ion flux increases. Therefore, it can be seen that by controlling the plasma state and reducing the incident ion flux, damage in the dry etching process can be reduced and the reliability life can be maintained high.

On the other hand, as shown in FIGS. 14 (a) and 14 (b), the antenna wiring is formed so as to relax the voltage applied to the gate electrode when forming the upper wiring and prevent the deterioration of the gate insulating film. The technology is known.

First, as shown in FIG. 14A, an n-type diffusion layer 201 is formed in a semiconductor substrate, and an n-type diffusion layer 20 in a transistor formation region surrounded by an element isolation 202 is formed.
1 on which a gate insulating film 203 and a gate electrode 204 are formed, and an n-type diffusion layer 201 separate from the transistor formation region is formed.
A p-type diffusion layer 208 is formed and placed therein. After that, an interlayer insulating film 205 is formed over the substrate, the interlayer insulating film 205 is opened, and a contact hole 207 reaching the gate electrode 204 and a contact hole 208 reaching the p-type diffusion layer 208 are formed. Next, as shown in FIG. 14B, an antenna wiring 209 is formed in each of the contact holes 207 and 208 and over the interlayer insulating film 205.

That is, when the wiring 209 is formed by dry etching, the gate electrode 2 is formed by the charges carried by the gate electrode 204 via the ion flux Iof.
The voltage of 04 is increased and charges are injected into the gate insulating film 203 so as to escape into the substrate through the antenna wiring 209.

[0008]

However, reducing the incident ion flux as described above is
When considering a mass production process, there is a problem in terms of process cost. For example, in the dry etching process, the ion flux incident on the wafer is almost proportional to the etching rate. That is, if the ion flux is reduced in order to reduce damage to the gate insulating film, the etching rate is also lowered, so that the time required for the dry etching step increases and the process cost increases.

On the other hand, also in the method of providing the wiring to be the antenna described above, in the step shown in FIG. 14A, the gate insulating film 203 is formed through the gate electrode 204 when the contact hole reaching the gate electrode is formed. The charge is injected. Moreover, since there is a difference in depth between the contact hole 206 to the gate electrode 204 and the contact hole 207 to the p-type diffusion region 208, the gate electrode 204 is plasma until the contact hole 207 reaches the p-type diffusion region 208. The amount of charges injected into the gate insulating film 203 is considerably large due to the exposure to the ion flux Iof from. Further, although the gate electrode 204 is already formed in the state shown in FIG. 14A, when dry etching for forming the gate electrode 204 is performed in the previous step, gate insulation is performed via the gate electrode 204. Membrane 203
A considerable amount of charge will be injected into. Therefore, FIG.
In the methods shown in FIGS. 4 (a) and 4 (b), if the size of the transistor is further miniaturized and the thickness of the gate insulating film is further reduced, it may not be possible to effectively prevent the deterioration of the life characteristic of the gate insulating film.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a semiconductor device having a MIS transistor, a stacked body for forming the semiconductor device, and a method for manufacturing the semiconductor device, in which a gate electrode is provided. By taking measures that can suppress the injection of charges into the gate insulating film during formation, it is possible to prevent deterioration of the life characteristics of the gate electrode and thereby improve the reliability of the semiconductor device.

[0011]

In order to achieve the above object, in the present invention, means relating to the method for manufacturing a semiconductor device according to claims 1 to 20 and semiconductor according to claims 21 to 29 are provided. Means relating to the device and means relating to the laminated body for forming a semiconductor device according to claim 30 are provided.

A method of manufacturing a semiconductor device according to claim 1 is
A first step of forming an insulating film on the first and second regions of a semiconductor substrate having a first region for forming a MIS transistor and a second region for releasing an electric charge; The second step of forming the first conductive film on the insulating film, and the second step of penetrating the first conductive film and the insulating film.
A third step of forming an opening reaching the area of the second conductive layer, a fourth step of forming a second conductive film in the opening and on the first conductive film, and the first and second A fifth step of patterning the conductive film to form a gate electrode above the first region by the first and second conductive films.

According to this method, in the fifth step, while the gate electrode is being formed, while the second conductive film remains in the region excluding the gate electrode, openings are made from the first and second conductive films. Electric charges move into the semiconductor substrate through the second conductive film embedded in the portion. In addition, even after the second conductive film in the region excluding the gate electrode is removed, the charges move from the first conductive film into the semiconductor substrate through the second conductive film embedded in the opening. Therefore, the charges escape to the semiconductor substrate without accumulating the charges in the gate electrode, so that the deterioration of the gate insulating film due to the injection of the charges into the gate insulating film can be suppressed. Therefore, a semiconductor device having a long reliability life is formed.

A method of manufacturing a semiconductor device according to claim 2 is
In Claim 1, In the said 5th process, the said 1st and 2nd conductive film is patterned so that a dummy electrode may be formed on the said 2nd area | region with the said 1st and 2nd conductive film. Is the way.

According to this method, the first dummy electrode is formed on the second region until the fifth step is completed.
Also, since the second conductive film remains, the electric resistance at the dummy electrode portion becomes small, and the amount of charge transfer to the semiconductor substrate increases. Therefore, the deterioration of the gate insulating film can be suppressed more reliably, and a semiconductor device having a longer reliability life can be formed.

A method of manufacturing a semiconductor device according to claim 3 is
3. The method according to claim 2, wherein in the fifth step, the first electrode is formed so that the gate electrode and the dummy electrode are continuous with each other.
And a method of patterning the second conductive film.

According to this method, the first and second layers are formed from the gate electrode to the inside of the semiconductor substrate until the fifth step is completed.
Since the electric charges move through the conductive film, the electric resistance in all the movement paths of the electric charges is further reduced, and the amount of electric charges transferred to the semiconductor substrate is further increased. Therefore,
Further, a semiconductor device having a long reliability life is formed.

A method of manufacturing a semiconductor device according to a fourth aspect is
4. The step of forming an interlayer insulating film on the substrate after the fifth step, the first connection hole penetrating the interlayer insulating film to reach the gate electrode, and And a step of forming an antenna wiring extending in each of the connection holes and on the interlayer insulating film.

According to this method, in the step of forming the first and second connection holes, after the first connection hole is opened, the second connection hole is formed.
Since the gate electrode receives the ion flux from the plasma until the connection hole is opened, charges tend to be accumulated in the gate electrode being formed. Since the charges move into the semiconductor substrate via the first conductive film, the increase in voltage due to the accumulation of charges in the gate electrode is suppressed. Also, when forming the antenna wiring, not only the third region but also the second electrode from the gate electrode is formed.
Since the charges move to the semiconductor substrate through the region of (1), the effect of suppressing the voltage rise of the gate electrode becomes extremely large.
Therefore, even when the upper layer wiring is formed after the gate electrode is formed, it is possible to suppress the charge injection into the gate insulating film, and a semiconductor device having a long reliable life is formed.

A method of manufacturing a semiconductor device according to claim 5 is
In Claim 2, The said 5th process is a method of patterning the said 1st and 2nd conductive film so that the said gate electrode and the said dummy electrode may be isolate | separated from each other.

With this method, the same effect as that of the second aspect is achieved. Also, the dummy electrode can be used as a grounding terminal electrode.

A method of manufacturing a semiconductor device according to claim 6 is
The step of forming an interlayer insulating film on a substrate after the fifth step, and the first connection hole penetrating the interlayer insulating film to reach the gate electrode and reaching the dummy electrode according to claim 5. And a step of forming an antenna wiring extending in each of the connection holes and on the interlayer insulating film.

According to this method, in the step of forming the first and second connection holes, there is almost no difference in depth between the first connection hole and the second connection hole. Receive almost no Further, in the step of forming the antenna wiring, the electric charge in the antenna wiring can move into the semiconductor substrate through the third region. Therefore, even when the upper layer wiring is formed after the gate electrode is formed, it is possible to suppress the charge injection into the gate insulating film, and a semiconductor device having a long reliable life is formed.

A method of manufacturing a semiconductor device according to a seventh aspect is
The method according to claim 1 or 2, wherein the fourth step is performed after the third step.
Prior to the step (2), the method further comprises a step of implanting a high concentration impurity into the semiconductor substrate exposed in the second region.

A method of manufacturing a semiconductor device according to claim 8 is
In the method of claim 7, the conductivity type of the impurities implanted into the second region is the same as the conductivity type of the impurities in the region in contact with the second region in the semiconductor substrate.

A method of manufacturing a semiconductor device according to a ninth aspect is
In claim 7, the conductivity type of the impurities implanted into the second region is different from the conductivity type of the impurities in the region in contact with the second region in the semiconductor substrate.

According to the method of claim 7, 8 or 9, further reducing the electric resistance when electric charges are transferred from the second conductive film embedded in the opening into the semiconductor substrate through the second region. Will be possible.

According to a tenth aspect of the present invention, in the method of manufacturing a semiconductor device according to the first aspect, in the third step, the opening is formed also in a region for forming a separation trench surrounding the first region, Further, the semiconductor substrate is further dug to a predetermined depth in the opening to form a charge escape groove and a separation groove, respectively, and after the third step, the fourth step is performed.
Before the step of, the step of depositing an isolation insulating film in each of the groove portions and on the first conductive film; and the isolation insulating film exposing at least the upper surface of the first conductive film and 1
Removing at least a part of the conductive film, and flattening the substrate surface so as to leave the isolation insulating film inside and above each of the trenches, and the isolation for each of the trenches left. A step of removing the insulating film for separating the charge releasing groove portion of the insulating film; and in the fourth step, the separating film left above the first conductive film and the separating groove portion. This is a method of forming the second conductive film over the insulating film.

According to an eleventh aspect of the present invention, in the method of manufacturing a semiconductor device according to the tenth aspect, in the fifth step, a dummy electrode is formed on the second region by the first and second conductive films. Then, it is a method of patterning the first and second conductive films.

According to a twelfth aspect of the present invention, in the method of manufacturing a semiconductor device according to the eleventh aspect, in the fifth step, the gate electrode and the dummy electrode are connected to each other through the second conductive film. And a method of patterning the first and second conductive films.

According to a thirteenth aspect of the present invention, in the method of manufacturing a semiconductor device according to the eleventh aspect, in the fifth step, the first and second conductive films are formed so that the gate electrode and the dummy electrode are separated from each other. Is a method of patterning.

According to the methods of claims 10, 11, 12 and 13, the same effects as those of the above-mentioned claims 1, 2, 3 and 5 are exerted when manufacturing a semiconductor device having a trench isolation structure. .

According to a fourteenth aspect of the present invention, in the method of manufacturing a semiconductor device according to the tenth aspect, in the third step, the opening is formed also in a region where an alignment key is formed, and a semiconductor substrate in the region is predetermined. In the step of forming the alignment key groove by engraving to a depth and depositing the isolation insulating film, the isolation insulating film is also deposited in the alignment key groove, and in the step of flattening the substrate surface, In the step of leaving the separation insulating film inside and above the alignment key groove and removing the separation insulating film of the charge escape groove, the separation insulating film of the alignment key groove is removed, and In the fourth step, the second conductive film is deposited also in the alignment key groove, and in the fifth step, the first conductive film is formed inside and around the alignment key groove portion. Beauty is a second conductive film method of removing.

According to this method, it is possible to allow charges to escape into the semiconductor substrate from the groove for the alignment key, which has a particularly large groove width, so that the effect of suppressing the injection of charges into the gate insulating film becomes remarkable.

According to a fifteenth aspect of the present invention, in the method of manufacturing a semiconductor device according to the tenth, eleventh or fourteenth aspect, after the third step and before the fourth step, the charge escape groove portion of the semiconductor substrate is formed. The method further comprises the step of implanting a high concentration impurity into the second region forming the side wall and the bottom wall.

According to a sixteenth aspect of the present invention, in the method of manufacturing a semiconductor device according to the fifteenth aspect, the conductivity type of the impurities implanted into the second region is within a region in contact with the second region in the semiconductor substrate. This is the same method as the conductivity type of impurities.

According to a seventeenth aspect of the present invention, in the method of manufacturing a semiconductor device according to the fifteenth aspect, the conductivity type of the impurities injected into the second region is within a region in contact with the second region in the semiconductor substrate. This method is different from the conductivity type of impurities.

According to the method of claims 15, 16 and 17, the same effect as that of the above-mentioned claims 7, 8 and 9 can be obtained in the manufacturing process of the semiconductor device having the trench structure.

A method of manufacturing a semiconductor device according to an eighteenth aspect is the method according to the first, second, tenth or eleventh aspect, wherein the first conductive film is formed of a polysilicon film in the second step.

A semiconductor device manufacturing method according to a nineteenth aspect is the method according to the first, second, tenth or eleventh aspect, wherein the second conductive film is formed of a refractory metal film in the fourth step.

A semiconductor device manufacturing method according to a twentieth aspect is the method according to the first, second, tenth or eleventh aspect, wherein the second conductive film is formed of a polysilicon film in the fourth step.

According to the method of claim 18, 19 or 20,
The MI with good characteristics of the gate electrode while maintaining a small resistance to the movement of charges from the gate electrode to the semiconductor substrate.
It becomes possible to form an S transistor.

A semiconductor device according to a twenty-first aspect of the invention is a semiconductor substrate having a first region in which a MIS transistor is to be formed and a second region for releasing charges, and the first region and the second region. An insulating film that is formed on the insulating film and serves as a gate insulating film on the first region, a first conductive film formed on the insulating film, and penetrates the first conductive film and the insulating film. And is formed over the opening reaching the second region and within the opening and over the first conductive film,
A second conductive film in contact with the second region,
The first conductive film and the second conductive film form a gate electrode above the first region on the semiconductor substrate, while forming a dummy electrode above the second region.

With this structure, in the manufacturing process of the semiconductor device, the MIS transistor in which the amount of charges injected into the gate insulating film is small can be obtained by the action of the above-described claim 2. If the amount of charges injected into the gate insulating film in the manufacturing process of the MIS transistor is large, the amount of charges injected during use is added to the amount of injected charges, resulting in rapid destruction of the gate insulating film. In this respect, in the semiconductor device according to the present invention, the semiconductor device is used in a state where the amount of charges injected into the gate insulating film is small, so that the reliability life characteristic of the semiconductor device is improved.

A semiconductor device according to claim 22 is the semiconductor device according to claim 2.
1, the gate electrode and the dummy electrode are integrally formed by the first and second conductive films.

A semiconductor device according to claim 23 is the semiconductor device according to claim 2.
2, an interlayer insulating film formed on the gate electrode and the dummy electrode, a first connection hole penetrating the interlayer insulating film to reach the gate electrode, and an interlayer insulating film penetrating the interlayer insulating film. The semiconductor device further comprises a second connection hole reaching the third region of the semiconductor substrate and an antenna wiring extending in the first and second connection holes and on the interlayer insulating film.

A semiconductor device according to claim 24 is the semiconductor device according to claim 2.
1, the gate electrode and the dummy electrode are separated from each other.

A semiconductor device according to claim 25 is the semiconductor device according to claim 2.
4, the dummy electrode is used as a grounding terminal electrode.

A semiconductor device according to claim 26 is the semiconductor device according to claim 2.
5, an interlayer insulating film formed on the gate electrode and the dummy electrode, a first connection hole penetrating the interlayer insulating film to reach the gate electrode, and an interlayer insulating film penetrating the interlayer insulating film It further comprises a second connection hole reaching the dummy electrode, and an antenna wiring extending in the first and second connection holes and on the interlayer insulating film.

With the configurations of claims 22, 23, 24, and 26, the actions of the above-described claims 3, 4, 5, and 6 are achieved in the manufacturing process of the semiconductor device. Therefore, the reliability life characteristic of the semiconductor device is further improved.

According to the twenty-fifth aspect, the semiconductor device having the grounding terminal electrode can be obtained without increasing the number of steps.

A semiconductor device according to claim 27 is the semiconductor device according to claim 2.
1 is formed in the second region of the semiconductor substrate,
The semiconductor device further comprises a charge escape groove formed by digging the semiconductor substrate to a predetermined depth, a separation groove portion surrounding the first region, and a separation insulating film formed inside and above the separation groove portion, The first conductive film is formed at the same height as the isolation insulating film, and the second conductive film fills the charge escape groove.

With this structure, the semiconductor device having the trench isolation structure has the effect of the above-mentioned claim 21.

A semiconductor device according to claim 28 is the semiconductor device according to claim 2.
1 is configured such that the second region and the region in contact with the second region in the semiconductor substrate are in resistive contact.

A semiconductor device according to claim 29 is the semiconductor device according to claim 2.
1, the second region and the region in contact with the second region in the semiconductor substrate are configured so as to have a rectifying contact.

According to the twenty-eighth aspect or the twenty-ninth aspect, since the actions of the eighth and ninth aspects are exhibited in the manufacturing process of the semiconductor device, the reliability life characteristic of the semiconductor device is further improved.

A semiconductor device forming laminate according to a thirtieth aspect of the invention is a semiconductor substrate having a first region in which a MIS transistor is to be formed and a second region for releasing charges, and the first region and An insulating film formed on the second region and serving as a gate insulating film on the first region, a first conductive film formed on the insulating film, the first conductive film, and the The first conductive film and the second conductive film are provided with an opening penetrating the insulating film to reach the second region, and a second conductive film formed on at least the first conductive film. When patterning the conductive film to form the gate electrode,
It is configured that charges can move from the gate electrode being formed into the semiconductor substrate through the second region.

With this structure, in the process of manufacturing a semiconductor device using this laminated body, it is possible to suppress the injection of charges into the gate insulating film during the formation of the gate electrode, so that it is possible to manufacture a semiconductor device having a long reliability life. Can be offered.

[0059]

BEST MODE FOR CARRYING OUT THE INVENTION

(First Embodiment) First, a first embodiment will be described. FIG. 1 is a sectional view showing a manufacturing process of the semiconductor device according to the first embodiment.

As shown in FIG. 1A, on the n-type semiconductor substrate 100 on which the separating silicon oxide film 101 is formed,
After forming a silicon oxide film 102 having a thickness of about 6 nm to be a gate insulating film of a MOS transistor and further forming an n-type polysilicon film 103 having a thickness of about 100 nm to be a gate electrode on the silicon oxide film 102, the n-type polysilicon film 103 is formed. An opening is formed on a region on which an n-type semiconductor substrate 100 and a gate electrode are electrically connected to each other by a photolithography process to form a region for discharging charges into the substrate (hereinafter referred to as a charge releasing region). Photoresist film Rm1
To form

Next, as shown in FIG. 1B, dry etching is performed using the photoresist film Rm1 as a mask to form the polysilicon film 103 and the silicon oxide film 102.
Are selectively removed to form the opening 104 reaching the region where the charge escape region of the n-type semiconductor substrate 100 is to be formed. At this time, charges are carried to the n-type polysilicon film 103, but the opening region of the photoresist film Rm1 is small, and each conductive film is in a state where it is not patterned yet and has an extremely large area. The damage to the silicon oxide film 102 that becomes the above is almost negligible.

Next, in the step shown in FIG. 1C, after removing the photoresist film Rm1, for example, arsenic ions are implanted at a dose of 30 KeV with the polysilicon film 103a having the opening 104 formed as a mask. The amount is 5E1
The n-type semiconductor substrate 100 is implanted under the condition of about 5 / cm ^2.
A charge escape region 105 made of a high concentration n-type semiconductor is formed therein. At this time, arsenic ions are also implanted into the polysilicon film 103a. After that, for example, a tungsten silicide film 106 is formed as a refractory metal film on the entire surface of the substrate.
Is deposited to about 200 nm. At this time, the tungsten silicide film 106 also fills the opening 104, and this portion becomes the buried layer 106a.

Next, in the step shown in FIG. 1D, a photoresist film Rm2 is formed on the tungsten silicide film 106 by a photolithography step, the photoresist film Rm2 having an opening except for the area where the gate electrode is to be formed is formed. Dry etching is performed using the photoresist film Rm2 as a mask to pattern the tungsten silicide film 106 and the polysilicon film 103a. By this step, the gate electrode 108 including the lower layer film 103b made of the polysilicon film and the upper layer film 106b made of the tungsten silicide film is formed.

After that, although not shown in the drawing, the formation of the MOS transistor is completed by forming the source / drain electrodes, the wiring, etc. by a known method.

Here, according to the method of the present embodiment, FIG.
In the dry etching step shown in (d), deterioration of the gate insulating film is prevented by the following actions. Figure 2 (a)
8A to 8C are cross-sectional views showing changes in the substrate during the dry etching process. When forming the gate electrode, as shown in FIG.
During the change from the state shown in FIG. 2A to the state shown in FIG. 2C, for example, the state shown in FIG. At that time, the ion flux Iof is incident on the polysilicon film 103a in the opening of the photoresist film Rm2, and the polysilicon film 103 is caused by this ion flux Iof.
A charge is injected into a. What is etching processing?
Since the process is to break the bonds between the atoms that make up the film, electric charges are also generated by processing. However, in this embodiment, the polysilicon film 1 is formed before the gate electrode is formed.
03a is the charge escape region 10 via the buried layer 106a.
Since it is connected to the capacitor 5, the charge flow Cur to the charge escape region 105 as shown in the figure occurs in the polysilicon film 103a and the buried layer 106a. Needless to say, the same phenomenon occurs when the tungsten silicide film 106 is selectively removed, and the charges move to the charge escape region 105. That is, in any of the states, most of the charges that are injected together with the ion flux Iof or that are generated by the processing are the silicon oxide film 102.
Will not be injected into the semiconductor substrate 100 and will be moved into the semiconductor substrate 100 via the charge escape region 105.

As described above, in the present embodiment, before performing the dry etching for forming the gate electrode, the tungsten silicide film 106 and the polysilicon film 103a, which will be the gate electrode, are n-type semiconductor via the buried layer 106a. Since it is electrically connected to the charge escape region 105 in the substrate 100, most of the charges in each of the films 106 and 103a are removed from the buried layer 1 during etching.
Semiconductor substrate 10 via 06a and charge escape region 105
It is possible to suppress the injection of charges into the gate insulating film as much as possible. Therefore, it is possible to extend the reliability life due to deterioration or destruction of the gate insulating film.

Particularly, in the present embodiment, the charge escape region 10
5 is composed of a high-concentration n-type semiconductor layer, and the charge escape region 10
5 and the surrounding n-type semiconductor substrate 100 are electrically connected to each other in a resistive contact state, the resistance to the charge flow Cur toward the semiconductor substrate 100 is reduced and the semiconductor substrate 100 is There is the advantage that the proportion of the transferred charges can be increased.

FIG. 3 is a graph showing the relationship between the amount of ion flux and the reliability life of the gate insulating film (QBD value on a logarithmic scale) in the conventional manufacturing method and the method of this embodiment. As shown in the figure, according to the method of the present embodiment, the reliability life (QB) of the gate insulating film when the same ion flux amount is injected into the film forming the gate electrode.
It can be seen that D) is significantly longer than the conventional method.

In particular, the amount of ion flux flowing from the plasma to the workpiece increases in accordance with the processing speed during plasma etching. Therefore, in the present embodiment, the gate speed can be increased without decreasing the etching rate by setting the processing speed high. Damage to the insulating film can be suppressed.

Although the n-type semiconductor substrate is used in the present embodiment, even when the p-type semiconductor substrate is used, the resistance is improved by forming the charge escape region with a high-concentration p-type semiconductor layer. The same effect can be obtained by electrically connecting the film to be the gate electrode and the semiconductor substrate through the buried layer and the charge escape region.

Further, in the present embodiment, a charge escape region made of a high concentration n-type semiconductor layer is formed in the n-type semiconductor substrate, and the charge escape region and the semiconductor substrate in contact therewith form a resistive contact. However, by forming the charge escape region made of the p-type semiconductor layer in the n-type semiconductor substrate or the charge escape region made of the n-type semiconductor layer in the p-type semiconductor substrate, the charge escape region and the charge escape region are formed. A rectifying contact may be made between the semiconductor substrate and the semiconductor substrate in contact with. In such a configuration, even when a reverse bias is applied to the rectifying contact, a reverse leakage current flows in the rectifying contact, and therefore the same effect as that of the present embodiment can be obtained.

Further, in the present embodiment, the place where the charge escape region where the second conductive film to be the gate electrode and the semiconductor substrate come into contact is formed is not particularly specified.
By using this region as the substrate terminal formation region of the MOS type semiconductor, a highly reliable semiconductor integrated circuit can be formed without hindering the high integration of the semiconductor element.

(Second Embodiment) Next, a second embodiment will be described. 4A to 4D are cross-sectional views showing the manufacturing process of the semiconductor device according to the second embodiment.

As shown in FIG. 4A, on the n-type semiconductor substrate 100 on which the separating silicon oxide film 101 is formed,
After forming a silicon oxide film 102 having a thickness of about 6 nm to be a gate insulating film of a MOS transistor and further forming an n-type polysilicon film 103 having a thickness of about 100 nm to be a gate electrode on the silicon oxide film 102, the n-type polysilicon film 103 is formed. A photoresist film Rm1 having an opening above the region where the charge escape region is to be formed is formed thereon by a photolithography process.

Next, as shown in FIG. 4B, dry etching is performed using the photoresist film Rm1 as a mask to form the polysilicon film 103 and the silicon oxide film 102.
Are selectively removed to form the opening 104 reaching the region where the charge escape region is to be formed.

Next, in the step shown in FIG. 4C, after removing the photoresist film Rm1, for example, arsenic ions are implanted at a dose of 30 KeV with the polysilicon film 103a having the openings 104 formed as a mask. The amount is 5E1
The n-type semiconductor substrate 100 is implanted under the condition of about 5 / cm ^2.
A charge escape region 105 made of a high concentration n-type semiconductor is formed therein. At this time, arsenic ions are also implanted into the polysilicon film 103a. After that, for example, a tungsten silicide film 106 is formed as a refractory metal film on the entire surface of the substrate.
Is deposited to about 200 nm. At this time, the tungsten silicide film 106 also fills the opening 104, and this portion becomes the buried layer 106a.

Next, in a step shown in FIG. 4D, a photoresist film Rm3 is formed on the tungsten silicide film 106 by opening a region except a region where a gate electrode is to be formed and a terminal forming region by a photolithography process. Then, dry etching is performed using the photoresist film Rm3 as a mask to pattern the tungsten silicide film 106 and the polysilicon film 103a. By this step, the gate electrode 108 including the lower layer film 103b made of the polysilicon film and the upper layer film 106b made of the tungsten silicide film is formed in the gate electrode formation region, and the lower layer made of the polysilicon film is formed in the terminal formation region. A dummy electrode 109 composed of the film 103c and the upper film 106c made of a tungsten silicide film is formed.

After that, although not shown, the formation of the MOS transistor is completed by forming the source / drain electrodes, the wiring, etc. by a known method.

According to the present embodiment, in the step of etching the gate electrode, the tungsten silicide film 106 and the polysilicon film 103a to be the gate electrode are n-type via the charge escape region 105 in which the high-concentration n-type impurity is diffused. It is electrically connected to the semiconductor substrate 100. Therefore, as in the first embodiment, it is found that most of the charges in the films 103a and 106 move to the n-type semiconductor substrate 100 in the etching process. Moreover, in this embodiment, since the dummy electrode 109 is formed by leaving the buried layer 106a above the charge escape region 105 and the polysilicon film and the tungsten silicide film around the buried layer 106a, the following effects can be obtained. it can.

FIGS. 5A and 5B are sectional views showing the difference between the first embodiment and the present embodiment. In the first embodiment, as shown in FIG. 5A, a charge flow Cur occurs in the polysilicon film 103a which becomes thinner as the etching progresses. In the present embodiment, however, as shown in FIG. The polysilicon film 10 is formed on the dummy electrode 109.
A charge flow Cur occurs in the 3a and the tungsten silicide film 106. Therefore, comparing the resistance values R1 and R2 of the respective paths, the resistance value R2 of the path in the present embodiment is smaller, and the potential V2 of the gate electrode in the second embodiment is the gate electrode potential in the first embodiment. Lower than V1. That is, in the present embodiment,
Due to the presence of the dummy electrode 109, each film 10
Since the resistance value of the path through which the charges injected into 6, 103a flow becomes small, it is possible to reduce the local potential rise of the gate electrode due to the generated charges. F flowing in the gate insulating film directly below the gate electrode according to the local potential of the gate electrode
Since the N tunnel current value is determined, the provision of the dummy electrode can more effectively suppress the injection of charges into the gate insulating film.

Further, this dummy electrode 109 can be used later as a terminal electrode for connection with an n-type semiconductor substrate, or for forming an antenna wiring of an upper layer as in a fourth embodiment described later. Can be used.

Although the n-type semiconductor substrate is used in the present embodiment, even when the p-type semiconductor substrate is used, the resistance is increased by forming the charge-releasing region with a high-concentration p-type semiconductor layer. The same effect can be obtained by electrically connecting the film to be the gate electrode and the semiconductor substrate through the buried layer and the charge escape region.

Further, in the present embodiment, a charge escape region made of a high concentration n-type semiconductor layer is formed in the n-type semiconductor substrate, and the charge escape region and the semiconductor substrate in contact therewith form a resistive contact. However, by forming the charge escape region made of the p-type semiconductor layer in the n-type semiconductor substrate or the charge escape region made of the n-type semiconductor layer in the p-type semiconductor substrate, the charge escape region and the charge escape region are formed. A rectifying contact may be made between the semiconductor substrate and the semiconductor substrate in contact with. With such a configuration, the same effect as that of the present embodiment can be obtained.

(Third Embodiment) Next, a third embodiment will be described. 6A to 6D are cross-sectional views showing the manufacturing process of the semiconductor device according to the third embodiment.

As shown in FIG. 6A, on the p-type semiconductor substrate 110 on which the separating silicon oxide film 101 is formed,
After forming a silicon oxide film 102 having a thickness of about 6 nm to be a gate insulating film of a MOS transistor and further forming an n-type polysilicon film 103 having a thickness of about 200 nm to be a gate electrode on the silicon oxide film 102, the n-type polysilicon film 103 is formed. A photoresist film Rm1 having an opening above the region where the charge escape region is to be formed is formed thereon by a photolithography process.

Next, as shown in FIG. 6B, dry etching is performed using the photoresist film Rm1 as a mask to form the polysilicon film 103 and the silicon oxide film 102.
Are selectively removed to form the opening 104 reaching the charge escape region 105 of the p-type semiconductor substrate 110.

Next, in the step shown in FIG. 6C, after removing the photoresist film Rm1, for example, arsenic ions are implanted at a dose of 30 KeV with the polysilicon film 103a having the opening 104 formed as a mask. The amount is 5E1
The p-type semiconductor substrate 110 is implanted under the condition of about 5 / cm ^2.
A charge escape region 105 made of a high concentration n-type semiconductor is formed therein. At this time, arsenic ions are also implanted into the polysilicon film 103a. After that, for example, a tungsten silicide film 106 is formed as a refractory metal film on the entire surface of the substrate.
Is deposited to about 200 nm. At this time, the tungsten silicide film 106 also fills the opening 104, and this portion becomes the buried layer 106a.

Next, in the step shown in FIG. 6D, a portion other than the area extending over the area where the gate electrode is to be formed and the area where the diode is about to be formed is formed on the tungsten silicide film 106 by a photolithography step. A photoresist film Rm4 having an open region is formed, and dry etching is performed using the photoresist film Rm4 as a mask to pattern the tungsten silicide film 106 and the polysilicon film 103a. By this step, the gate electrode 111 with the protection diode, which is composed of the lower layer film 103d made of the polysilicon film and the upper layer film 106d made of the tungsten silicide film, is formed.

After that, although not shown, the source / drain electrodes, wirings, etc. are formed by a known method to complete the formation of the MOS transistor.

FIG. 7 is a plan view showing a state in the vicinity of the gate electrode 111, and FIGS. 6 (a) to 6 (d) are different from the sectional views in the first and second embodiments. It is shown that it is a cross-sectional view taken along line VI-VI orthogonal to the channel direction of the gate electrode.

FIGS. 8A and 8B are a sectional view and an equivalent electric circuit diagram showing the structure of the semiconductor device during the process of patterning the tungsten silicide film 106 and the polysilicon film 103. That is, the charge escape region 1 is provided for the capacitor body corresponding to the gate insulating film of the MOSFET.
05 and the semiconductor substrate 100 constitute a circuit in which a protection diode is connected in parallel.

Also in this embodiment, in the step of forming the gate electrode by etching, each film 10 provided by the ion flux or produced by the processing is used.
Until the formation of the gate electrode 111 is completed, the charges in the reference numerals 6, 103a are transferred to the substrate side via a charge escape region 105 in which a high concentration n-type impurity is diffused and a p-type semiconductor substrate 110. This can be released, and the injection of charges into the gate insulating film 102 can be suppressed as much as possible. In particular, there is an advantage that the negative charges in the gate electrode being formed can be quickly moved into the semiconductor substrate.

Further, since the gate electrode 111 has a structure in which it is integrated with the dummy electrode, charges can move through the first and second conductive films 103a and 106, and an electric charge against the movement of charges can be obtained. The resistance can be further reduced as compared with the second embodiment.

Further, it can also be used in a step after the step shown in FIG. 8A to prevent a high voltage from being applied to the gate insulating film.

That is, as shown in FIG. 9, an interlayer insulating film 112 is deposited on a substrate on which a gate electrode 111 is formed, and a photoresist having an opening above the gate electrode 111 and other portions is formed on the interlayer insulating film 112. The film Rm5 is formed. afterwards,
Using the photoresist film Rm5 as a mask, dry etching is performed to form the gate electrode 1 on the interlayer insulating film 112.
A contact hole 114 reaching 11 and a contact hole (not shown) reaching other locations are formed. At that time, the gate electrode 111 exposed at the bottom of the contact hole 114 is over-etched and exposed to the ion flux Iof until another contact hole reaching the surface of the semiconductor substrate penetrates. Since the charges inside are released to the charge escape region 105 via the buried layer 106a, it is possible to prevent the charges from being injected into the gate insulating film 102 as much as possible.

In this embodiment, the protective diode is formed by forming the charge escape region 105 made of the n-type semiconductor layer in the p-type semiconductor substrate.
Even when the protection diode is formed by forming the charge escape region made of the p-type semiconductor layer in the n-type semiconductor substrate, the positive charge injected into the gate electrode can flow into the n-type semiconductor substrate. A similar effect can be obtained for positive charge injection into the gate electrode.

(Fourth Embodiment) In this embodiment, an embodiment will be described in which the antenna wiring is formed by using the gate electrode or the dummy electrode formed in the second and third embodiments.

First, the case where the third embodiment is used will be described. As shown in FIG. 10A, an interlayer insulating film 112 is deposited on the substrate on which the gate electrode 111 is formed, and a photo film having an opening above the gate electrode 111 and the n-type diffusion layer 113 is formed thereon. A resist film Rm5 is formed. After that, dry etching is performed using the photoresist film Rm5 as a mask to form the interlayer insulating film 112.
The contact hole 11 reaching the gate electrode 111
4 and the contact hole 1 reaching the n-type diffusion layer 113
Open 15 At that time, the gate electrode 111 exposed at the bottom of the contact hole 114 is not covered with the contact hole 11.
5 is exposed to the ion flux Iof by being over-etched until it penetrates, but the charge in the gate electrode 111 is escaped to the charge escape region 105 through the buried layer 106a, so that the gate insulating film 102 is exposed. It is possible to prevent charges from being injected as much as possible.

Then, as shown in FIG. 10B, after removing the photoresist film Rm5, each contact hole 1
An antenna wiring 116 is formed to fill 14 and 115.

Next, the case where the second embodiment is used will be described. As shown in FIG. 11A, an interlayer insulating film 112 is formed on the entire surface of the substrate on which the gate electrode 108 and the dummy electrode 109 are formed, and the gate electrode electrodes 10 are formed.
Photoresist film R having an opening above 8,109
Form m6. Then, dry etching is performed using the photoresist film Rm6 as a mask to form the interlayer insulating film 112.
The contact hole 11 reaching the gate electrode 108
7 and the contact hole 1 reaching the dummy electrode 109
18 and 18 are formed. At this time, each contact hole 11
Since the depths of 7 and 118 are almost the same, charges are not injected into the gate insulating film 102 by overetching. Therefore, the deterioration of the gate insulating film 102 can be effectively avoided.

After that, as shown in FIG. 11B, the antenna wiring 1 for filling the contact holes 117 and 118 is formed.
19 is formed.

In this embodiment, the protection diode is formed by forming the charge escape region 105 made of the n-type semiconductor layer in the p-type semiconductor substrate.
Even when the protection diode is formed by forming the charge escape region made of the p-type semiconductor layer in the n-type semiconductor substrate, the positive charge injected into the gate electrode can flow into the n-type semiconductor substrate. A similar effect can be obtained for positive charge injection into the gate electrode.

(Fifth Embodiment) Next, a fifth embodiment will be described in which the present invention is applied to a semiconductor device having a trench isolation structure.
An embodiment will be described. 12 (a) to (f)
FIG. 9A is a sectional view showing a manufacturing process for a semiconductor device according to a fifth embodiment. However, in FIGS. 12A to 12F, the left diagram is a sectional view in a portion including the transistor formation region, and the right diagram is a sectional view in the alignment key formation region.

As shown in FIG. 12A, a silicon oxide film 102 having a thickness of about 6 nm to be a gate insulating film of a MOS transistor is formed on an n-type semiconductor substrate 100, and a thickness to be a gate electrode is further formed thereon. N of about 200 nm
After forming the type polysilicon film 103, a photolithography process is performed on the n-type polysilicon film 103 by a photolithography process.
Photoresist film Rm7 having an opening above the region where charge escape region, trench isolation, and alignment key are to be formed
To form

Next, as shown in FIG. 12B, dry etching is performed using the photoresist film Rm7 as a mask, and the polysilicon film 103 and the silicon oxide film 10 are etched.
After 2 is selectively removed, the n-type semiconductor substrate 100 is further dug in these regions to a predetermined depth to form a charge escape groove 121a, a separation groove 121b, and an alignment key groove 121c, respectively. .

Next, as shown in FIG. 12C, after removing the photoresist film Rm7, an insulating film (silicon oxide film) 124 is deposited to a thickness of, for example, about 700 nm on the entire surface of the substrate, and each groove portion is formed. 121a to 121c are insulating films 1
Insulating embedded layers 124a to 1
24c is formed. Further, for example, chemical mechanical polishing (C
The insulating film 124 is removed from above by planarization by the MP) method, and the divided polysilicon film 103a is separated.
To expose. At this time, the insulating burying layers 124a to 124c embedded in the respective groove portions 121a to 121c are in an isolated state.

Thereafter, as shown in FIG. 12D, the insulating burying layer 124a of the charge escape groove 121a,
Insulating embedding layer 12 in alignment key groove 121b
A photoresist film Rm8 having an opening above 4c is formed, and dry etching is performed using this photoresist film Rm8 as a mask to remove the insulating buried layers 124a and 124c in the openings of the photoresist film Rm8.
That is, the surface of the semiconductor substrate forming the charge escape groove 121a and the alignment key groove 121c is exposed.
Next, after removing the photoresist film Rm8, using the polysilicon film 103 and the insulating burying layer 124b as a mask, for example, arsenic ions are added at 30 KeV, 5E15.
Under a condition of / cm ² to form charge escape regions 105a and 105b made of an n-type semiconductor layer in the semiconductor substrate forming the side surfaces and the bottom surface of the charge escape groove portion 121a and the alignment key groove portion 121c, respectively. Refractor metal film (for example, tungsten film) 126 of 200n
It is formed with a thickness of about m. At this time, each groove 121
A tungsten film is buried in a and 121c to form conductive buried layers 126a and 126c, respectively.

Then, as shown in FIG. 12F, the refractory metal film 126 and the polysilicon film 103 are formed.
By patterning a, the gate electrode 108 including the lower layer film 103b and the upper layer film 126c, and the lower layer film 1
03c and the upper layer film 126d are formed to form the dummy electrode 109. At this time, the alignment key groove 121c
Since the tungsten film is removed from the groove 121,
c can be used as an alignment key for aligning the photolithography mask.

After that, the source / drain electrodes, wirings, etc. are formed by a known method, thereby completing the formation of the MOS transistor.

According to the present embodiment, in the dry etching process for forming the gate electrode, the charges in the films 126 and 103a are electrically conductive in the charge escape regions 105a and 105b by the same action as in the second embodiment. Can be released into the substrate through the buried layers 126a and 126b,
At that time, the electric resistance to the flow of charges can be reduced as much as possible.

In particular, in this embodiment, charges can be released into the substrate through the conductive embedding layer 126b of the alignment key groove portion 121c, and the groove width of the alignment key groove portion 121c is large, so that the charge receiving ability is high. Is high. Moreover, since the number of steps for forming this alignment key does not increase, a semiconductor integrated circuit having high gate insulating film reliability can be formed without increasing the number of steps.

Also in this embodiment, similarly to the fourth embodiment, an interlayer insulating film can be further deposited to form an antenna wiring that contacts the dummy electrode 109 and the gate electrode 108.

Further, as shown in FIG. 13, as in the third embodiment, in the cross section orthogonal to the cross section shown in FIGS. 12A to 12F, the charge burying groove portion 121a is electrically conductively embedded. The layer 126a and the gate electrode 108 may be connected to each other through a tungsten film. With this configuration, in addition to the effects of the above-described fifth embodiment, the same effects as those of the above-described third embodiment can be exhibited.

Further, an interlayer insulating film can be formed on the substrate shown in FIG. 13 to form an antenna wiring which contacts this gate electrode 108.

[0115]

According to the method of manufacturing a semiconductor device of the present invention, the insulating film and the first conductive film are deposited on the semiconductor substrate, and then the first region for forming the gate electrode is formed separately. Forming a second conductive film in the connection hole and over the first conductive film by opening a connection hole on the second region of
Since the conductive film is patterned to form the gate electrode, the charges in the gate electrode are transferred to the semiconductor substrate through the second conductive film embedded in the opening during the formation of the gate electrode. Therefore, it is possible to provide a method for manufacturing a semiconductor device which can be moved and has a long reliability life with a small amount of charges injected into the gate insulating film.

In particular, the fourth and sixth aspects provide a method of manufacturing a semiconductor device which can reduce the amount of charges injected into the gate insulating film even when forming a contact hole and has a long reliability life. be able to.

According to the tenth to seventeenth aspects, it is possible to provide a method of manufacturing a semiconductor device having a trench isolation structure and having a small amount of charges injected into the gate insulating film.

According to the semiconductor device of claims 21 to 29,
A gate electrode composed of an insulating film, a first conductive film, and a second conductive film and a dummy electrode are respectively provided in the first region where the MIS transistor is to be formed and the second region where the charge is released. Since the dummy electrode is formed by embedding the second conductive film in the opening penetrating the first conductive film and the insulating film, it is possible to reduce the injection amount into the gate insulating film in the manufacturing process of the semiconductor device. Can be done, so
The reliability life of the semiconductor device can be improved.

According to the semiconductor device forming laminated body of the thirtieth aspect, the insulating film and the first conductive film are provided in the first region where the MIS transistor is to be formed and the second region where the charge is released. The second layer is deposited and extends over the first conductive film and in the opening penetrating the first conductive film and the insulating film on the second region.
The structure in which the second conductive film is deposited and the second conductive film is connected to the semiconductor substrate through the second region is used, so that the amount of implantation into the gate insulating film in the subsequent step of forming the gate electrode is reduced. Therefore, it can be used for manufacturing a semiconductor device having a long reliability life.

[Brief description of drawings]

FIG. 1 is a sectional view illustrating a manufacturing process of a semiconductor device according to a first embodiment.

FIG. 2 is a cross-sectional view for explaining the flow of charges when forming a gate electrode in the first embodiment.

FIG. 3 is a diagram showing a relationship between an ion flux at the time of forming a gate electrode and a reliability life of a gate insulating film in the first embodiment in comparison with a conventional semiconductor device.

FIG. 4 is a sectional view illustrating a manufacturing process of a semiconductor device according to a second embodiment.

FIG. 5 is a cross-sectional view illustrating a charge flow when forming a gate electrode according to the second embodiment.

FIG. 6 is a cross-sectional view taken along the line VI-VI of FIG. 7 showing the manufacturing process of the semiconductor device according to the third embodiment.

FIG. 7 is a plan view showing a structure near a gate electrode in a third embodiment.

8A and 8B are a cross-sectional view and an equivalent electric circuit diagram between a gate electrode and a substrate for explaining the flow of charges when forming a gate electrode in the third embodiment.

FIG. 9 is a cross-sectional view for explaining the flow of charges when opening a contact hole reaching a gate electrode in an interlayer insulating film in the third embodiment.

FIG. 10 is a cross-sectional view showing the manufacturing process of the fourth embodiment in which the antenna wiring is formed by using the third embodiment.

FIG. 11 is a cross-sectional view showing the manufacturing process of the fourth embodiment in which the antenna wiring is formed by using the second embodiment.

FIG. 12 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the fifth embodiment.

FIG. 13 is a sectional view showing a structure of a semiconductor device according to a modification of the fifth embodiment.

FIG. 14 is a cross-sectional view showing a process of forming a conventional antenna wiring.

FIG. 15 is a diagram showing a relationship between ion flux and reliability life of a gate insulating film when forming a conventional gate electrode.

[Explanation of symbols]

 100 n-type semiconductor substrate 101 isolation insulating film 102 silicon oxide film (gate insulating film) 103 polysilicon film (first conductive film) 104 opening 105 charge escape region 106 tungsten silicide film (second conductive film) 108 gate electrode 109 dummy electrode 110 p-type semiconductor substrate 111 gate electrode 112 interlayer insulating film 114 contact hole 115 contact hole 116 antenna wiring 117 contact hole 118 contact hole 119 antenna wiring 121a charge escape groove 121b separation groove 121c alignment key groove 124a to 124c Insulating buried layer 126 Tungsten film (second conductive film) 126a to 126c Conductive buried layer Rm1 to Rm8 Photoresist film

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Office reference number FI technical display location H01L 21/768 H01L 29/78 301G

Claims (30)

[Claims] 1. A first forming an insulating film on the first and second regions of a semiconductor substrate having a first region for forming a MIS transistor and a second region for releasing charges. And a second step of forming a first conductive film on the insulating film, and forming an opening penetrating the first conductive film and the insulating film to reach the second region. A third step; a fourth step of forming a second conductive film in the opening and on the first conductive film; and a patterning of the first and second conductive films to form the first conductive film. And a fifth step of forming a gate electrode above the first region by the second conductive film, the method of manufacturing a semiconductor device. 2. The method of manufacturing a semiconductor device according to claim 1, wherein in the fifth step, a dummy electrode is formed on the second region by the first and second conductive films. A method of manufacturing a semiconductor device, which comprises patterning the first and second conductive films. 3. The method of manufacturing a semiconductor device according to claim 2, wherein in the fifth step, the first and second conductive films are patterned so that the gate electrode and the dummy electrode are continuous with each other. A method of manufacturing a semiconductor device, comprising: 4. The method of manufacturing a semiconductor device according to claim 3, wherein after the fifth step, a step of forming an interlayer insulating film on the substrate, and a step of penetrating the interlayer insulating film to reach the gate electrode. Forming a first connection hole and a second connection hole reaching the third region of the semiconductor substrate, and forming an antenna wiring in each connection hole and on the interlayer insulating film. A method of manufacturing a semiconductor device, further comprising: 5. The method of manufacturing a semiconductor device according to claim 2, wherein in the fifth step, the first and second conductive films are patterned so that the gate electrode and the dummy electrode are separated from each other. A method of manufacturing a semiconductor device, comprising: 6. The method of manufacturing a semiconductor device according to claim 5, wherein after the fifth step, a step of forming an interlayer insulating film on the substrate, and a step of penetrating the interlayer insulating film to reach the gate electrode. And a step of forming a second connection hole reaching the dummy electrode, and a step of forming an antenna wiring extending in each of the connection holes and on the interlayer insulating film. A method for manufacturing a semiconductor device, comprising: 7. The method of manufacturing a semiconductor device according to claim 1, wherein after the third step and before the fourth step, a high concentration is formed in the semiconductor substrate exposed in the second region. A method of manufacturing a semiconductor device, further comprising a step of implanting impurities. 8. The method of manufacturing a semiconductor device according to claim 7, wherein the conductivity type of the impurity implanted in the second region is the conductivity of the impurity in the region in contact with the second region in the semiconductor substrate. A method for manufacturing a semiconductor device, which is the same as the mold. 9. The method of manufacturing a semiconductor device according to claim 7, wherein the conductivity type of the impurity implanted into the second region is the conductivity of the impurity within a region of the semiconductor substrate in contact with the second region. A method of manufacturing a semiconductor device, which is different from the mold. 10. The method of manufacturing a semiconductor device according to claim 1, wherein in the third step, the opening is formed also in a region where a separation groove surrounding the first region is formed, and the opening is formed. The semiconductor substrate is further dug to a predetermined depth in the portion to form the charge escape groove portion and the separation groove portion, respectively, and after the third step and before the fourth step, in each of the groove portions and the Depositing an isolation insulating film over the first conductive film, and removing the isolation insulating film until at least the upper surface of the first conductive film is exposed and at least a part of the first conductive film remains. A step of flattening the substrate surface so as to leave the isolation insulating film inside and above each of the groove portions, and for separating the charge releasing groove portion of the isolation insulating film left in each groove portion. And a step of removing the insulating film In the fourth step, the second conductive film is formed over the first conductive film and the isolation insulating film left above the isolation trench. Manufacturing method. 11. The method of manufacturing a semiconductor device according to claim 10, wherein in the fifth step, a dummy electrode is formed on the second region by the first and second conductive films. A method of manufacturing a semiconductor device, which comprises patterning the first and second conductive films. 12. The method of manufacturing a semiconductor device according to claim 11, wherein in the fifth step, the gate electrode and the dummy electrode are connected to each other through the second conductive film. A method of manufacturing a semiconductor device, which comprises patterning the first and second conductive films. 13. The method of manufacturing a semiconductor device according to claim 11, wherein in the fifth step, the first and second conductive films are patterned so that the gate electrode and the dummy electrode are separated from each other. A method of manufacturing a semiconductor device, comprising: 14. The method of manufacturing a semiconductor device according to claim 10, wherein in the third step, the opening is also formed in a region where an alignment key is formed, and the semiconductor substrate in the region is dug to a predetermined depth. Then, in the step of forming the alignment key groove portion and depositing the isolation insulating film, in the step of depositing the isolation insulating film also in the alignment key groove portion and flattening the substrate surface, In the step of removing the insulating film for separation in the charge-releasing groove while leaving the insulating film for separation in and above the groove for use in separation, the insulating film for separation in the groove for alignment key is removed, Then, the second conductive film is deposited also in the alignment key groove, and in the fifth step, the first and second portions inside and around the alignment key groove portion are formed. A method of manufacturing a semiconductor device, comprising removing the conductive film of. 15. The method for manufacturing a semiconductor device according to claim 10, 11 or 14, wherein after the third step and before the fourth step, the side wall and the bottom of the charge escape groove portion of the semiconductor substrate are provided. A method of manufacturing a semiconductor device, further comprising the step of implanting a high concentration of impurities into the second region forming the wall. 16. The method of manufacturing a semiconductor device according to claim 15, wherein the conductivity type of the impurity implanted in the second region is the impurity type in the region in contact with the second region in the semiconductor substrate. A method of manufacturing a semiconductor device, which is of the same conductivity type. 17. The method of manufacturing a semiconductor device according to claim 15, wherein the conductivity type of the impurities implanted into the second region is the impurity type in the region in contact with the second region in the semiconductor substrate. A method of manufacturing a semiconductor device, which is different from the conductivity type. 18. The method for manufacturing a semiconductor device according to claim 1, 2, 10 or 11, wherein in the second step, the first conductive film is made of a polysilicon film. Manufacturing method. 19. The method of manufacturing a semiconductor device according to claim 1, 2, 10 or 11, wherein in the fourth step, the second conductive film is made of a refractory metal film. Manufacturing method. 20. The method of manufacturing a semiconductor device according to claim 1, 2, 10 or 11, wherein in the fourth step, the second conductive film is composed of a polysilicon film. Manufacturing method. 21. A semiconductor substrate having a first region in which a MIS transistor is to be formed and a second region for releasing charges, and a semiconductor substrate formed on the first region and the second region, An insulating film serving as a gate insulating film on the first region, a first conductive film formed on the insulating film, the first conductive film and the insulating film, and the second region. And a second conductive film which is formed over the inside of the opening and over the first conductive film and is in contact with the second region. And the second conductive film forms a gate electrode above the first region on the semiconductor substrate, while forming a dummy electrode above the second region. . 22. The semiconductor device according to claim 21, wherein the gate electrode and the dummy electrode are integrally formed by the first and second conductive films. 23. The semiconductor device according to claim 22, wherein an interlayer insulating film formed on the gate electrode and the dummy electrode and a first connection hole penetrating the interlayer insulating film to reach the gate electrode. A second connection hole penetrating the interlayer insulating film to reach the third region of the semiconductor substrate; and an antenna wiring extending in the first and second connection holes and on the interlayer insulating film. A semiconductor device further comprising: 24. The semiconductor device according to claim 21, wherein the gate electrode and the dummy electrode are separated from each other. 25. The semiconductor device according to claim 24, wherein the dummy electrode is a grounding terminal electrode. 26. The semiconductor device according to claim 25, wherein an interlayer insulating film formed on the gate electrode and the dummy electrode and a first connection hole penetrating the interlayer insulating film to reach the gate electrode. And a second connection hole penetrating the interlayer insulating film to reach the dummy electrode, and an antenna wiring extending in the first and second connection holes and on the interlayer insulating film. A semiconductor device characterized by the above. 27. The semiconductor device according to claim 21, wherein a charge escape groove portion formed in the second region of the semiconductor substrate and formed by digging the semiconductor substrate to a predetermined depth, and an isolation region surrounding the first region. A groove and a separation insulating film formed inside and above the separation groove, wherein the first conductive film is formed at the same height as the separation insulating film; 2. The semiconductor device according to claim 2, wherein the second conductive film fills the charge escape groove. 28. The semiconductor device according to claim 21, wherein the second region and a region in the semiconductor substrate which is in contact with the second region are in resistive contact with each other. 29. The semiconductor device according to claim 21, wherein the second region and a region in the semiconductor substrate which is in contact with the second region are in rectifying contact. 30. A semiconductor substrate having a first region in which a MIS transistor is to be formed and a second region for releasing charges, and a semiconductor substrate formed on the first region and the second region, wherein: An insulating film serving as a gate insulating film on the first region, a first conductive film formed on the insulating film, the first conductive film and the insulating film, and the second region. A second conductive film formed on at least the first conductive film, and patterning the first conductive film and the second conductive film to form a gate electrode. At this time, the stacked body for forming a semiconductor device is configured such that charges can move from the gate electrode being formed into the semiconductor substrate through the second region.