JP2003243444A - Substrate mounting structure and semiconductor device - Google Patents

Substrate mounting structure and semiconductor device

Info

Publication number
JP2003243444A
JP2003243444A JP2002044052A JP2002044052A JP2003243444A JP 2003243444 A JP2003243444 A JP 2003243444A JP 2002044052 A JP2002044052 A JP 2002044052A JP 2002044052 A JP2002044052 A JP 2002044052A JP 2003243444 A JP2003243444 A JP 2003243444A
Authority
JP
Japan
Prior art keywords
chip
underfill material
substrate
groove structure
mounting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2002044052A
Other languages
Japanese (ja)
Other versions
JP3818441B2 (en
Inventor
Shinji Aoyama
眞二 青山
Tomoyuki Akeyoshi
智幸 明吉
Masami Tokumitsu
雅美 徳光
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP2002044052A priority Critical patent/JP3818441B2/en
Publication of JP2003243444A publication Critical patent/JP2003243444A/en
Application granted granted Critical
Publication of JP3818441B2 publication Critical patent/JP3818441B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/921Connecting a surface with connectors of different types
    • H01L2224/9212Sequential connecting processes
    • H01L2224/92122Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits

Abstract

<P>PROBLEM TO BE SOLVED: To provide a substrate mounting structure surely formed with an underfill material unfilled region. <P>SOLUTION: The substrate mounting structure is mounted with a chip like OEIC chip 1 to a mounting substrate 5 in the form of a flip chip, and filled with the underfill material between the substrate 5 and the chip 1. A groove 3 for preventing the invasion of the underfill material is formed at at least either a part of the mounting substrate or chip 1, and there is provided the underfill material unfilled region. <P>COPYRIGHT: (C)2003,JPO

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本願発明は、基板実装構造及び半
導体装置に係る。特に、フリップチップボンディング実
装に関するものであり、フリップチップボンディング時
に通常利用されるアンダーフィル材の侵入を部分的に阻
止することにより、フリップチップされる半導体チップ
の一部をアンダーフィル材の侵入から保護するものであ
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a board mounting structure and a semiconductor device. In particular, it relates to flip-chip bonding mounting, and partially blocks the infill material that is normally used during flip-chip bonding to protect part of the flip-chip semiconductor chip from intruding the underfill material. To do.

【0002】[0002]

【従来の技術】インターネット需要等の急速な増加に対
し、通信容量の拡大が急務になっている。光通信におけ
る通信容量を拡大する方法としては、個々の通信の処理
速度を上げて複数の信号を多重する時間分割多重(TD
M)方式と、異なる複数の波長を利用して信号を多重す
る波長多重(WDM)方式が提案されている。TDM方
式を採用した場合、必然的にファイバー内を流れる信号
の速度を速くする必要がある。しかしながら、電気信号
の速度が60Gbit/s程度以上になると、電気信号
特有の表皮効果や寄生容量などの影響が顕著になり損失
が大きくなるため、高速電気信号をパッケージに入出力
することが困難となる。
2. Description of the Related Art With the rapid increase in demand for the Internet and the like, there is an urgent need to expand communication capacity. As a method for expanding the communication capacity in optical communication, a time division multiplexing (TD) method for increasing the processing speed of each communication and multiplexing a plurality of signals is used.
The M) method and the wavelength division multiplexing (WDM) method for multiplexing signals by using a plurality of different wavelengths have been proposed. When the TDM method is adopted, it is inevitably necessary to increase the speed of the signal flowing in the fiber. However, when the speed of the electric signal becomes about 60 Gbit / s or more, the effect of the skin effect and parasitic capacitance peculiar to the electric signal becomes remarkable and the loss becomes large, which makes it difficult to input / output the high speed electric signal to / from the package. Become.

【0003】このような問題に対する1つの対策とし
て、高速信号に光インターフェースを採用した光・電気
融合集積回路(OEIC)の研究開発が行われている。
光・電気融合インターフェースを採用した1つの例とし
て、高飽和電流特性を有する高速フォトダイオードと4
0Gbit/s以上の高速動作可能なInP系デジタル
ICをモノリシック集積したレシーバ機能を有するデジ
タルOEICが実現されている。ここで、フォトダイオ
ードとしては、面型構造の受光部を有する素子を採用し
ているが、この場合、電子回路の電極端子面に対し垂直
方向に光信号を入出力する必要があり、パッケージに入
れる場合には、側面に配置されている電気端子と垂直に
ファイバー接続端子を設ける必要がある。実際に該OE
ICをパッケージに実装する場合には、光学系の位置合
わせが極めて困難であり、また、該パッケージをボード
に実装することを考慮すると、電気入出力端子と光入出
力端子が垂直に存在することは好ましい構造とはいえな
い。なお、光通信用に通常用いられる波長1.55μm
帯の光はInP基板を透過することができるため、基板
の裏面から信号光を入射しても基板表面に形成したフォ
トダイオードに給光することができる。
As one measure against such a problem, research and development of an optical-electrical integrated circuit (OEIC) which employs an optical interface for high-speed signals is being conducted.
As one example of adopting the optical / electrical fusion interface, a high-speed photodiode having a high saturation current characteristic and 4
A digital OEIC having a receiver function, which is a monolithically integrated InP-based digital IC capable of high-speed operation of 0 Gbit / s or more, has been realized. Here, as the photodiode, an element having a light receiving portion of a planar structure is adopted, but in this case, it is necessary to input / output an optical signal in a direction perpendicular to the electrode terminal surface of the electronic circuit, When it is inserted, it is necessary to provide the fiber connection terminal vertically to the electric terminal arranged on the side surface. Actually the OE
When mounting an IC on a package, it is extremely difficult to align the optical system, and in consideration of mounting the package on a board, the electric input / output terminal and the optical input / output terminal must be present vertically. Is not a preferred structure. Note that the wavelength normally used for optical communication is 1.55 μm
Since the band light can pass through the InP substrate, even if the signal light is incident from the back surface of the substrate, it can be supplied to the photodiode formed on the front surface of the substrate.

【0004】また、導波路型の受光部を有するフォトダ
イオードを、アナログ増幅回路と集積したOEICも報
告されている。導波路型の素子を用いる場合、光導波路
との整合性が良く、外部光ファイバーとの接続という点
においては優れているが、そのサイズが横長となり素子
の微細化の点で問題があると共に、光閉じ込めのための
クラッド層を必要とするため、素子構造が面型の場合に
比べて厚くなる。このため、アナログ増幅回路程度であ
ればモノリシック集積することも可能であるが、回路規
模の大きなデジタル信号処理用ICをモノリシック集積
することは極めて困難であるため、実現されるに至って
いない。
An OEIC in which a photodiode having a waveguide type light receiving section is integrated with an analog amplifier circuit has also been reported. When a waveguide type element is used, it has good compatibility with the optical waveguide and is excellent in connection with an external optical fiber, but its size is laterally long and there is a problem in terms of device miniaturization. Since the clad layer for confinement is required, the device structure becomes thicker than that of the planar type. For this reason, it is possible to monolithically integrate as long as it is an analog amplifier circuit, but it is extremely difficult to monolithically integrate a digital signal processing IC having a large circuit scale, and it has not been realized yet.

【0005】光・電気インターフェースを有するOEI
Cを実現するに当たり、実装という観点から光および電
気入出力端子は全てパッケージの側面に配置したいとい
う要望がある。また、実装時のコストを低減するため、
OEICチップと外部光ファイバーとの光学位置合わせ
を、特性を見ながら固定する「アクティブアラインメン
ト」から、特性を見ながら位置合わせを行わずとも、単
に決められた位置に両者を設置固定するだけの「パッシ
ッブアラインメント」で光学位置合わせが可能なで実装
方法が望まれている。
OEI with optical / electrical interface
In realizing C, there is a demand for arranging all the optical and electric input / output terminals on the side surface of the package from the viewpoint of mounting. Also, in order to reduce the cost of mounting,
From the "active alignment" that fixes the optical alignment between the OEIC chip and the external optical fiber while observing the characteristics, it is possible to simply install and fix both at a predetermined position without performing the alignment while observing the characteristics. A mounting method is desired because optical alignment can be performed by “sib alignment”.

【0006】このような要求に対する1つの構造とし
て、光半導体チップ上に光配線構造と光路変更構造を作
製し、かつ、フリップチップボンディング技術を用いて
実装するものが提案されている(図10)。ここでフリ
ップチップ接続を用いるのは、半田バンプの表面張力に
よる自己位置合わせ機能により実装基板に対してフリッ
プチップが極めて精度よく位置合わせができるからであ
る。
As one structure to meet such demands, there has been proposed a structure in which an optical wiring structure and an optical path changing structure are manufactured on an optical semiconductor chip and mounted by using a flip chip bonding technique (FIG. 10). . The flip-chip connection is used here because the flip-chip can be extremely accurately aligned with the mounting substrate by the self-alignment function by the surface tension of the solder bump.

【0007】しかしながら、フリップチップボンディン
グ技術を用いた実装では、基板とフリップチップとの機
械的接続強度が弱いため、基板とチップの間にアンダー
フィル材と呼ばれる接着剤を充填し、機械的接続強度を
補強することが一般的である。このアンダーフィル材の
充填は、図11に示す様に行う。チップと実装基板を半
田バンプ等を用いて電気的に接続した後、チップと実装
基板の隙間に毛細管現象を利用して液体であるアンダー
フィル材を挿入する。その後、加熱処理などでアンダー
フィル材を乾燥させて固化する。これにより機械的接続
強度増加させる。ここで十分な接続強度を得るため、ア
ンダーフィル材はフリップチップ接続されるチップの全
面に広がるような量を充填するのが普通である。
However, in the mounting using the flip chip bonding technique, since the mechanical connection strength between the substrate and the flip chip is weak, an adhesive agent called an underfill material is filled between the substrate and the chip to make the mechanical connection strength. It is common to reinforce. The filling of the underfill material is performed as shown in FIG. After electrically connecting the chip and the mounting substrate with solder bumps or the like, an underfill material that is a liquid is inserted into the gap between the chip and the mounting substrate by utilizing the capillary phenomenon. After that, the underfill material is dried and solidified by heat treatment or the like. This increases the mechanical connection strength. Here, in order to obtain sufficient connection strength, it is usual to fill the underfill material in an amount that spreads over the entire surface of the chip to be flip-chip connected.

【0008】光半導体チップをフリップチップ実装する
場合、光半導体チップの表面あるいは側面に光信号のイ
ンターフェースが存在するため、毛細管現象を用いて実
装基板とフリップチップ間にアンダーフィル材を充填す
ると、アンダーフィル材がチップ全体およびチップ側面
にまで広がるため光入出力部を遮ってしまうという問題
があった。
When an optical semiconductor chip is flip-chip mounted, since an optical signal interface exists on the surface or side surface of the optical semiconductor chip, if an underfill material is filled between the mounting substrate and the flip chip by using a capillary phenomenon, an underfill material is generated. Since the fill material spreads over the entire chip and the side surface of the chip, there is a problem that it blocks the light input / output section.

【0009】[0009]

【発明が解決しようとする課題】本発明は、アンダーフ
ィル材を充填したくない部分に確実にアンダーフィル材
非充填領域が形成されている基板実装構造を提供するこ
とを目的とする。
SUMMARY OF THE INVENTION It is an object of the present invention to provide a board mounting structure in which an underfill material non-filled region is surely formed in a portion where the underfill material is not desired to be filled.

【0010】[0010]

【課題を解決するための手段】本発明の基板実装構造
は、実装基板にチップがフリップチップで実装され、両
者の間にアンダーフィル材が充填された基板実装構造に
おいて、該実装基板あるいは該チップの少なくともどち
らか一方の一部に、アンダーフィル材の侵入を防ぐ為の
溝構造が形成されアンダーフィル材非充填領域を有する
ことを特徴とする。
The board mounting structure of the present invention is a board mounting structure in which a chip is mounted on a mounting board by flip-chip and an underfill material is filled between the two. A groove structure for preventing the underfill material from entering is formed in at least one of the two or more of the above to have an underfill material non-filled region.

【0011】アンダーフィル材としては、実装基板とチ
ップの間に充填し、流動性を有するものならばすべてを
含む。特に、接着剤が好適に用いられる。
The underfill material includes any material that is filled between the mounting substrate and the chip and has fluidity. In particular, an adhesive is preferably used.

【0012】前記溝構造が前記チップ側に作製される場
合、該溝構造が前記チップのエッジにまで達しているこ
とが好ましい。この場合、アンダーフィル材が溝構造の
外側から回り込むことを防止することができる。そのた
め、アンダーフィル材の侵入をより一層完全に防止する
ことができる。
When the groove structure is formed on the chip side, it is preferable that the groove structure reaches the edge of the chip. In this case, the underfill material can be prevented from wrapping around from the outside of the groove structure. Therefore, intrusion of the underfill material can be prevented even more completely.

【0013】前記溝構造が前記アンダーフィル材非充填
領域を取り囲む様に配置されているのが好ましい。この
場合もアンダーフィル材の侵入をより完全に防止するこ
とができる。
It is preferable that the groove structure is arranged so as to surround the area not filled with the underfill material. Also in this case, the underfill material can be more completely prevented from entering.

【0014】前記溝構造が前記実装基板側に作製される
場合には、前記チップの搭載領域の外部にまで溝構造が
広がっていることが好ましい。チップの搭載領域の外側
にまで溝構造が広がっているとアンダーフィル材は、光
インターフェース等の対向部分に回り込みにくくなりア
ンダーフィル材非充填領域をより確実に形成することが
できる。
When the groove structure is formed on the mounting substrate side, it is preferable that the groove structure extends outside the mounting area of the chip. If the groove structure extends to the outside of the chip mounting region, the underfill material is less likely to wrap around the facing portion such as the optical interface, and the underfill material non-filled region can be formed more reliably.

【0015】前記溝構造が前記基板及び前記チップの両
方に作製される場合、両溝構造が対向していることが好
ましい。両溝構造が対向していると溝の深さは両溝構造
を足した深さとなり、アンダーフィル材非充填領域への
アンダーフィル材の流入をよりよく防止することができ
る。
When the groove structures are formed on both the substrate and the chip, it is preferable that both groove structures face each other. When the two groove structures are opposed to each other, the depth of the groove is equal to the depth of the both groove structures, and it is possible to better prevent the underfill material from flowing into the underfill material unfilled region.

【0016】前記チップは、半導体チップであることが
好ましい。特に光半導体チップであることが好ましい。
The chip is preferably a semiconductor chip. An optical semiconductor chip is particularly preferable.

【0017】さらに、前記アンダーフィル材非充填領域
は、光インターフェイス部分であることが好ましい。か
かる場合、光インターフェイス部分における光の入出力
は遮られることなく行われる。その結果光の入出力が確
実に行われる。
Further, the underfill material non-filled region is preferably an optical interface portion. In such a case, the input / output of light in the optical interface portion is performed without interruption. As a result, the input and output of light is surely performed.

【0018】[0018]

【作用】本願発明は、実装基板に半導体チップなどのチ
ップをフリップチップ接続する構造において、実装基板
あるいはチップの少なくともどちらか一方に溝構造を作
製することにより、部分的にチップと実装基板の間隔を
広げた箇所を作製する。このように間隔が広がった部分
では毛細管現象で侵入するアンダーフィル材などの液体
にとって実効的な表面張力が変化するため、アンダーフ
ィル材などの液体の一様な拡散浸入が阻害される。な
お、アンダーフィル材が毛細管現象で拡散する際、溝構
造の直前に作製された凸部によって基板間隔が狭められ
た後、溝構造となる場合には、アンダーフィル材等の液
体にとって実効的な表面張力の変化分を更に大きくする
ことができる。従って、毛細管現象で注入されるアンダ
ーフィル材などの液体は溝構造で止まることになり、ア
ンダーフィル材非充填領域が形成される。例えば、光イ
ンターフェース部分などのアンダーフィル材から保護し
たい部分がアンダーフィル材非充填領域となるようにす
ることにより光インターフェイス部分を保護することが
可能となる。フリップチップ接続する半導体チップとし
ては光インターフェースを有するOEICを例にその構
成例を示すが、フリップチップ接続するチップと実装基
板間の一部にアンダーフィル材の浸入を防ぐ必要のある
ものであれば、チップは特にOEICに限定するもので
はない。
According to the present invention, in a structure in which a chip such as a semiconductor chip is flip-chip connected to a mounting board, a groove structure is formed in at least one of the mounting board and the chip, so that a gap between the chip and the mounting board is partially formed. Create a place where In such a widened portion, the effective surface tension of the liquid such as the underfill material entering due to the capillary phenomenon changes, so that the uniform diffusion and infiltration of the liquid such as the underfill material is hindered. In addition, when the underfill material diffuses due to the capillary phenomenon, when the groove structure is formed after the substrate interval is narrowed by the convex portion formed immediately before the groove structure, it is effective for the liquid such as the underfill material. The change in surface tension can be further increased. Therefore, the liquid such as the underfill material injected by the capillary phenomenon stops in the groove structure, and the underfill material unfilled region is formed. For example, the optical interface portion can be protected by setting the portion, such as the optical interface portion, desired to be protected from the underfill material to be the underfill material non-filling area. As the semiconductor chip to be flip-chip connected, an OEIC having an optical interface is taken as an example to show the configuration example, but if it is necessary to prevent the underfill material from entering a part between the chip to be flip-chip connected and the mounting substrate. The chip is not particularly limited to the OEIC.

【0019】なお、図7に本構造に対してアンダーフィ
ル材を充填した後のイメージ図を示す。OEICチップ
1側面に配置された光インターフェイス部分2にアンダ
ーフィル材が広がり光インターフェイス部分を遮ること
が避けられる。アンダーフィル材が部分的に排除されて
いる様子が図7(b)に示されている。
Incidentally, FIG. 7 shows an image view after the underfill material is filled in this structure. It is possible to prevent the underfill material from spreading to the optical interface portion 2 arranged on the side surface of the OEIC chip 1 and blocking the optical interface portion. A state in which the underfill material is partially removed is shown in FIG. 7 (b).

【0020】[0020]

【実施例】(実施例1)本願発明の第1の実施例とし
て、特にフリップチップ接続する半導体チップとして光
インターフェースを有するOEICを例にその構成例を
示す。ただ、フリップチップ接続するチップと実装基板
との間の一部にアンダーフィル材の浸入を防ぐ必要のあ
るものであれば、特にOEICに限定するものではな
い。
(Embodiment 1) As a first embodiment of the present invention, an example of the configuration will be shown taking an OEIC having an optical interface as a semiconductor chip for flip-chip connection. However, the OEIC is not particularly limited as long as it is necessary to prevent the underfill material from entering the part between the chip to be flip-chip connected and the mounting substrate.

【0021】図1に示すように、OEICのチップ1の
表面に光インターフェース部分2がある場合、この光イ
ンターフェース部分2を取り囲む様に溝構造3を作製す
る。このチップをフリップチップボンディングした後、
アンダーフィル材を溝構造3により囲まれた光インター
フェース部分2の反対側から充填すれば、アンダーフィ
ル材は溝構造で拡散浸入が阻害されるため光インターフ
ェース部分2がアンダーフィル材非充填領域となる。そ
のため、光インターフェイス部分2がアンダーフィル材
で遮られてしまうことはない。
As shown in FIG. 1, when the optical interface portion 2 is provided on the surface of the OEIC chip 1, the groove structure 3 is formed so as to surround the optical interface portion 2. After flip chip bonding this chip,
If the underfill material is filled from the opposite side of the optical interface portion 2 surrounded by the groove structure 3, the underfill material prevents diffusion and invasion in the groove structure, so that the optical interface portion 2 becomes an underfill material unfilled region. . Therefore, the optical interface portion 2 is not blocked by the underfill material.

【0022】図2に溝構造の平面形状の例を数種類示す
が、光インターフェース部分2をアンダーフィル材の浸
入から防止する形状であればどんな形状でも良い。ま
た、溝構造3の深さや溝構造の断面形状は液体の毛細管
現象による拡散を阻害するものであればよく、特に深さ
や断面形状を制限するものではない。
FIG. 2 shows some examples of the planar shape of the groove structure, but any shape may be used as long as it can prevent the optical interface portion 2 from entering the underfill material. Further, the depth of the groove structure 3 and the cross-sectional shape of the groove structure may be any as long as they prevent the diffusion of the liquid due to the capillary phenomenon, and the depth and the cross-sectional shape are not particularly limited.

【0023】溝構造の平面形状としては、凹形状(図2
(a)、(d))、V形状(図2(b)、(e))、線
形状(図2(c))四角形状(図2(f))などが例示
される。もちろんU形状などの他の形状でもよい。な
お、図2(a)、(b)、(c)の溝構造3はOEIC
チップ1のエッジに達している。この場合、アンダーフ
ィル材が溝構造3の外側から回り込むことを防止するこ
とができる。そのため、アンダーフィル材の侵入をより
一層完全に防止することができる。
The planar shape of the groove structure is a concave shape (see FIG. 2).
(A), (d)), V shape (FIG. 2 (b), (e)), linear shape (FIG. 2 (c)) square shape (FIG. 2 (f)), etc. are illustrated. Of course, another shape such as a U shape may be used. The groove structure 3 shown in FIGS. 2A, 2B, and 2C is OEIC.
The edge of chip 1 has been reached. In this case, the underfill material can be prevented from wrapping around from the outside of the groove structure 3. Therefore, intrusion of the underfill material can be prevented even more completely.

【0024】また、図2(f)は光インターフェイス部
分2を取り囲む様に溝構造3が配置されており、この場
合もアンダーフィル材の侵入をより完全に防止すること
ができる。
Further, in FIG. 2 (f), the groove structure 3 is arranged so as to surround the optical interface portion 2, and in this case as well, the intrusion of the underfill material can be prevented more completely.

【0025】(実施例2)本願発明の第2の実施例を図
3に示す。フリップチップ実装するOEICチップ1の
光インターフェース部分2に対向する実装基板5側に溝
構造3を形成する。ここで、溝構造3はフリップチップ
実装されるOEICチップ1の対向面だけではなく、O
EICチップ1の対向面(フリップチップ搭載領域8)
より外側に広く形成しても良い。本例の溝構造3の平面
形状は四角形である。ただ、溝構造3の平面形状や断面
形状などに関しても第1の実施例と同様、光インターフ
ェース部分2をアンダーフィル材の浸入から防止する形
状であればどんな形状でも良いことはいうまでも無い。
(Second Embodiment) FIG. 3 shows a second embodiment of the present invention. The groove structure 3 is formed on the mounting substrate 5 side facing the optical interface portion 2 of the OEIC chip 1 to be flip-chip mounted. Here, the groove structure 3 is formed not only on the facing surface of the OEIC chip 1 to be flip-chip mounted but also on the O
Opposing surface of EIC chip 1 (flip chip mounting area 8)
It may be formed wider outward. The planar structure of the groove structure 3 of this example is a quadrangle. However, it goes without saying that the planar shape and the cross-sectional shape of the groove structure 3 may be any shape as long as it can prevent the optical interface portion 2 from entering the underfill material, as in the first embodiment.

【0026】(実施例3)本願発明の第3の実施例を図
4に示す。フリップチップ実装するOEICチップ1側
と、それに対向する実装基板5側との両側に溝構造3を
形成する場合を示す。この場合、両者の溝構造3は対向
させた時に同位置に来ることが望ましいが、特に一致し
ていなくても良い。本例ではOEICチップ1側の溝構
造はOEICチップ1のエッジまで達したV形状であ
り、また、実装基板5側の光インターフェイス対向部6
にもV形状の溝構造3が設けられている。なお、溝構造
3の平面形状や断面形状などに関しても第1の実施例と
同様、光インターフェース部分をアンダーフィル材の浸
入から防止する形状であればどんな形状でも良いことは
いうまでも無い。
(Embodiment 3) A third embodiment of the present invention is shown in FIG. The case where the groove structure 3 is formed on both sides of the OEIC chip 1 side for flip-chip mounting and the mounting substrate 5 side facing it is shown. In this case, it is desirable that the two groove structures 3 are located at the same position when they are opposed to each other, but they may not be particularly aligned. In this example, the groove structure on the OEIC chip 1 side has a V shape reaching the edge of the OEIC chip 1, and the optical interface facing portion 6 on the mounting substrate 5 side.
Also, a V-shaped groove structure 3 is provided. Needless to say, the planar shape and the cross-sectional shape of the groove structure 3 may be any shape as long as it is a shape that prevents the underfill material from entering the optical interface portion, as in the first embodiment.

【0027】(実施例4)本願発明の第4の実施例を図
5に示す。特に、その側面に光インターフェース2を有
するOEICチップ1を実装する場合を示す。
(Embodiment 4) A fourth embodiment of the present invention is shown in FIG. Particularly, the case where the OEIC chip 1 having the optical interface 2 on its side surface is mounted is shown.

【0028】OEICチップ1には光デバイス12が形
成されている。光デバイス12に続き光導波路11が光
デバイス12に対して光信号を入出力するように設けら
れ、OEICチップ1の側面に光インターフェイス部分
2を有している。
An optical device 12 is formed on the OEIC chip 1. An optical waveguide 11 is provided following the optical device 12 so as to input / output an optical signal to / from the optical device 12, and has an optical interface portion 2 on a side surface of the OEIC chip 1.

【0029】一方、実装基板5にはファイバ保存用V字
型溝10が形成され、ファイバ保存用V字型溝10内に
光ファイバ9が保存される。ここでは光ファイバ9の光
軸を直接あわせるため、実装基板5上におけるフリップ
チップ搭載領域8の外側に光ファイバ9を搭載した例を
示している。もちろん、フリップチップ搭載領域8の外
側の構造については限定するものではない。また図5で
はアンダーフィル材の侵込みを阻止する溝構造3が実装
基板5に作製されている構造を記載するが、実施例1乃
至3と同様、溝構造3はチップ1側か実装基板5側の少
なくてもどちらか一方に存在すれば良い。更に、溝形状
や溝断面形状も特に限定するものではない。フリップチ
ップ搭載するOEICに関しても、図6に例示する様に
チップ1の側面に光インターフェイス部分2が存在する
構造であれば、どんな構造でも良い。
On the other hand, a V-shaped groove 10 for fiber storage is formed in the mounting substrate 5, and the optical fiber 9 is stored in the V-shaped groove 10 for fiber storage. Here, an example is shown in which the optical fiber 9 is mounted outside the flip chip mounting region 8 on the mounting substrate 5 in order to directly align the optical axis of the optical fiber 9. Of course, the structure outside the flip chip mounting area 8 is not limited. Further, although FIG. 5 shows a structure in which the groove structure 3 for preventing the infiltration of the underfill material is formed in the mounting substrate 5, the groove structure 3 is the chip 1 side or the mounting substrate 5 as in the first to third embodiments. It suffices if at least one side exists. Furthermore, the groove shape and the groove cross-sectional shape are not particularly limited. The flip-chip mounted OEIC may have any structure as long as the optical interface portion 2 exists on the side surface of the chip 1 as illustrated in FIG.

【0030】(実施例5)図8(a)は本願発明の他の
実施例を示すものである。
(Embodiment 5) FIG. 8A shows another embodiment of the present invention.

【0031】本例では、実装基板5側にV形状の溝構造
3が形成されている。また、チップ1側の溝構造対向部
分のアンダーフィル材の混入を阻止したい側とは逆側の
溝構造対向部外側にV形状の凸部30が作製されてい
る。図8(b)には基板とチップ1とを重ねた場合の各
構造の位置を示すイメージ図を、また同図a−a‘の断
面図を図8(c)に示す。なお、ここでは、溝構造3及
び凸部30の形状としてV形状をもちいて説明している
が、第1の実施例同様、アンダーフィル材の侵入を阻止
できる形状であればどんなものでもよいことは言うまで
もない。また、本例では凸部は溝構造の作製されていな
い側に作製されているが、図9に示すように溝構造と同
じ側に作製してもよい。
In this example, the V-shaped groove structure 3 is formed on the mounting substrate 5 side. In addition, a V-shaped convex portion 30 is formed outside the groove structure facing portion on the side opposite to the side where it is desired to prevent the underfill material from mixing in the groove structure facing portion on the chip 1 side. FIG. 8 (b) is an image diagram showing the position of each structure when the substrate and the chip 1 are stacked, and FIG. 8 (c) is a sectional view taken along the line aa '. Here, the V-shape is used as the shape of the groove structure 3 and the convex portion 30, but any shape may be used as long as it can prevent the underfill material from entering, as in the first embodiment. Needless to say. Further, in this example, the convex portion is formed on the side where the groove structure is not formed, but it may be formed on the same side as the groove structure as shown in FIG.

【0032】[0032]

【発明の効果】以上、説明したように本願発明によれ
ば、フリップチップボンディング技術を用いた実装方法
において、接続の機械的強度を上げるためにアンダーフ
ィル材などの接着剤を充填する場合、アンダーフィル材
が浸入しては困る領域のみアンダーフィル材の浸入を阻
止する構造を実現することができる。これは、主にフリ
ップチップ実装するチップがOEICなどの様に光イン
ターフェースを持つ場合には、極めて効果的である。
As described above, according to the present invention, in the mounting method using the flip chip bonding technique, when filling an adhesive agent such as an underfill material in order to increase the mechanical strength of the connection, It is possible to realize a structure in which the underfill material is prevented from entering only in a region where it is difficult for the filler material to enter. This is extremely effective mainly when the chip to be flip-chip mounted has an optical interface such as OEIC.

【図面の簡単な説明】[Brief description of drawings]

【図1】半導体チップ上に溝構造を作製した場合の実施
例を示す図。
FIG. 1 is a diagram showing an example in which a groove structure is formed on a semiconductor chip.

【図2】各種溝構造の形状を例示する図。FIG. 2 is a diagram illustrating the shapes of various groove structures.

【図3】実装基板側に溝構造を作製する場合の実施例を
示すフリップチップボンディングのイメージ図。
FIG. 3 is an image diagram of flip-chip bonding showing an example in which a groove structure is formed on the mounting substrate side.

【図4】半導体チップと実装基板の両者に溝構造を作製
する場合の実施例を示すフリップチップボンディングの
イメージ図。
FIG. 4 is an image diagram of flip chip bonding showing an example in which a groove structure is formed on both a semiconductor chip and a mounting substrate.

【図5】半導体チップの側面に光インターフェース部分
が存在する場合の実施例を示すフリップチップボンディ
ングのイメージ図。
FIG. 5 is an image diagram of flip chip bonding showing an embodiment in which an optical interface portion is present on a side surface of a semiconductor chip.

【図6】半導体チップの側面に光インターフェース部分
が存在する溝構造を示す図。
FIG. 6 is a view showing a groove structure in which an optical interface portion is present on a side surface of a semiconductor chip.

【図7】半導体チップの側面に光インターフェース部分
が存在する場合の実施例に対してアンダーフィル材を充
填した後の図。
FIG. 7 is a view after filling an underfill material with respect to an example in which an optical interface portion is present on a side surface of a semiconductor chip.

【図8】実施例5に係る実装構造を示す図である。FIG. 8 is a diagram showing a mounting structure according to a fifth embodiment.

【図9】実施例5の変形例に係る実装構造を示す斜視図
である。
FIG. 9 is a perspective view showing a mounting structure according to a modified example of the fifth embodiment.

【図10】半導体チップ上に作製した光配線構造の例。FIG. 10 shows an example of an optical wiring structure manufactured on a semiconductor chip.

【図11】フリップチップボンディング構造においてア
ンダーフィル材を充填する様子と充填後の様子を示す
図。
FIG. 11 is a view showing a state of filling an underfill material and a state after the filling in a flip chip bonding structure.

【符号の説明】[Explanation of symbols]

1 OEICチップ、 2 光インターフェイス部分(保護部分)、 3 溝構造、 4 バンプ、 5 実装基板、 6 光インターフェイス部分、 7 バンプ接続用パッド、 8 フリップチップ搭載領域、 10 ファイバ保存用V字型溝、 11 光導波路、 12 光デバイス、 20 アンダーフィル材、 21 アンダーフィル材堤み山し部分、 22 アンダーフィル材非充填領域、 23 アンダーフィル材充填領域、 30 凸部 1 OEIC chip, 2 Optical interface part (protection part), 3 groove structure, 4 bumps, 5 mounting board, 6 optical interface part, 7 bump connection pads, 8 flip chip mounting area, 10 V-shaped groove for fiber storage, 11 optical waveguide, 12 optical devices, 20 underfill material, 21 Underfill material 22 Underfill material unfilled area, 23 underfill material filling area, 30 convex

フロントページの続き (72)発明者 徳光 雅美 東京都千代田区大手町二丁目3番1号日本 電信電話株式会社内 Fターム(参考) 5F044 KK02 LL01 RR18 5F088 AA20 BA16 BB01 DA20 EA20 JA03 JA14 Continued front page    (72) Inventor Masami Tokumitsu             2-3-1, Otemachi, Chiyoda-ku, Tokyo Japan             Telegraph and Telephone Corporation F-term (reference) 5F044 KK02 LL01 RR18                 5F088 AA20 BA16 BB01 DA20 EA20                       JA03 JA14

Claims (10)

【特許請求の範囲】[Claims] 【請求項1】 実装基板にチップがフリップチップで実
装され、両者の間にアンダーフィル材が充填された基板
実装構造において、該実装基板あるいは該チップの少な
くともどちらか一方の一部に、アンダーフィル材の侵入
を防ぐ為の溝構造が形成されアンダーフィル材非充填領
域を有することを特徴とする基板実装構造。
1. In a substrate mounting structure in which a chip is flip-chip mounted on a mounting substrate and an underfill material is filled between the both, an underfill is formed on at least one of the mounting substrate and the chip. A substrate mounting structure characterized in that a groove structure for preventing material intrusion is formed and has an underfill material unfilled region.
【請求項2】 前記アンダーフィル材が、接着剤である
ことを特徴とする請求項1記載の基板実装構造。
2. The board mounting structure according to claim 1, wherein the underfill material is an adhesive.
【請求項3】 前記溝構造が前記チップ側に作製される
場合、該溝構造が前記チップのエッジにまで達している
ことを特徴とする請求項1又は2記載の基板実装構造。
3. The substrate mounting structure according to claim 1, wherein when the groove structure is formed on the chip side, the groove structure reaches an edge of the chip.
【請求項4】 前記溝構造が前記アンダーフィル材非充
填領域を取り囲む様に配置されていることを特徴とする
請求項1又は2記載の基板実装構造。
4. The board mounting structure according to claim 1, wherein the groove structure is arranged so as to surround the underfill material non-filled region.
【請求項5】 前記溝構造が前記実装基板側に作製され
る場合には、前記チップの搭載領域の外部にまで溝構造
が広がっていることを特徴とする請求項1又は2記載の
基盤実装構造。
5. The substrate mounting according to claim 1, wherein when the groove structure is formed on the mounting substrate side, the groove structure extends to the outside of the mounting area of the chip. Construction.
【請求項6】 前記溝構造が前記基板及び前記チップの
両方に作製される場合、両溝構造が対向していることを
特徴とする請求項1乃至5のいずれか1項記載の基盤実
装構造。
6. The substrate mounting structure according to claim 1, wherein when the groove structure is formed on both the substrate and the chip, the groove structures are opposed to each other. .
【請求項7】 前記溝構造が前記チップ側又は前記実装
基板側の少なくともどちらか一方に製作される場合、前
記溝構造の周辺部あるいは前記溝構造が作製されていな
い側の溝構造対向部分外側に凸部を設けることを特徴と
する請求項1乃至5のいずれか1項記載の基板実装構
造。
7. When the groove structure is formed on at least one of the chip side and the mounting substrate side, the periphery of the groove structure or the outside of the groove structure facing portion on the side where the groove structure is not formed. The board mounting structure according to claim 1, wherein a convex portion is provided on the substrate.
【請求項8】 前記チップは、半導体チップであること
を特徴とする請求項1乃至7のいずれか1項記載の基板
実装構造。
8. The substrate mounting structure according to claim 1, wherein the chip is a semiconductor chip.
【請求項9】 前記アンダーフィル非充填領域は、光イ
ンターフェイス部分であることを特徴とする請求項1乃
至8のいずれか1項記載の基板実装構造。
9. The substrate mounting structure according to claim 1, wherein the underfill non-filled region is an optical interface portion.
【請求項10】 請求項1乃至9のいずれか1項記載の
基板実装構造を有することを特徴とする半導体装置。
10. A semiconductor device having the substrate mounting structure according to claim 1. Description:
JP2002044052A 2002-02-20 2002-02-20 Substrate mounting structure and semiconductor device Expired - Fee Related JP3818441B2 (en)

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