JP2003243395A - Method for fabricating semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent stripping of a pattern due to dense/sparse cross-sectional shape of electroplating interconnections. <P>SOLUTION: Interconnections 5 are formed by electroplating based on a resist pattern 4 formed on a semiconductor substrate 1, and the rear surface of the semiconductor substrate 1 is ground while pasting a protective film to the surface thereof provided with the electroplating interconnections 5. In such a method for fabricating a semiconductor device, a dummy pattern 7 is formed along the side on the semiconductor substrate 1 where the density of the electroplating interconnections 5 is sparse before the resist pattern 4 is formed. Since no stress is applied to the resist pattern 4 at the part of the electroplating interconnections 5 when an electroplating interconnection layer is grown after the resist pattern 4 is formed, the electroplating interconnections 5 are grown perpendicularly to the substrate 1. Since the electroplating interconnections 5 are not tapered, they are not stripped when the surface protective layer is stripped after the rear surface is ground. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a highly integrated MMIC (Monolithic M).
The present invention relates to a method for manufacturing a semiconductor device using a compound semiconductor substrate used for icrowave IC (hereinafter referred to as MMIC).

[0002]

2. Description of the Related Art In recent years, MMICs used in transmission / reception circuits of mobile communication devices such as mobile phones have been miniaturized and patterns have been miniaturized. In such an integrated circuit, the cross-sectional shape of the wiring portion changes due to the density of the wiring pattern, which may cause pattern peeling when peeling the surface protection tape for backside grinding or pattern peeling due to water pressure during the dicing process.

FIG. 12 to FIG. 12 showing a manufacturing process of a conventional MMIC.
This phenomenon will be specifically described with reference to FIG.

First, as shown in FIG. 12, in order to avoid a short circuit between elements such as field effect transistors (FETs) and resistors formed on a compound semiconductor substrate 1 such as GaAs,
The interlayer insulating film 2 made of a silicon nitride film (SiN) or the like is formed by a method such as chemical vapor deposition (CVD). Then, T
A plating base conductive film 3 made of i, Pt, and Au is formed by a method such as vapor deposition and sputtering. Then, a resist pattern 4 is formed with a photoresist.

Next, as shown in FIG. 13, electrolytic plating wiring 5 is formed by electrolytic plating. At this time, during the growth of the electroplated wiring 5, the resist 4a on the sparse pattern side has a tapered shape due to the density of the resist pattern 4, and the electrolysis that grows on the tapered resist 4a portion. The plated wiring 5a has a reverse taper shape.

Next, as shown in FIG. 14, after removing the resist pattern 4 by an asher or the like, unnecessary portions of the plating base conductive film 3 are etched by ion milling using the electrolytic plating wiring 5 as a mask for selective etching.

[0007]

The semiconductor substrate thus formed is subjected to backside grinding in order to reduce the thickness of the substrate. The surface of the compound semiconductor substrate 1 is protected for surface protection during this backside grinding. UV tape can be attached to the electrolytic plating wiring 5 of. At this time, as shown in FIG. 15, the adhesive 6 of the surface protection tape enters the electrolytic plating wiring 5.

After grinding the back surface of the compound semiconductor substrate 1, the UV tape is irradiated with ultraviolet rays to soften the adhesive 6 and peel it off. At the time of peeling, the adhesive 6 on the UV tape is removed as shown in FIG. The electroplated wiring 5a having a reverse taper shape is caught and the gold wiring is lifted.

Further, as shown in FIG. 17, the electrolytically-plated wiring 5a having an inverse taper shape is likely to be subjected to water pressure stress during dicing.
Is easy to peel off.

An object of the present invention is to prevent pattern peeling caused by unevenness of the cross-sectional shape of electrolytic plated wiring.

[0011]

According to a method of manufacturing a semiconductor device of the present invention, wiring is formed by electrolytic plating based on a resist pattern formed on a semiconductor substrate, and the surface of the semiconductor substrate provided with this electrolytic plating wiring is protected. In a method of manufacturing a semiconductor device, wherein a back surface of the semiconductor substrate is ground while a tape is attached, before forming the resist pattern,
It is characterized in that a dummy pattern is formed along the side where the density of the electroplated wiring is sparse.

In the present invention, since the dummy pattern is formed in advance on the side where the electroplating wiring is sparse, after forming the resist pattern, when the electroplating wiring layer grows, the resist of the electroplating wiring portion is resisted. The pattern is not stressed and the electroplated wiring grows perpendicular to the substrate. As a result, the electroplated wiring does not have a tapered shape, and therefore the electroplated wiring does not peel off when the surface protection tape is peeled off after grinding the back surface.

The method of manufacturing a semiconductor device of the present invention can be suitably applied to a compound semiconductor such as MMIC in which a fine wiring pattern is formed.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION A semiconductor manufacturing process according to an embodiment of the present invention will be described below with reference to FIGS.

First Process As shown in FIG. 1, in order to avoid short circuits between elements such as FETs and resistors formed on a compound semiconductor substrate 1 such as GaAs, an interlayer insulating film 2 made of SiN or the like is formed by CVD or the like. The film is formed by the method.

Second Step As shown in FIG. 2, a plating base conductive film 3 made of Ti, Pt, and Au is formed by a method such as vapor deposition and sputtering.

Third Step As shown in FIG. 3, the dummy pattern 7 is formed by a method such as photoresist. The dummy pattern 7 may be the same material as the resist material, or may be a nitride film or oxide film material.

Fourth Step As shown in FIG. 4, a resist film 4'is applied with the dummy pattern 7 left.

Fifth step As shown in FIG. 5, by a method such as photoresist,
A resist pattern 4 is formed.

Sixth Process As shown in FIG. 6, electrolytic plating wiring 5 is formed by electrolytic plating. In the plating growth in this step, unlike the conventional technique, the dummy pattern 7 suppresses the deformation of the resist on the sparse pattern side, and the electrolytic plating wiring 5 does not have a reverse taper shape. The arrangement of the electroplated wiring 5 and the dummy pattern 7 thus formed is shown in FIG. 7 (plan view). The dummy pattern 7 is arranged outside the electrolytic plating wiring 5.

Seventh step When the resist pattern 4 and the dummy pattern 7 are removed by an asher or the like, only the electrolytic plating wiring 5 remains as shown in FIG. Since the dummy pattern 7 does not contribute to the operation of the semiconductor device, it need not always be removed.

Eighth Process As shown in FIG. 9, unnecessary portions of the plating base conductive film 3 are removed by etching by ion milling. At this time, the electroplated wiring 5 serves as a mask for selective etching. Next, although not shown, a wiring protection film is deposited on the electroplated wiring 5 by a method such as CVD.

The side end surface of the electroplated wiring 5 thus formed does not have a tapered shape due to the sparse / dense dependence of the wiring pattern as in the conventional case, and the compound semiconductor substrate 1
To be perpendicular to. Therefore, as shown in FIG. 10, when the surface protection tape such as the UV tape attached to the electrolytic plated wiring 5 during the back surface grinding of the substrate is peeled off after the back surface grinding, the glue 6 of the surface protection tape is caught. The electrolytic plating wiring 5 will not be peeled off.

Further, as shown in FIG. 11, since the water pressure during dicing does not concentrate on the end surface of the electroplated wiring 5, the electroplated wiring 5 does not peel off.

[0025]

According to the present invention, in the semiconductor manufacturing method, by forming the dummy pattern in advance on the side where the electroplating wiring is sparse, the electroplating wiring is not formed in a tapered shape, and therefore the back surface is not formed. Electrolytically plated wiring does not peel off when the surface protection tape is peeled off after grinding. It is also possible to prevent the electroplated wiring from peeling off due to water pressure during dicing.

The dummy pattern can be appropriately changed to another pattern such as an intermittent pattern without departing from the gist of the present invention.

The semiconductor device manufacturing method of the present invention can be suitably applied to a compound semiconductor such as GaAs in which a fine wiring pattern is formed.

[Brief description of drawings]

FIG. 1 is a sectional view showing a first step of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a second step of the semiconductor device according to the embodiment of the present invention.

FIG. 3 is a cross-sectional view showing a third step of the semiconductor device according to the embodiment of the present invention.

FIG. 4 is a cross-sectional view showing a fourth step of the semiconductor device according to the embodiment of the present invention.

FIG. 5 is a cross-sectional view showing a fifth step of the semiconductor device according to the embodiment of the present invention.

FIG. 6 is a cross-sectional view showing a sixth step of the semiconductor device according to the embodiment of the present invention.

FIG. 7 is a plan view of FIG.

FIG. 8 is a cross-sectional view showing a seventh step of the semiconductor device according to the embodiment of the present invention.

FIG. 9 is a cross-sectional view showing an eighth step of the semiconductor device according to the embodiment of the present invention.

FIG. 10 is a cross-sectional view showing a state when the surface protection tape is peeled off according to the embodiment of the present invention.

FIG. 11 is a cross-sectional view showing a state in which the influence of water pressure during dicing according to the embodiment of the present invention has been eliminated.

FIG. 12 is a cross-sectional view showing a manufacturing process of a conventional semiconductor device.

FIG. 13 is a cross-sectional view showing the manufacturing process of the conventional semiconductor device.

FIG. 14 is a cross-sectional view showing the manufacturing process of the conventional semiconductor device.

FIG. 15 is a cross-sectional view showing the manufacturing process of the conventional semiconductor device.

FIG. 16 is a cross-sectional view showing a state when a UV tape is peeled off in a conventional semiconductor device.

FIG. 17 is a cross-sectional view showing the influence of water pressure during dicing in a conventional semiconductor device.

[Explanation of symbols]

1 Compound semiconductor substrate 2 Interlayer insulation film 3 Plating base conductive film 4 Resist pattern 4'resist film 5 Electroplating wiring 6 Surface protection tape glue 7 Dummy pattern

Claims (4)

[Claims] 1. A back surface of the semiconductor substrate is ground by forming wiring by electrolytic plating based on a resist pattern formed on the semiconductor substrate and attaching a protective tape to the surface of the semiconductor substrate provided with the electrolytic plating wiring. In the method of manufacturing a semiconductor device, a dummy pattern is formed along the side where the density of the electroplated wiring is sparse before forming the resist pattern. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the dummy pattern is removed after the electrolytic plating wiring is formed. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the dummy pattern is left on the semiconductor substrate even after the electrolytic plating wiring is formed. 4. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor substrate is a compound semiconductor substrate.