JP2003242101A5 - - Google Patents

Download PDF

Info

Publication number
JP2003242101A5
JP2003242101A5 JP2002044698A JP2002044698A JP2003242101A5 JP 2003242101 A5 JP2003242101 A5 JP 2003242101A5 JP 2002044698 A JP2002044698 A JP 2002044698A JP 2002044698 A JP2002044698 A JP 2002044698A JP 2003242101 A5 JP2003242101 A5 JP 2003242101A5
Authority
JP
Japan
Prior art keywords
bus
bus width
bits
data
unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2002044698A
Other languages
English (en)
Japanese (ja)
Other versions
JP4135374B2 (ja
JP2003242101A (ja
Filing date
Publication date
Application filed filed Critical
Priority to JP2002044698A priority Critical patent/JP4135374B2/ja
Priority claimed from JP2002044698A external-priority patent/JP4135374B2/ja
Publication of JP2003242101A publication Critical patent/JP2003242101A/ja
Publication of JP2003242101A5 publication Critical patent/JP2003242101A5/ja
Application granted granted Critical
Publication of JP4135374B2 publication Critical patent/JP4135374B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

JP2002044698A 2002-02-21 2002-02-21 拡張カードおよび拡張カードの記憶部へのデータ書き込み方法 Expired - Fee Related JP4135374B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2002044698A JP4135374B2 (ja) 2002-02-21 2002-02-21 拡張カードおよび拡張カードの記憶部へのデータ書き込み方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002044698A JP4135374B2 (ja) 2002-02-21 2002-02-21 拡張カードおよび拡張カードの記憶部へのデータ書き込み方法

Publications (3)

Publication Number Publication Date
JP2003242101A JP2003242101A (ja) 2003-08-29
JP2003242101A5 true JP2003242101A5 (enExample) 2005-06-23
JP4135374B2 JP4135374B2 (ja) 2008-08-20

Family

ID=27783969

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002044698A Expired - Fee Related JP4135374B2 (ja) 2002-02-21 2002-02-21 拡張カードおよび拡張カードの記憶部へのデータ書き込み方法

Country Status (1)

Country Link
JP (1) JP4135374B2 (enExample)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FI20022113A7 (fi) * 2002-11-29 2004-08-06 Nokia Corp Menetelmä ja järjestelmä väyläleveyden tunnistamiseksi, elektroniikkalaite ja oheislaite
JP4652274B2 (ja) * 2006-05-10 2011-03-16 富士フイルム株式会社 デジタルカメラ

Similar Documents

Publication Publication Date Title
EP1065594A3 (en) Error detection and correction circuit in a flash memory
JPH09259033A5 (enExample)
ATE532182T1 (de) Erfassung von lesedaten in einem synchrondatenspeicher
EP1102261A3 (en) Data recorder capable to prevent buffer underrun errors
EP1763034A3 (en) Information playback system using information storage medium
WO2008020297A3 (en) Systems, methods, and apparatus for recording of graphical display
DE69223090D1 (de) Busüberwachung für Rechnersystemführer
EP1975799A3 (en) Implementing read/write, multi-versioned file system on top of backup data
EP1605344A3 (en) Page printer and page print system
WO2008130703A8 (en) Clock synchronization in a memory system
WO2002017323A3 (en) Synchronized write data on a high speed memory bus
WO2005041055A3 (en) Echo clock on memory system having wait information
EP1659494A3 (en) Method and apparatus for classifying memory errors
PT2439680E (pt) Método e dispositivo para leitura e gravação de cartões de memória
JP2000011646A5 (enExample)
TW200705200A (en) Data transfer control device, image processing device, and data transfer control method
EP1158515A3 (en) Method and apparatus for recording data at accurate location on recording medium
JP2003242101A5 (enExample)
EP1220077A3 (en) Data processing apparatus and memory card using the same
WO2008042201A3 (en) Memory write timing system
WO2001037076A3 (en) Method and apparatus for ring buffer flow error detection
EP1758023A3 (en) Data error detection during media write
DE60236913D1 (de) Verfahren und Schaltung zur Initialisierung eines Laufzeitausgleichpuffers in einem taktweitergeleiteten System
JP2004018227A (ja) 用紙端検出装置
JP4821628B2 (ja) パケットバッファfifoメモリ装置