JP2003241211A - Method of manufacturing liquid crystal display element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a liquid crystal display element, which can reduce the loading effect of dry etching in an array process for forming a TFT thin film transistor of a liquid crystal display device. <P>SOLUTION: The aperture ratio of punched parts is increased by forming punched dummy patterns 7 in a large-area pattern 5 in the peripheries of inter- wiring spaces 6 for separating the large-area pattern 5. Because of the dummy patterns 7, the problem of the residual caused by the loading effect of dry etching for pattern formation, which occurs in the inter-wiring spaces 6, is resolved. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a liquid crystal display device using a TFT (thin film transistor).

[0002]

2. Description of the Related Art Conventionally, particularly in the case where fine processing such as semiconductors is required, a loading effect in which a processed shape and a rate differ depending on a pattern density difference appears in a dry etching technique.

The formation of an array wiring process of a conventional liquid crystal display device will be described below. A resist pattern 3 is formed on the conductive film 2 deposited on the glass substrate 1, and a wiring pattern 4 is formed by dry etching. At this time, a wiring pattern is formed inside the pixel body, and at the same time, a pattern is formed as a peripheral circuit outside the pixel body. FIG. 4 is a plan view showing this conventional peripheral circuit pattern. In FIG. 4, a large area pattern 5 of the pixel body may be arranged as a peripheral wiring in order to reduce the resistivity, and a large inter-wiring space 6 is provided in the large area pattern 5 to separate the wirings. They are arranged to separate the wires.

[0004]

However, in the configuration of the above-mentioned conventional example, due to the loading effect of the dry etching which is a process for forming the wiring pattern by the conductive film on the glass substrate, the wiring between the wirings in the large area pattern 5 is There is a problem that the etching rate of the space 6 is lowered and etching residue is generated. When the etching residue is generated, a short circuit occurs between the wirings, which causes a problem of image abnormality.

An object of the present invention is to solve the above conventional problems and to propose a method of manufacturing a liquid crystal display device capable of reducing the loading effect of dry etching.

[0006]

In order to achieve this object, a method of manufacturing a liquid crystal display device according to the present invention comprises a method of forming a metal wiring in an array forming step of the liquid crystal display element, wherein a peripheral metal wiring outside the pixel body is formed. When forming the portion, a minute blanking pattern between the wirings inside the large area pattern of the peripheral metal wiring portion and a dummy blanking pattern inside the large area pattern are formed.

In the above method, it is preferable that the dummy pattern is formed inside the large area pattern and is not a pattern for separating wiring.

The dummy pattern is preferably the same as or larger than the space between the wirings.

Further, it is preferable that the dummy pattern is formed adjacent to a space between wirings.

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

1A and 1B are cross-sectional views of a wiring forming process according to an embodiment of the present invention, where FIG. 1A is a cross-sectional view before etching and FIG. 1B is a cross-sectional view after etching. Prior to etching, an indium-tin oxide alloy (ITO) transparent conductive film having a predetermined film thickness is formed on the glass substrate 1, a resist is applied, and then exposure is performed to remove unnecessary portions to obtain a predetermined film. Pattern, and then the transparent conductive film is etched to form the wiring pattern 4.

Next, FIG. 2 is a plan view showing that dummy patterns are arranged in the peripheral circuit pattern of one embodiment of the present invention. In FIG. 2, a large area pattern 5 is arranged as a peripheral wiring in order to reduce the resistivity, and an inter-wiring space 6 is arranged in the large area pattern 5 in order to separate the wirings. Are separated. A dummy pattern 7 is arranged around the inter-wiring space 6 to increase the area ratio of the blank around the inter-wiring space 6. As a result, the loading effect during dry etching can be reduced and the generation of etching residues can be suppressed. Further, as an example of the pattern area ratio, it is possible to suppress the etching residue by realizing a pattern ratio of 90% or less per 1 mm ² (a punched pattern is 10% or more).

Further, the dummy pattern 7 secures a space width equal to or larger than that of the blank pattern 6. As an example, the width of the dummy pattern 7 is 20 to 5
The range is 0 μm and the length is 500 nm or more.

The same effect can be obtained by forming the dummy pattern adjacent to the inter-wiring space 6 as in the dummy pattern 8 of FIG. In this case, as an example, the width of the dummy pattern 8 is 500 nm.
As described above, the length is 200 nm or more.

As described above, the large area pattern 5 is separated by arranging the dummy patterns 7 and 8 around the inter-wiring space 6 separating the large area pattern 4 of the peripheral circuit pattern outside the pixel body. While suppressing the reduction of the etching rate of the open pattern of the inter-wiring space 6,
The loading effect can be reduced.

[0016]

As described above, according to the present invention, a dummy punching pattern is formed around a minute inter-wiring space existing inside a large area pattern, so that a loading effect that occurs when the pattern is formed by dry etching. Can be suppressed,
Generation of etching residues can be suppressed.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a wiring forming process according to an embodiment of the present invention, in which (a) is a cross-sectional view before etching and (b) is a cross-sectional view after etching.

FIG. 2 is a plan view of the wiring formation according to the embodiment of the present invention.

FIG. 3 is a plan view of wiring formation according to another embodiment of the present invention.

FIG. 4 is a plan view showing a conventional wiring formation.

[Explanation of symbols]

1 glass substrate 2 Conductive film 3 resist pattern 4 wiring pattern 5 large area pattern 6 space between wires 7 Large area internal dummy pattern 8 Inter-wiring space adjacent dummy pattern

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) G09F 9/35 G09F 9/35 // H01L 21/3065 H01L 21/302 105A F term (reference) 2H088 FA19 FA23 FA24 HA02 HA08 MA20 2H092 GA24 HA04 JA24 MA18 NA11 PA01 5C094 AA42 BA43 CA19 EA01 EA05 FA01 HA08 5F004 AA01 DB13 EA21 EB02 5G435 AA17 BB12 CC09 HH12 KK05 LL06 LL07 LL08

Claims (4)

[Claims] 1. In a process of forming an array of liquid crystal display elements, when forming a peripheral metal wiring portion outside a pixel body in a step of forming a metal wiring, a minute gap between wirings inside the large area pattern of the peripheral metal wiring portion is formed. A method of manufacturing a liquid crystal display device, comprising forming a punching pattern and a dummy punching pattern inside the large area pattern. 2. The method of manufacturing a liquid crystal display device according to claim 1, wherein the dummy pattern is formed inside a large area pattern. 3. The method of manufacturing a liquid crystal display device according to claim 1, wherein the dummy pattern is equal to or larger than a space between wirings. 4. The method of manufacturing a liquid crystal display device according to claim 1, wherein the dummy pattern is formed adjacent to a space between wirings.