KR20080048103A - Display substrate and method of manufactruing the same - Google Patents

Abstract

A display substrate and a manufacturing method thereof are provided to hide a semiconductor pattern, exposed between a source electrode and a drain electrode, by using an etch stopper pattern, thereby preventing performance deterioration of a TFT(Thin Film Transistor) of the display substrate and more reducing manufacturing processes of the display substrate. A gate line structure(20) comprises a gate electrode(10) and a gate line(15). The gate electrode is disposed in a display region of a substrate(1), and includes a first gate pattern and a second gate pattern disposed on the first gate pattern. The gate line is prolonged from a pad area disposed in a peripheral region of the display region from the gate electrode. A pixel electrode(30) is formed in the same layer as the first gate pattern on the substrate. A gate insulating layer pattern covers the gate line structure and the pixel electrode, and has a contact hole for exposing a part of the pixel electrode. A semiconductor pattern covers the gate electrode. A data line structure(60) includes a source electrode(65) electrically connected with the semiconductor pattern, and a data line(67) prolonged from the source electrode to the pad region. A drain electrode(80) is electrically connected with the semiconductor pattern, and electrically connected with the exposed pixel electrode. The drain electrode is spaced from the source electrode. An etch stopper pattern(90) is disposed in an exposed part of the semiconductor pattern exposed by the source electrode and the drain electrode.

Description

DISPLAY SUBSTRATE AND METHOD OF MANUFACTRUING THE SAME}

1 is a plan view of a display substrate according to an exemplary embodiment of the present invention.

FIG. 2 is a cross-sectional view taken along the line II ′ of FIG. 1.

3 is a cross-sectional view taken along the line II-II ′ of FIG. 1.

4 is a cross-sectional view taken along the line III-III ′ of FIG. 1.

5 to 14 are cross-sectional views illustrating a method of manufacturing a display device according to an embodiment of the present invention.

The present invention relates to a display substrate and a method of manufacturing the same. More specifically, the present invention relates to a display substrate and a method for manufacturing the same, which improve the device reliability of the thin film transistor and reduce the number of manufacturing steps.

Recently, the development of an information processing apparatus capable of processing a large amount of data in a short time and the development of a technology of a display apparatus for displaying data processed by the information processing apparatus as an image are rapidly progressing.

A display device for processing data processed by an information processing device includes a liquid crystal display device for displaying information using a liquid crystal, an organic light generating device for displaying information using an organic light emitting material, and a plasma for displaying information using a plasma. Display panels and the like are typical.

Among them, liquid crystal display devices have been spotlighted as next generation advanced display devices having low power consumption and good portability.

The liquid crystal display includes a thin film transistor substrate including a thin film transistor (TFT), a color filter substrate having a color filter, and a liquid crystal injected therebetween. The liquid crystal display generates an image by using a difference in refractive index of light according to the anisotropy of the liquid crystal.

Thin-film transistors for displaying full-color images in liquid crystal displays are manufactured by using a five-mask mask manufacturing process and a four-mask mask manufacturing process, but the four-mask mask manufacturing process uses a diffraction exposure process, so the process margin is increased. Since it is very small, there is a problem in that device characteristics are nonuniform, and in the case of a five-sheet mask fabrication process, the source / drain electrodes are etched and a part of the high concentration impurity amorphous silicon film is exposed to reduce the characteristics of the thin film transistor.

Accordingly, one object of the present invention is to provide a display substrate having a thin film transistor with improved device characteristics.

Another object of the present invention is to provide a method of manufacturing the display substrate.

The display substrate for implementing the above object of the present invention is a display area from a gate electrode, a gate electrode disposed in the display area of the substrate and including a first gate pattern and a second gate pattern disposed on the first gate pattern. A gate wiring structure having a gate wiring extending to a pad region disposed at a periphery thereof, a contact covering a pixel electrode, a gate wiring structure and a pixel electrode formed on the same layer as the first gate pattern on the substrate, and exposing a portion of the pixel electrode; A data wiring structure including a gate insulating film pattern having holes, a semiconductor pattern covering the gate electrode, a source electrode electrically connected to the semiconductor pattern, a data wiring extending from the source electrode to the pad region, and electrically connected and exposed to the semiconductor pattern A drain electrically connected to the pixel electrode and spaced apart from the source electrode It comprises an etch stopper pattern disposed on the exposed part of the electrode and the source electrode and the semiconductor pattern exposed by the drain electrode.

According to another aspect of the present invention, there is provided a method of manufacturing a display substrate, including: a gate wiring structure having a gate electrode and a gate wiring having a first gate pattern and a second gate pattern disposed on the first gate pattern; Forming a pixel electrode formed on the same layer as the first gate pattern, sequentially forming a gate insulating layer, a semiconductor layer, and an etch stopper layer covering the gate wiring and the pixel electrode, the etch stopper layer, the semiconductor layer; Patterning the gate insulating layer to form a contact hole exposing the pixel electrode, patterning the etch stopper layer and the semiconductor layer together to form a semiconductor pattern and an etch stopper pattern, respectively, through the contact hole Source / drain metal electrically connected to the pixel electrode and covering the semiconductor pattern Forming a film and patterning the source / drain metal film to form a data line having a source electrode connected on the semiconductor pattern and a drain electrode connected to the pixel electrode through the contact hole.

Hereinafter, a display substrate and a manufacturing process thereof according to embodiments of the present invention will be described in detail with reference to the accompanying drawings, but the present invention is not limited to the following embodiments, and the general knowledge in the art. Those skilled in the art can implement the present invention in various other forms without departing from the technical spirit of the present invention.

Display board ( Display Apparatus )

1 is a plan view of a display substrate according to an exemplary embodiment of the present invention. FIG. 2 is a cross-sectional view taken along the line II ′ of FIG. 1. 3 is a cross-sectional view taken along the line II-II ′ of FIG. 1. 4 is a cross-sectional view taken along the line III-III ′ of FIG. 1.

Referring to FIG. 1, the display substrate 100 includes a substrate 1, a gate wiring structure 20, a pixel electrode 30, a gate insulating film pattern 40, a semiconductor pattern 50, a data wiring structure 60, The drain electrode 80 and the etch stopper pattern 90 are included.

The substrate 1 includes, for example, a transparent glass substrate.

The gate wiring structure 20 is disposed on the substrate 1. The gate wiring structure 20 includes a gate electrode 10 and a gate wiring 15.

The gate wiring 15 is disposed on the substrate 1 in the first direction. Although only one gate wiring 15 is shown in FIG. 1, a plurality of gate wirings 15 are disposed on the substrate 1. For example, when the resolution of the display substrate 100 is 1,280 × 1,024, 1,024 gate wirings 15 are disposed on the substrate 1. The gate line 15 extends from the display region DR of the substrate 1 to the peripheral region PR surrounding the display region DR.

The gate electrode 10 extends from the gate wiring 15 along the substrate 1 in a second direction substantially perpendicular to the first direction. Although only one gate electrode 10 is shown in FIG. 1, a plurality of gate electrodes 10 protrude from the gate wiring 15. For example, when the resolution of the display substrate 100 is 1,280 × 1,024, 1,280 × 3 gate electrodes 10 protrude from one gate wire 15.

Referring to FIG. 3, the gate wiring structure 20 including the gate electrode 10 and the gate wiring 15 disposed on the substrate 1 is disposed in the display area DR, and the gate electrode 10 and The gate line 15 commonly includes a first gate pattern 12 and a second gate pattern 14 disposed on the first gate pattern 12.

In this embodiment, examples of materials that can be used as the first gate pattern 12 include indium tin oxide, zinc indium oxide, amorphous tin indium oxide, and the like.

In addition, examples of materials that may be used as the second gate pattern 14 include aluminum, aluminum alloys, tungsten, tungsten alloys, titanium alloys, and the like.

Referring to FIG. 4, a pad part disposed in the peripheral area PR disposed around the display area DR of the gate wiring 15 including the first gate pattern 12 and the second gate pattern 14 may be provided. 16, the second gate pattern 14 is removed to expose the first gate pattern 12. In this embodiment, oxidation of the pad portion 16 can be suppressed by removing the second gate pattern 14 from the pad portion 16 of the gate wiring 15.

The pixel electrode 30 is disposed directly on the substrate 1. That is, the pixel electrode 30 is formed on the same layer as the first gate pattern 12. The pixel electrode 30 has a substantially rectangular shape in plan view. Examples of materials that can be used as the pixel electrode 30 may include tin indium oxide, zinc indium oxide, amorphous tin indium oxide, and the like.

1 and 2, the gate insulating layer pattern 40 covers the gate wiring structure 20 and the pixel electrode 30, and the gate insulating layer pattern 40 exposes a portion of the pixel electrode 30. Has 42. In this embodiment, examples of the material that can be used as the gate insulating film pattern 40 include an oxide film or a nitride film.

In the present embodiment, although the pixel electrode 30 is covered with the gate insulating film pattern 40, the transmittance of the light passing through the pixel electrode 30 is not significantly affected because the thickness of the gate insulating film pattern 40 is thin.

The semiconductor pattern 50 is formed on the gate insulating layer pattern 40 corresponding to each gate electrode 10. In the present exemplary embodiment, the semiconductor pattern 50 may include an amorphous silicon pattern and an n + amorphous silicon pattern implanted with a high concentration of impurities.

The data wiring structure 60 includes a source electrode 65 and a data wiring 67.

The source electrode 65 is electrically connected to the semiconductor pattern 50. In this embodiment, examples of the material that can be used as the source electrode 65 may include aluminum, aluminum alloy, and the like. In the present embodiment, the source electrode 65 is connected to the semiconductor pattern 50 disposed on each gate electrode 10. In this embodiment, the source electrode 65 is arranged in the first direction.

The data line 67 is disposed on the gate insulating layer pattern 40 and is formed integrally with the source electrode 65. In the present embodiment, the data line 67 extends in the second direction substantially perpendicular to the gate line 15. Although only one data line 67 is shown in FIG. 1, a plurality of data lines 67 are disposed on the substrate 1. For example, when the resolution of the display substrate 100 is 1,280 × 1,024, 1,280 × 3 data lines 67 are disposed on the substrate 1. The data line 67 extends from the display region DR of the substrate 1 to the peripheral region PR surrounding the display region DR.

The drain electrode 80 is disposed on the semiconductor pattern 50. The drain electrode 80 is spaced apart from the source electrode 65 by a predetermined interval. In the present embodiment, the drain electrode 80 is substantially the same as the material forming the source electrode 65.

The etch stopper pattern 90 is disposed on the semiconductor pattern 50. Specifically, the etch stopper pattern 90 covers a part of the semiconductor pattern 50 exposed between the source electrode 65 and the drain electrode 80, so that the semiconductor pattern 50 is damaged by a subsequent process. prevent. In the present embodiment, the etch stopper pattern 90 may include an oxide film pattern including an oxide and a nitride film pattern including a nitride.

Referring back to FIG. 4, a pad protection member 92 may be disposed around the pad portion 16 of the gate wiring 15 of the gate wiring structure 20. The pad part protection member 92 is disposed along the edge of the first gate pattern 12 to form a concave groove in the center of the pad part 16 to protect the edge of the first gate pattern 12. In addition, the pad protection member 92 also greatly improves the bonding force between the pad 16 and the tape carrier package TCP when tab bonding the pad 16 to the tape carrier package TCP. do.

Manufacturing method of display element Method of Manufacturing the Display Apparatus )

5 to 14 are cross-sectional views illustrating a method of manufacturing a display device according to an embodiment of the present invention.

Referring to FIG. 5, the first conductive layer 12a and the second conductive layer 14a are sequentially formed on the substrate 1.

In the present embodiment, the first conductive layer 12a is formed by a sputtering process or a chemical vapor deposition process. The first conductive layer 12a includes a transparent and conductive material. Examples of the material constituting the first conductive layer 12a include indium tin oxide, indium zinc oxide, amorphous indium oxide, and the like.

After the first conductive layer 12a is formed, a second conductive layer 14a is formed on the first conductive layer 12a. The second conductive layer 14a is formed by a sputtering process, a chemical vapor deposition process, or the like, and examples of the material constituting the second conductive layer 14a include aluminum, aluminum alloys, tungsten and titanium.

Referring to FIG. 6, after the first conductive layer 12a and the second conductive layer 14a are formed on the substrate 1, a photoresist film (not shown) is formed over the entire surface of the second conductive layer 14a. Is formed. In this embodiment, the photoresist film is formed through a spin coating process or a slit coating process.

After the photoresist film is formed, the photoresist film is subjected to diffraction exposure and development using a first mask (not shown) which is a diffraction exposure mask to form a photoresist pattern 16 on the second conductive layer 14a. The photoresist pattern 16 includes a first photoresist pattern portion 16a and a second photoresist pattern portion 16b.

The first photoresist pattern portion 16a is formed in the gate wiring structure formation region including the gate electrode and the gate wiring to be described later, and the second photoresist pattern portion 16b is formed in the pixel electrode formation region where the pixel electrode to be described later will be formed. Is formed.

In the present embodiment, the first photoresist pattern portion 16a has a first height T1 as measured from the surface of the second conductive layer 14a. On the other hand, the second photoresist pattern portion 16b has a second height T2 when measured from the surface of the second conductive layer 14a. In the present embodiment, the first height T1 has a thicker thickness than the second height T2.

Referring to FIG. 7, by using the first photoresist pattern 16a as an etching mask, the first conductive layer 12a and the second conductive layer 14a are sequentially etched to form the substrate 1 on FIG. 9. As described above, the gate wiring structure 20 including the gate electrode 10 and the gate wiring 15 is formed. In the present embodiment, the gate wiring 15 and the gate electrode 10 are formed on the first conductive pattern 12 and the second conductive pattern 12 formed by patterning the first conductive layer 12a. Pattern 14. In addition, during the formation of the gate wiring structure 20 on the substrate 1, the first conductive layer 12a and the second conductive layer 14a are sequentially formed using the second photoresist pattern 16b as an etching mask. After etching, the preliminary pixel electrode 32 is formed on the substrate 1. That is, in the present embodiment, the gate wiring structure 20 and the preliminary pixel electrode 32 are formed on the substrate 1 as shown in FIG. 7 by one mask and one etching process.

Meanwhile, after the gate wiring structure 20 and the preliminary pixel electrode 32 are formed as shown in FIG. 7, the third photoresist pattern portion 16c is formed on the gate wiring structure 20, and the preliminary pixel electrode ( On the 32, the remaining second conductive layer 14a is formed.

Referring to FIGS. 7 and 8, the remaining second conductive layer 14a is etched using the third photoresist pattern portion 16c as an etch mask to form a pixel electrode 30 on the substrate 1. Then, when the third photoresist pattern portion 16c remains on the gate wiring structure 20, the third photoresist pattern portion 16c may be removed from the gate wiring structure 20 by an ashing process and / or a strip process. Removed.

Referring to FIG. 9, when the remaining second conductive layer 14a covering the preliminary pixel electrode 32 is removed to form the pixel electrode 30, the gate wiring 15 of the gate wiring structure 20 is removed. A part of the second conductive pattern 14 covering the pad portion 16 disposed at the end is also removed, so that the first conductive pattern 12 formed under the second conductive pattern 14 is removed at the pad portion 16. Exposed.

Referring to FIG. 10, after the gate wiring structure 20 and the pixel electrode 30 are formed on the substrate 1, the gate insulating layer covering the gate wiring structure 20 and the pixel electrode 30 is formed on the substrate 1. 40a, the semiconductor layer 50a and the etch stopper layer 90a are sequentially formed.

After the gate insulating film 40a, the semiconductor layer 50a, and the etch stopper layer 90a are sequentially formed, a photoresist film (not shown) is formed over the etch stopper layer 90a over the entire area.

Subsequently, the photoresist film is patterned by a photo process including an exposure process and a developing process to form a fourth photoresist pattern 62 on the etch stopper layer 90a. The fourth photoresist pattern 62 has an opening 64 corresponding to a portion of the pixel electrode 32.

Using the fourth photoresist pattern 62 having the opening 64 as an etching mask, the etch stopper layer 90a, the semiconductor layer 50a, and the gate insulating layer 40a are patterned to expose the pixel electrode 30. The semiconductor pattern 50, the gate insulating layer pattern 40a, and the preliminary etch stopper layer 90b corresponding to the contact hole and the gate electrode 10 are formed.

Referring to FIG. 11, after the photoresist film is formed on the substrate 1, the photoresist film is patterned by a photo process including an exposure process and a developing process to form a fifth photoresist pattern on the preliminary etch stopper layer 90b. 72 is formed. The fifth photoresist pattern 72 has a first height as measured from the preliminary etch stopper layer 90b in the portion where the etch stopper pattern will be described later, and the preliminary etch stopper layer 90b in the portion where the semiconductor pattern is to be formed. Has a second height lower than the first height as measured from.

Referring to FIG. 12, the preliminary etch stopper pattern 90b disposed on the semiconductor layer 50a is patterned using the fifth photoresist pattern 72 illustrated in FIG. 11 as an etch mask, thereby forming the semiconductor pattern 50. And an etch stopper pattern 90 on the semiconductor pattern 50.

At this time, when patterning the preliminary etch stopper pattern 90b disposed on the semiconductor pattern 50, the semiconductor layer 50a and the etch stopper layer 90a left on the pixel electrode 30 are also removed.

Referring to FIG. 13, after the etch stopper pattern 90 is formed, a metal film 60a is formed over the entire surface of the substrate 1 to cover the etch stopper pattern 90. In this embodiment, examples of the material that can be used as the metal film 60a include aluminum, aluminum alloy, and the like.

After the metal film 60a is formed, a photoresist film is formed on the upper surface of the metal film 60a.

After the photoresist film is formed on the metal film 60a, the photoresist film is patterned to form a sixth photoresist pattern 92.

Referring to FIG. 14, the metal film 60a is etched using the sixth photoresist pattern 92 as an etch mask, and a data wiring structure and a drain including a source electrode 65 and a data line on the substrate 1. The electrode 80 is formed. In this embodiment, the source electrode 65 is disposed substantially perpendicular to the gate wiring, and the drain electrode 80 is electrically connected to the pixel electrode 30 through the contact hole 42. In this case, the etch stopper pattern 90 is disposed between the source electrode 65 and the drain electrode 80 to prevent the semiconductor pattern 50 from being exposed to the outside.

As described above in detail, when the display substrate is manufactured by the four-sheet process, the semiconductor pattern exposed between the source electrode and the drain electrode is covered with an etch stopper pattern, thereby preventing the performance of the thin film transistor of the display substrate. It has the effect of shortening the manufacturing process of the display substrate.

Although the detailed description of the present invention has been described with reference to the embodiments of the present invention, those skilled in the art or those skilled in the art will have the spirit and scope of the present invention as set forth in the claims below. It will be appreciated that various modifications and variations can be made in the present invention without departing from the scope of the art.

Claims (13)

A gate electrode disposed in the display area of the substrate, the gate electrode including a first gate pattern and a second gate pattern disposed on the first gate pattern, and a gate wiring extending from the gate electrode to a pad area disposed around the display area; A gate wiring structure having a; A pixel electrode formed on the substrate in the same layer as the first gate pattern; A gate insulating pattern covering the gate wiring structure and the pixel electrode and having a contact hole exposing a portion of the pixel electrode; A semiconductor pattern covering the gate electrode; A data wiring structure including a source electrode electrically connected to the semiconductor pattern, and a data line extending from the source electrode to the pad region; A drain electrode electrically connected to the semiconductor pattern and electrically connected to the exposed pixel electrode and spaced apart from the source electrode; And And an etch stopper pattern disposed on an exposed portion of the semiconductor pattern exposed by the source electrode and the drain electrode. The display substrate of claim 1, wherein the first gate pattern is selected from the group consisting of tin indium oxide, zinc indium oxide, and amorphous tin indium oxide. The display substrate of claim 1, wherein the second gate pattern comprises a metal. The display substrate of claim 1, wherein the etch stopper pattern is any one of an oxide film pattern including an oxide and a nitride film pattern including a nitride. The display substrate of claim 1, wherein the pad part formed at an end of the gate line is exposed to the first gate pattern. The display substrate of claim 1, wherein a pad part protection member including a same material as that of the etch stopper pattern is formed along an edge of the pad part formed at an end of the gate line. Forming a gate electrode having a first gate pattern and a second gate pattern disposed on the first gate pattern and a gate wiring structure having gate wirings, and a pixel electrode formed on the same layer as the first gate pattern on a substrate; ; Sequentially forming a gate insulating layer, a semiconductor layer, and an etch stopper layer covering the gate line and the pixel electrode; Patterning the etch stopper layer, the semiconductor layer, and the gate insulating layer to form a contact hole exposing the pixel electrode; Patterning the etch stopper layer and the semiconductor layer together to form a semiconductor pattern and an etch stopper pattern, respectively; Forming a source / drain metal layer electrically connected to the pixel electrode through the contact hole and covering the semiconductor pattern; And Patterning the source / drain metal layer to form a data line having a source electrode connected on the semiconductor pattern and a drain electrode connected to the pixel electrode through the contact hole. The method of claim 7, wherein the patterning of the etch stopper layer and the semiconductor layer comprises: Forming a first photoresist thin film on the etch stopper layer; Patterning the first photoresist thin film to form a first photoresist pattern having an opening corresponding to a portion of the pixel electrode; Forming the contact hole by patterning the etch stopper layer, the semiconductor layer, and the gate insulating layer using the first photoresist pattern as an etching mask; Forming a second photoresist pattern on the etch stopper layer corresponding to the gate electrode, the second photoresist pattern having a second thickness lower than the first thickness at a position where the semiconductor pattern is to be formed; And And etching the etch stopper layer and the semiconductor layer simultaneously using the second photoresist pattern as an etch mask to form an etch stopper pattern and a semiconductor pattern. The method of claim 7, wherein the first gate pattern is selected from the group consisting of indium tin oxide, zinc indium oxide, and amorphous tin indium oxide. The method of claim 7, wherein the second gate pattern comprises a metal. The method of claim 7, wherein the etch stopper pattern is any one of an oxide film pattern including an oxide and a nitride film pattern including a nitride. The method of claim 7, wherein the pad part formed at an end of the gate line is exposed to the first gate pattern. The method of claim 7, wherein a pad part sign member including the same material as the etch stopper pattern is formed along an edge of the pad part formed at an end of the gate line.

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