KR101450884B1 - Flat panel display device and method fabricating the same - Google Patents

Abstract

The present invention relates to a flat panel display, and a top gate type organic thin film transistor is provided and a gate wiring line electrically connecting the gate wiring and the gate pad electrode to each other is formed to be covered by a protective film, A flat panel display device capable of minimizing damage and reducing the cost of a process is provided.

Organic thin film transistor, top gate, link wiring, peeling, flat panel display

Description

TECHNICAL FIELD [0001] The present invention relates to a flat panel display device and a method of manufacturing the same,

The present invention relates to a flat panel display, and more particularly, to a flat panel display including a top gate type organic thin film transistor and a method of manufacturing the same.

The flat panel display device is a device that provides information to the user through the image and is becoming a necessity for today's modern people.

Examples of the flat panel display device include a liquid crystal display device and an organic electroluminescent display device. A flat panel display device has a plurality of pixels for displaying an image. At this time, each pixel includes a switching element for controlling each pixel or a driving element for driving each pixel, thereby improving image quality characteristics and driving characteristics. As the switching element or the driving element, a thin film transistor is generally used.

The thin film transistor includes a gate electrode, a gate insulating layer, a semiconductor layer, and a source / drain electrode. In order to form each element of the thin film transistor, a patterning process accompanied by an exposure and development process is formed.

Currently, flat panel displays are important not only in terms of product quality but also in price competitiveness, and many processes must be added to manufacture thin film transistors. As a result, the production cost of the flat panel display device increases.

Particularly, when the semiconductor layer of the thin film transistor is formed of amorphous silicon, the semiconductor layer is formed by performing a film forming process through a sputtering method or a chemical vapor deposition method, an etching process accompanied with a photolithography process, etc., And there is a limit in manufacturing a large-area flat panel display device.

In addition, when the semiconductor layer is formed of amorphous silicon, the process environment requires a high temperature of 200 DEG C or more, so that the selection range for the material of the substrate on which the semiconductor layer is formed becomes narrow.

Therefore, the conventional flat panel display device has a thin film transistor for quality improvement, but the manufacturing cost of the thin film transistor increases due to the manufacturing process of the thin film transistor.

One aspect of the present invention is to provide a flat panel display device having an organic thin film transistor and capable of reducing the manufacturing cost, and a method of manufacturing the same.

According to an aspect of the present invention, there is provided a flat panel display. Wherein the flat panel display device includes a substrate including a display region for displaying an image and a pad region disposed in the periphery of the display region with a boundary region therebetween, a substrate disposed on the substrate in the display region, An organic semiconductor pattern which exposes a portion of the drain electrode and which is disposed on the substrate in the upper portion of the source electrode and the drain electrode and in the spacing space; A gate electrode disposed on the gate insulating pattern; a pixel electrode disposed on the substrate of the display region and electrically in contact with the drain electrode; A gate pad electrode electrically connected to an end of the gate link wiring, , Disposed on the protective film, and the protective film of the display region disposed on the substrate including the gate link interconnection, the gate pad electrode, a gate wiring electrically connected to the gate electrode and the gate link interconnection.

According to another aspect of the present invention, there is provided a method of manufacturing a flat panel display. The manufacturing method includes the steps of providing a substrate having a display region and a pad region with a boundary region sandwiched therebetween, a data line disposed on the substrate of the display region, a source and drain electrode, and a gate Forming a gate electrode pad electrically connected to the gate electrode line and a pixel electrode electrically connected to the drain electrode in each of the display region and the pad region; Forming an organic semiconductor pattern, a gate insulating pattern, and a gate electrode on the source electrode, the drain electrode, and the spacing space; A protective film is formed on a substrate including a pixel electrode, a gate electrode, and a gate pad electrode And forming a gate wiring crossing the data wiring on the protection film and electrically connected to the gate electrode and the gate link wiring.

The flat panel display device of the present invention can reduce the manufacturing cost by forming the semiconductor pattern of the thin film transistor into an organic material that can be manufactured by a wet process that is easier than the vapor deposition process.

In addition, in the flat panel display device of the present invention, since the gate line wiring is formed so as to cover the protective film in the top gate type thin film transistor, process defects such as peeling can be prevented and the number of processes can be further reduced.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings of the flat panel display. The following embodiments are provided by way of example so that those skilled in the art can fully understand the spirit of the present invention. Therefore, the present invention is not limited to the embodiments described below, but may be embodied in other forms. In the drawings, the size and thickness of an apparatus may be exaggerated for convenience. Like reference numerals designate like elements throughout the specification.

1 and 3 are views illustrating a flat panel display according to an embodiment of the present invention. 1 is a plan view showing a part of a flat panel display according to an embodiment of the present invention. FIG. 2 is an enlarged plan view of one pixel of the flat panel display shown in FIG. 1. FIG. 3 is a cross-sectional view taken along the line I-I 'shown in FIG.

1 and 3, the flat panel display of the present invention is divided into a display area D and a pad area P disposed around the display area D with a boundary area DP interposed therebetween .

The display area D is divided into a plurality of pixels for displaying an image. The pixel may be defined by a gate wiring 101 and a data wiring 104 which intersect each other on a substrate 100.

A thin film transistor (Tr) and a pixel electrode (120) electrically connected to the thin film transistor (Tr) may be disposed in each pixel. The thin film transistor Tr may be an organic thin film transistor which is easy to manufacture.

Specifically, the thin film transistor Tr may include source and drain electrodes 111 and 112, an organic semiconductor pattern 113, a gate insulating pattern 114, and a gate electrode 115.

The source electrode 111 may have a shape partially protruding from the data line 104. That is, the source electrode 111 is integrated with the data line 104, and the source electrode 111 and the data line 104 are electrically connected to each other.

The drain electrode 112 faces the source electrode 111 and is spaced apart from the source electrode 111 and is disposed on the substrate 100.

The organic semiconductor pattern 113 is disposed on the substrate 100 in the upper part of the source electrode 111 and the drain electrode 112 and in the spacing space. The organic semiconductor pattern 113 exposes a portion of the drain electrode 112 for electrical connection with a pixel electrode 120 to be described later. For example, both ends of the source electrode 111 and the drain electrode 112 are exposed. The organic semiconductor pattern 113 is formed of an organic semiconductor material. For example, the organic semiconductor materials include pentacine and polythiophene.

The gate insulating pattern 114 is disposed on the organic semiconductor pattern 113. The gate insulating pattern 114 may have the same shape as the organic semiconductor pattern 113. The gate insulating pattern 114 may be formed of an organic insulating material. For example, the gate insulating pattern 114 may be formed of acrylic resin, polyvinyl alcohol, or the like.

The gate electrode 115 is disposed on the organic semiconductor pattern 113. The gate electrode 115 may have the same shape as the organic semiconductor pattern 113. The gate electrode 115 may be formed of any one of molybdenum, chromium, and alloys thereof.

Thus, the top gate type organic thin film transistor Tr is arranged in each pixel. By designing the gate electrode 115 and the organic semiconductor pattern 113 in the same shape, the organic semiconductor pattern and the gate electrode 115 can be formed using a single mask, Can be saved.

In addition, a photoresist pattern 125 having the same shape as the gate electrode 115 and having a gate contact hole exposing the gate electrode 115 may be further disposed. The photoresist pattern 125 may be an etch mask used in the process of forming the gate electrode 115, the organic semiconductor pattern 113, and the gate insulating pattern 114.

The pixel electrode 120 is in electrical contact with the drain electrode 112 exposed from the organic semiconductor pattern 113. The pixel electrode 120 may be in direct contact with the drain electrode 112. The pixel electrode 120 is divided into pixels. The pixel electrode 120 may be formed of a transparent conductive material. For example, the pixel electrode 120 may be formed of ITO or IZO.

A protective layer 130 is disposed on the substrate including the pixel electrode 120 and the thin film transistor Tr. The passivation layer 130 has a gate contact hole exposing the gate electrode 115 and an opening exposing the pixel electrode 120.

A gate wiring 101 electrically connected to the gate electrode 115 is disposed on the protection film 130 through the gate contact hole. The gate wiring 101 may be formed to be in direct contact with the gate electrode 115 through the gate contact hole. The gate line 101 intersects the data line 104 to define a pixel. The gate wiring 101 may be formed of any one of Al, AlNd, Cu, and alloys thereof.

Pad electrodes are provided on the substrate 100 of the pad region P to receive an electrical signal from the external driving circuit and provide an electrical signal to each pixel of the display region D. The pad electrodes are provided with a gate pad electrode 103 electrically connected to the gate line 101 and data pad electrodes 105 and 107 electrically connected to the data line 104. The pad electrode is connected to the external driving circuit portion by a TAB (108, 109) using a TCP having a built-in driving IC. Here, the gate pad electrode 103 and the data pad electrodes 105 and 107 may include a conductive material having high corrosion resistance in order to prevent the gate pad electrode 103 and the data pad electrodes 105 and 107 from being exposed to the outside and being corroded. For example, the gate pad electrode 103 may be formed of the same conductive material as the pixel electrode 120. The data pad electrodes 105 and 107 are formed on the first data pad electrode 105 made of the same conductive material as the data line 104 and on the first data pad electrode 105, And a second data pad electrode 107 formed of the same conductive material as the first data pad electrode 107.

A gate link wiring 102 for electrically connecting the gate wiring 101 and the gate pad electrode 103 to each other may be disposed on the substrate 100 in the boundary region DP. A data link line 106 electrically connecting the data line 104 and the data pad electrode may be disposed in the boundary region DP.

The gate link wiring 102 electrically connected to the gate wiring 101 may be formed integrally with each other to reduce the number of process steps. At this time, since the gate wiring 101 is disposed on the protection film 130, the gate wiring wiring 102 can also be disposed on the protection film 130. However, when the gate link wiring line 102 is exposed to the outside, the gate line wiring line 102 can be easily peeled from the protective film 130 during a manufacturing process, for example, an etching process or an alignment film forming process. This is because, when the protective layer 130 is formed of an organic material, the adhesion between the protective layer 130 and the gate link layer 102 is weak. Particularly, since the gate link wiring 102 is densely arranged with a smaller line width than the gate wiring 101, the poor filling of the gate link wiring 102 occurs more seriously than the gate wiring 101 .

Fig. 4 is a photograph after the step of forming the gate link wiring, and Fig. 5 is a photograph after the step of forming the alignment film.

4 and 5, in the case where the gate link wiring 102 is disposed on the protective film 130, in the etching process for forming the gate link wiring 102 or in the process for forming the alignment film, It was confirmed that a defect that the wiring 102 was peeled occurred.

3, the gate line wiring line 102 is formed between the substrate 100 and the passivation layer 130. As shown in FIG. That is, the gate wiring line 102 is formed to cover the protective film 130. Thus, even if a subsequent process such as the etching process or the orientation film forming process is performed, the gate line wiring line 102 is protected by the protective film 130 to prevent process defects such as peeling. The gate line wiring 102 may be disposed on the same layer as the source and drain electrodes 111 and 112, that is, on the substrate 100. The gate wiring line 102 may be formed of the same conductive material as the source and drain electrodes 111 and 112. This prevents the poor filling of the gate link wiring 102 and does not require additional process steps.

Although not shown in the drawings, when the flat panel display device is a liquid crystal display device, an upper substrate facing the substrate may be further disposed, and a liquid crystal layer may be further disposed between the substrate and the upper substrate. Alternatively, when the flat panel display device is an organic light emitting diode display device, an organic light emitting layer for forming light on the pixel electrode and a common electrode disposed on the organic light emitting layer may be further disposed.

6 to 10 are cross-sectional views illustrating a method of manufacturing a flat panel display device according to a second embodiment of the present invention.

Referring to FIG. 6, a substrate 100 having a display region D and a pad region P disposed across a boundary region DP is provided to manufacture a flat panel display. In the display area D, a plurality of pixels for displaying an image are defined. In addition, the pad region P is disposed around the display region D.

The substrate 100 may be any one of a plastic substrate, a glass substrate, a metal foil, and a film.

A data line 104, source and drain electrodes 111 and 112, and a gate link line 102 are formed on the substrate 100. In order to form the data line 104, the source and drain electrodes 111 and 112, a first conductive film is first formed on the substrate. For example, the first conductive layer may be formed by depositing a metal material. A first photoresist pattern having a predetermined pattern is formed on the first conductive film through an exposure process and a development process using a mask. The data line 104, the source and drain electrodes 111 and 112 can be formed through an etching process of the first conductive film using the first photoresist pattern as an etching mask.

The data line 104 and the source and drain electrodes 111 and 112 are formed on the display region D of the substrate 100. [ The source electrode 111 may be formed so as to be branched from the data line 104, that is, the source electrode 111 and the data line 104 may be integrally formed. The source and drain electrodes 111 and 112 have a predetermined spacing space and face each other. Further, the gate link wiring 102 is formed on the boundary region DP.

In addition, although not shown in the drawing, a data link wiring and a first data pad electrode may be further formed on the boundary region DP and the pad region P, respectively.

Referring to FIG. 7, the pixel electrode 120 and the gate pad electrode 103 are formed on the display region D and the pad region P, respectively.

The substrate 100 including the data line 104, the source and drain electrodes 111 and 112 and the gate line 102 is first formed to form the pixel electrode 120 and the gate pad electrode 103. [ The second conductive film is formed. The second conductive layer may be formed by depositing a transparent conductive material such as ITO or IZO. Thereafter, a second photoresist pattern having a predetermined pattern is formed on the second conductive film through an exposure process and a development process using a mask. The pixel electrode 120 and the gate pad electrode 103 may be formed through an etching process of the second conductive film using the second photoresist pattern as an etching mask. The pixel electrode 120 is partially overlapped with the edge of the drain electrode 112 and the pixel electrode 120 and the drain electrode 112 may be electrically connected to each other. The pixel electrode 120 may be in direct contact with the drain electrode 112. In addition, the pixel electrode 120 may be separated for each pixel. The gate pad electrode 103 is formed to overlap with a part of the gate link wiring 102 so that the gate pad electrode 103 and the gate link wiring 102 can be electrically connected to each other. The gate pad electrode 103 may be formed to be in direct contact with the gate link wiring 102. The gate pad electrode 103 may be exposed to the outside, and the reliability of the flat panel display device may be lowered due to corrosion. However, since the second conductive film has greater corrosion resistance than other metals, the reliability of the gate pad electrode 103 can be prevented from lowering due to corrosion.

In addition, although not shown in the drawing, a second data pad electrode covering the first data pad electrode may be further formed in the process of forming the gate pad electrode 103.

Referring to FIG. 8, at least a portion of the drain electrode 112, for example, both ends of the source and drain electrodes 111 and 112 are exposed, and the source and drain electrodes 111 and 112, An organic semiconductor pattern 113, a gate insulating pattern 114 and a gate electrode 115 are formed on the spacing space between the electrodes 111 and 112. [

In order to form the organic semiconductor pattern 113, the gate insulating pattern 114 and the gate electrode 115, an organic semiconductor layer, a gate electrode layer, and a gate electrode layer are sequentially formed on the substrate 100 including the pixel electrode and the gate pad electrode 103, An insulating layer and a conductive layer are sequentially formed.

The organic semiconductor layer applies an organic semiconductor material such as a petasine or a polythiophene on the substrate 100 including the pixel electrode 120 and the gate pad electrode 103. Examples of the method for forming the organic semiconductor layer include an inkjet printing method, a slit coating method, a spray coating method, a bar coating method, a spin coating method, and a doctor blade method.

The gate insulating layer may be formed by applying an insulating material such as acrylic resin or polyvinyl alcohol on the organic semiconductor layer. However, the material of the gate insulating layer is not limited in the embodiment of the present invention, and the gate insulating layer may be formed of silicon oxide, silicon nitride, or the like.

The conductive layer may be formed of a conductive material capable of dry etching. For example, the conductive layer may be formed by depositing Mo, Cr, an alloy thereof, or the like.

A third photoresist pattern 125 having a predetermined pattern is formed on the conductive layer through an exposure process and a development process using a mask. The gate insulating layer 114 and the organic semiconductor pattern are patterned by sequentially etching the conductive layer, the gate insulating layer, and the organic semiconductor layer using the third photoresist pattern 125 as an etching mask, (113) can be formed.

Accordingly, the organic semiconductor pattern 113, the gate insulating pattern 114, and the gate electrode 115 are formed using the same mask, so that the organic semiconductor pattern 113, the gate insulating pattern 114, Lt; RTI ID = 0.0 > 115 < / RTI >

Thus, by forming the thin film transistor Tr as an organic thin film transistor, it can be formed through a wet process that is easier than a deposition process. In addition, by forming the thin film transistor Tr as a top gate, the organic semiconductor pattern 113 and the gate electrode 115 can be formed using the same mask, and the number of processes can be reduced.

Referring to FIG. 9, after completing the thin film transistor Tr, the third photoresist pattern 125 may be removed through ashing or stripping solution. However, in the embodiment of the present invention, the third photoresist pattern 125 is left to prevent the thin film transistor Tr from being damaged due to the removal process of the third photoresist pattern 125.

A protective layer 130 is formed on the substrate 100 including the third photoresist pattern 125. The protective layer 130 may be formed of a photosensitive resin. For example, the protective layer 130 may be formed of an acrylic resin, polyvinyl alcohol, polyimide resin, or the like. As the protective layer 130 is formed of a photosensitive resin, a gate contact hole exposing the gate electrode 115, a gate link contact hole exposing the gate link wiring 102, a gate line contact hole exposing the pixel electrode 130, It is not necessary to form a separate photoresist pattern to form an opening and a gate pad contact hole exposing the gate pad electrode 103. That is, the gate contact hole, the gate link contact hole, the opening, and the gate pad contact hole of the passivation layer 130 may be formed through the exposure and development process using the mask. However, the material of the protective layer 130 is not limited to the material of the protective layer 130, and the protective layer 130 may be formed of benzocyclobutene, silicon oxide, silicon nitride, or the like.

The gate contact hole is formed to penetrate the third photoresist pattern 125 to expose the gate electrode 115.

Here, although not shown in the figure, the passivation layer 130 may further include a data pad contact hole exposing the second data pad electrode.

Referring to FIG. 10, the gate electrode 115 and the gate link wiring 102 are electrically connected to the protective film 130 of the display area D through the gate contact hole and the gate link contact hole A gate wiring 101 is formed. That is, the gate wiring 101 may be formed to be in direct contact with the gate electrode 115 and the gate link wiring 102 through the gate contact hole and the gate link contact hole.

In order to form the gate wiring 101, a third conductive film is formed on the protective film 130. The third conductive layer may be formed by depositing any one of conductive materials having low resistance, such as Al, AlNd, Cu, and alloys thereof. Then, a fourth photoresist pattern having a predetermined pattern is formed on the third conductive film through an exposure process and a development process using a mask. The gate wiring 10 may be formed through the etching process of the third conductive film using the fourth photoresist pattern as an etching mask.

The gate line 101 intersects the data line 104, and a pixel can be defined in the display area D.

Hereinafter, although not shown, when the flat panel display device is a liquid crystal display device, a method of forming an alignment film on a substrate including the pixel electrode 120, attaching a color filter substrate on the substrate, And forming a liquid crystal layer between the substrate and the color filter substrate. Alternatively, when the flat panel display device is an organic light emitting diode display device, an organic light emitting layer and a common electrode may be formed on the pixel electrode 120, and a sealing process may be performed using an encapsulation substrate.

Therefore, in the embodiment of the present invention, the gate link wiring 102, which is smaller in line width than the gate wiring 101 and densely arranged, is covered by the protection film 130, It is possible to prevent occurrence of defective peeling.

In addition, since the thin film transistor Tr is formed of the top gate type organic thin film transistor, the process water and the process cost can be reduced.

1 is a plan view showing a part of a flat panel display according to an embodiment of the present invention.

FIG. 2 is an enlarged plan view of one pixel of the flat panel display shown in FIG. 1. FIG.

3 is a cross-sectional view taken along the line I-I 'shown in FIG.

4 is a photograph after the step of forming the gate link wiring.

5 is a photograph after the step of forming an alignment film.

6 to 10 are cross-sectional views illustrating a method of manufacturing a flat panel display device according to a second embodiment of the present invention.

 (Description of Reference Numbers to Main Parts of the Drawings)

100: substrate 101: gate wiring

102: Gate link wiring 103: Gate pad electrode

104: data line 120: pixel electrode

130: protective film Tr: thin film transistor

Claims (11)

A substrate including a display region for displaying an image and a pad region disposed in the periphery of the display region with a boundary region therebetween; Source and drain electrodes disposed on the substrate of the display region with a predetermined spacing therebetween; A gate link wiring disposed on the substrate in the boundary region and formed in the same layer as the source and drain electrodes; A pixel electrode disposed on the substrate of the display region and electrically in contact with the drain electrode; A gate pad electrode disposed on the substrate of the pad region and electrically connected to an end of the gate link wiring; An organic semiconductor pattern exposing at least a portion of the drain electrode, an organic semiconductor pattern disposed on the source electrode, the upper portion of the drain electrode, and the substrate in the spacing space; A gate insulating pattern disposed on the organic semiconductor pattern; A gate electrode disposed on the gate insulating pattern; A photoresist pattern disposed on the gate electrode and having the same shape as the gate electrode and having a gate contact hole exposing a part of the gate electrode; A protective film formed on the substrate including the pixel electrode, the gate electrode, the gate link wiring, the gate pad electrode, and the photoresist pattern, the contact hole exposing the gate electrode and the gate link wiring; And And a gate wiring disposed on the protective film of the display region and electrically connected to the gate electrode and the gate link wiring through the contact hole. The method according to claim 1, Wherein the gate line wiring includes the same conductive material as the source and drain electrodes. The method according to claim 1, Wherein the gate pad electrode includes the same conductive material as the pixel electrode. delete The method according to claim 1, Wherein the gate electrode, the organic semiconductor pattern, and the gate insulating pattern have the same shape. Providing a substrate having a display region and a pad region across a border region; A data line disposed on the substrate of the display region, source and drain electrodes disposed with a predetermined spacing from each other, and gate line wiring disposed on the substrate of the boundary region; Forming a pixel electrode electrically connected to the drain electrode and a gate pad electrode electrically connected to the gate link line in each of the display region and the pad region; Sequentially forming an organic semiconductor layer, a gate insulating layer, and a conductive layer on a substrate including the source electrode and the drain electrode; Forming a photoresist pattern having a predetermined pattern on the conductive layer; Etching the organic semiconductor layer, the gate insulating layer, and the conductive layer using the photoresist pattern as an etch mask to expose at least a portion of the drain electrode, and forming an upper portion of the source electrode and the drain electrode, Forming an organic semiconductor pattern, a gate insulating pattern, and a gate electrode on the substrate; Forming a protective film on the substrate including the data wiring, the source and drain electrodes, the gate link wiring, the pixel electrode, the gate electrode, the gate pad electrode and the photoresist pattern; Forming a contact hole in the protective film exposing the gate electrode and the gate link wiring; And And forming a gate interconnection crossing the data line on the protective film and electrically connected to the gate electrode and the gate link interconnection through the contact hole. delete delete delete The method according to claim 1, Wherein the gate wiring is formed to directly contact the gate electrode and the gate link wiring through the contact hole. The method according to claim 6, Wherein the gate wiring is formed to directly contact the gate electrode and the gate link wiring through the contact hole.

Images