JP2003240829A - Test vector generating device for power consumption calculation and test vector generating method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To lighten a burden on a test vector designer, to make it possible to input a test vector into a simulator without erroneous input, and also to shorten test vector generating time, by generating the test vector automatically in a short period of time. <P>SOLUTION: This test vector generating device 1 generates a test vector or an electrical signal pattern used for calculating electric power consumption of an apparatus from electrical signal patterns inputted into the apparatus, and is equipped with a temporary test vector generating part 2 for inputting thereinto electric signal patterns to be inputted into the apparatus, a power consumption presence determining part 4 for determining an electrical signal pattern causing power consumption from among the signal patterns inputted into the generating part 2, a regular test vector generating part 5 for simplifying the signal pattern determined by the determining part 4, and a power consumption absolute value calculating part 7 for calculating regular power consumption of the apparatus in the signal pattern determined by the determining part 4. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test vector generation device and a test vector generation method for generating a test vector which is an input condition to be input to a simulator for calculating a heat generation amount of a semiconductor integrated circuit or the like, that is, power consumption. Is.

[0002]

2. Description of the Related Art In recent years, for example, in the manufacture of semiconductor integrated circuits, heat generation, that is, increase in power consumption has become non-negligible with improvement in integration degree and operating frequency. Therefore, it is essential to estimate the power consumption at the design stage.

In designing an ASIC which is a semi-customized semiconductor integrated circuit, a desired system is constructed by combining elements called "cells" or functional blocks. The "cell" is typically provided by a semiconductor vendor.

By giving this "cell" information such as power consumption corresponding to each operation, the power consumption of the entire semiconductor integrated circuit can be estimated. Generally, in order to obtain the power consumption, a method of measuring a through current from a power source to a ground by using a dedicated analog simulator for simulating an electric circuit operation is adopted.

To calculate power consumption using this analog simulator, it is necessary to input an input waveform called a test vector. This test vector is created and input by manual work by the operator.

As described above, a simple example of the conventional test vector creating method will be described by taking the case of the logic circuit cell 10 shown in FIG. 3 as an example.

FIG. 3 shows a logic circuit cell 10 including an inverting element A and a NAND element B. This logic circuit cell 10
Then, the input signal I1 is input to the inverting element A. The input signal I1 is inverted by the inverting element A, and the output signal M1 which is its inverted output is input to the NAND element B. NA
The ND element B receives the input signal I2 and the input signal I3 in addition to the output signal M1 from the inverting element A, and outputs the output signal O1.

When the input signals I1 to I3 are input to the logic circuit cell 10 having such an operation in the timing chart as shown in FIG. 4A, the timing as shown in FIG. Then, the signals M1 and O1 are output.

Conventionally, using an analog simulator,
To obtain the power consumption of the logic circuit cell 10, FIG.
The timing chart shown in the input signals I1 to I3 of (a) is input as a test vector, or the test vector shown in FIG. .

In FIG. 4A, only one of the input signals I1 to I3 is changed from 0 to 1 and 1 to 0, and the other input signals are fixed to 0 or 1 as one. Units (portions delimited by vertical thin lines in FIG. 4) and all combinations of them are arranged as a test vector in this circuit. For example, in FIG. 4A, the input signals I2 and I3 are fixed to 0 and the input signal I1 is changed to 0-1-0 at the first division. In the next division, the input signal I3 is set to 1 and the input signal I1 is similarly converted. This is input signal I2, I3 all 0, 1
Perform for fixed combinations. Next, from the fifth, the input signal I2 is changed to 0-1-0 with a fixed combination of 0 and 1 for the input signal I1 and the input signal I3. Similarly, the input signals I1 and I3 are fixed to 0 and 1.

Hereinafter, this combination of inputs will be referred to as an input pattern. In an actual analog simulator,
In many cases, the inputs are assigned to voltage values instead of logical values 0 and 1. For example, 0 becomes 0 volt and 1 becomes 5 volt. The value depends on the manufacturing process of the target cell library. In addition, the input patterns are independent in one combination, need not be continuous as shown in the figure, and the order is arbitrary.

In this logic circuit cell 10, power consumption occurs when the outputs of the inverting element A and the NAND element B change. That is, the power consumption W _a of the inverting element A, the NAND
The power consumption of the element B is generated at the timing shown in FIG. Figure 4 shows the combination of these.
It is Wa _{+ b} shown in (c). As shown in FIG. 4C, the inverting element A always consumes power due to a change in input, whereas the NAND element B does not necessarily consume power. The same applies to the NOR element.

In the case of a combination that has no power consumption, it can be omitted. Therefore, in an actual simulation,
The test vector of FIG. 4 (e), which omits that part and is shortened, is often used. This is because analog simulation generally requires a lot of time, that is, cost. The test vector without omission is called a tentative test vector and a regular test vector.

[0014]

However, such a conventional method has the following problems.

Generally, in a test vector for the purpose of delay calculation or fault detection, the result is always detected at the external output terminal, but if there is a change in the output of each element inside the power consumption circuit, it will occur. To do. The external terminal may not change due to the change of the input terminal, but power may be consumed inside the cell.

Therefore, the test vector V must be created in consideration of the characteristics of the target circuit. The logic circuit cell 10 for which the power consumption W is calculated is not limited to the simple one as shown in FIG. 3, and it is necessary to perform the complicated circuit. Therefore, the test vector designer who creates the test vector V is , It is necessary to fully understand the circuit operation.
That is, in order to reduce the simulation time described above, it is necessary to collect only the combinations that consume power and use them as test vectors. This causes a problem that the test vector designer has a heavy work load and takes a long time. In addition, the created test vector must be input to the simulator, but this is also a manual operation, which may cause erroneous input, omission of input, and excessive input.

The present invention has been made in view of the above circumstances. By automatically generating a test vector in a short time, the load on the designer of the test vector can be reduced, and erroneous input can be prevented. An object of the present invention is to provide a test vector generation device and a test vector generation method for power consumption calculation that can input a test vector to a simulator and shorten the test vector generation time.

[0018]

In order to achieve the above object, the present invention takes the following means.

That is, the test vector generation device for calculating power consumption according to the invention of claim 1 generates a test vector which is an electric signal pattern for calculating the power consumption of the device from the electric signal pattern input to the device. And a temporary test vector generating means for inputting an electric signal pattern to be input to the device, and an electric signal pattern for generating power consumption out of the electric signal patterns input to the temporary test vector generating means. Power consumption presence / absence determining means for determining, normal test vector generating means for simplifying the electric signal pattern determined by the power consumption determining means, and normal power consumption of the device in the electric signal pattern determined by the power consumption determining means And a power consumption absolute value calculating means.

According to a second aspect of the invention, in the test vector generation device for calculating power consumption of the first aspect of the invention, the device is a logic circuit.

According to a third aspect of the present invention, there is provided a test vector generating method for calculating power consumption, which is a test for generating a test vector which is an electric signal pattern for calculating power consumption of a device from an electric signal pattern input to the device. A vector generation method, which determines a temporary test vector generation step of inputting an electrical signal pattern to be input to a device, and an electrical signal pattern that causes power consumption among the electrical signal patterns input in the temporary test vector generation step. Power consumption presence / absence determination step, regular test vector generation step for simplifying the electric signal pattern determined in the power consumption presence / absence determination step, and normal power consumption of the device in the electric signal pattern determined in the power consumption presence / absence determination step And the absolute power consumption value calculation step.

Therefore, in the test vector generating apparatus and the test vector generating method for calculating the power consumption of the present invention, the test vector can be automatically generated in a short time by taking the above means. You can

As a result, the load on the test vector designer can be reduced, and even an operator who does not have specialized knowledge can generate a test vector. In addition, no error occurs due to manual input to the simulator.

[0024]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

An embodiment of the present invention will be described with reference to FIGS.

FIG. 1 is a system configuration diagram showing an example of a power consumption calculation test vector generation apparatus to which a power consumption calculation test vector generation method according to an embodiment of the present invention is applied.

That is, the power consumption calculation test vector generation device 1 to which the power consumption calculation test vector generation method according to the embodiment of the present invention is applied, includes a temporary test vector generation unit 2, a temporary simulation unit 3, and It includes a power consumption presence / absence determination unit 4, a normal test vector generation unit 5, a normal simulation unit 6, and a power consumption absolute value calculation unit 7.

The configuration of the power consumption calculation test vector generation device 1 as shown in FIG. 1 will be described by taking the case of generating the test vector of the logic circuit cell 10 shown in FIG. 3 as an example.

The provisional test vector generator 2 generates the first test vector input to the logic circuit cell 10. The test vector generated here is as shown in FIG.
As shown in (a), all the combinations in which only one of the input terminals is operated and the other is fixed are arranged.

The provisional simulation section 3 is performed for the purpose of later determining the presence or absence of power consumption.

In a normal simulation, a large amount of time is required, but if the presence / absence determination is not the power consumption value, the accuracy is reduced to shorten the simulation time.

In the power consumption presence / absence determining section 4, a temporary simulation is performed for an input waveform as shown in FIG.
Usually, a mountain-shaped current waveform as shown in FIGS. 2B and 2C is obtained. 2B is a diagram of low precision measurement, and FIG. 2C is a diagram of high precision measurement. Since presence / absence detection can be determined by whether or not a certain reference value is exceeded, low accuracy as shown in FIG.

In the normal test vector generation unit 5, only the input patterns which are determined to be present based on the result of presence / absence detection are selected and set as the normal test vector.

The normal simulation section 6 executes a simulation with high accuracy as shown in FIG. 2 (c) by using the normal test vector. Here, the current peak value, total (integral value)
And so on.

[0035]

As described above, according to the present invention,
Generate test vectors automatically in a relatively short time,
The load on the test vector designer can be reduced and the operation can be reduced to a simple operation.

As described above, the test vector generation device and the test vector generation method for calculating the power consumption can be realized by automating the generation of the test vector and the automation of the input thereof.

[Brief description of drawings]

FIG. 1 is a system configuration diagram showing an example of a power consumption test vector generation device to which a power consumption calculation test vector generation method according to an embodiment of the present invention is applied.

FIG. 2 is a schematic diagram showing an example of a power consumption waveform acquired by a power consumption presence / absence determining unit for an input waveform.

FIG. 3 is a circuit configuration diagram showing a logic circuit cell including an inverting element and a NAND element.

FIG. 4 is a timing chart of an input signal, an output signal, and power consumption.

[Explanation of symbols]

A ... Inversion element B ... NAND element 1. Power consumption calculation test vector generation device 2. Temporary test vector generation unit 3 ... Temporary simulation part 4 ... Power consumption presence / absence determination unit 5: Regular test vector generator 6 ... Regular simulation part 7 ... Absolute power consumption value calculation unit 10 ... Logic circuit cell

Claims (3)

[Claims] 1. A test vector generation device for generating a test vector, which is an electrical signal pattern for calculating the power consumption of the device, from an electrical signal pattern input to the device, the electrical vector input to the device. Temporary test vector generation means for inputting a signal pattern, power consumption presence / absence determination means for determining an electrical signal pattern that causes power consumption among the electrical signal patterns input to the temporary test vector generation means, and the power consumption presence / absence determination A normal test vector generation means for simplifying the electric signal pattern determined by the means, and a power consumption absolute value calculation means for calculating the normal power consumption of the device in the electric signal pattern determined by the power consumption presence / absence determination means. A test vector generation device for calculating power consumption. 2. The test vector generation device for power consumption calculation according to claim 1, wherein the device is a logic circuit for power consumption calculation. 3. A test vector generation method for generating a test vector, which is an electric signal pattern for calculating the power consumption of the device, from an electric signal pattern input to the device. A provisional test vector generation step of inputting a signal pattern; a power consumption presence / absence determination step of determining an electric signal pattern that causes power consumption in the electrical signal patterns input in the provisional test vector generation step; and a power consumption presence / absence determination From a normal test vector generation step that simplifies the electrical signal pattern determined in the step, and an absolute power consumption value calculation step that calculates the regular power consumption of the device in the electrical signal pattern determined in the power consumption presence / absence determination step Test vector generation method for power consumption calculation.