JP2003240826A - Interface substrate, inspection system, and inspecting method for inspecting nonstandard memory element in actual operating environment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an interface substrate, an inspection system, and an inspecting method, for making it possible to inspect a nonstandard memory element mounted on a standard substrate for inspection in an actual operating environment. <P>SOLUTION: The system and method for inspecting nonstandard memory elements in an actual operating environment are applicable to nonstandard memory elements by using an interface substrate 100 for adapting a nonstandard pin configuration to a standard pin configuration on a substrate 170 to be inspected. The substrate 100 has a first surface for mounting the substrate 100 on a nonstandard memory element 50, a pin matching circuit, and a second surface structured so as to connect the matching circuit to the standard pin configuration. The substrate 100 is directly mountable on the substrate 170, and connected to the substrate 170, by variously arranging a second socket 120, a socket 140, a connection substrate 130, and support materials 150. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device inspection technique, and more particularly, to an interface board, an inspection system and an inspection method for inspecting a non-standard memory device in an actual operating environment. is there.

[0002]

2. Description of the Related Art FIG. 1 is a diagram for explaining a conventional process for manufacturing and inspecting a semiconductor integrated circuit device and a printed circuit board on which the semiconductor integrated circuit device is mounted. First, a plurality of semiconductor elements are formed on the semiconductor wafer 10. The semiconductor devices are inspected at the wafer level, and defective devices are selectively marked for removal in the sorting process. Thereafter, the good quality device is separated from the wafer.

Each semiconductor device that has passed the wafer level inspection is assembled in a package. The package device 20 is inspected at a package level by a burn-in test that eliminates an initial defective device under high voltage and high temperature conditions, and a functional test is performed to determine the electrical characteristics of the device. Good quality devices that pass the package level inspection are assembled into a printed circuit board type product (for example, the memory module 30 of FIG. 1). A printed circuit board type product is also subjected to an inspection process after assembly.

The above-described conventional inspection process has a problem that the inspection conditions do not always match the actual operating environment of the semiconductor device. Therefore, even a semiconductor device that has passed the burn-in test and the functional test may have defects that cannot be detected until the device is assembled into a board-type product. The cost of repairing and reexamining the board product increases the production cost, and if the repair cannot be performed, the board product must be discarded.

For example, a plurality of semiconductor memory devices are SIM
M (Single Inline Memory Module) or DIMM (D
ual Inline Memory Module) is assembled into a board-type memory module. Such memory modules are installed on a system level board such as a motherboard of a computer system. Even if the memory module has only one memory device that does not work properly, after installing the memory module, it costs a lot of money to remove the defective memory device soldered to the memory module and switch to a normal memory device. Therefore, the entire memory module must be discarded.

Another problem with the conventional inspection process is that the conventional inspection equipment is very complicated, occupies a lot of space and is expensive. In general, a semiconductor memory device manufacturer packages a memory device using an HP83000 inspection device manufactured by Hewlett-Packard Company (“Hewlett-Packard” is a registered trademark) or an inspection device manufactured by Advan Corporation (“Advan” is a registered trademark). To inspect. These inspection devices generate an inspection signal pattern including a memory bus signal (for example, RAS, CAS, a data signal and an address signal) received from a CPU or a chip set when a memory device is mounted on a system-level board. . Such a test signal is supplied to the terminal leads of the test memory device (DUT), and the test device analyzes the signal received from the memory device to determine whether the electrical characteristics of the memory device are correct. Although such an inspection apparatus has high compatibility and can inspect various characteristics, it cannot provide the same environment as the mounting environment in which the memory device actually operates. To provide such compatibility, inspection equipment becomes more complex, more difficult and expensive to operate and program.

In order to provide a test environment closer to the actual operating environment, a board product such as a memory module can be tested on a system-level test board that provides a test environment comparable to the actual operating environment. . For example, the board-type element can be mounted on a motherboard of a computer system used as an inspection board, and the board-type element can be tested in an actual operating environment. In general, board products are JEDEC (Joint Electron Device Engineering)
According to international standards (such as the Council), system level test boards, such as computer system motherboards, have sockets for mounting board products.

The inspection board used for the actual inspection is JED.
Suitable for EC standard memory modules, but not for non-standard memory modules, ie custom memory modules. For example, the JEDEC standard 168-pin DIM, which is a custom module for high-performance servers that uses a 200-pin DIMM for desktop computers.
When mounted on the test board for M, the memory device does not operate correctly because the operating environment provided by the test board is different from the actual operating environment for the 200-pin DIMM.

[0009]

SUMMARY OF THE INVENTION It is an object of the present invention to provide an interface board, an inspection system and an inspection method capable of mounting a non-standard memory element on a standard inspection board and performing mounting inspection in an actual operating environment.

Another object of the present invention is to provide an interface board, an inspection system and an inspection method for inspecting a non-standard memory device capable of improving reliability of the non-standard memory device in an actual operating environment. is there. Still another object of the present invention is to perform a mounting test of a non-standard memory device using a test board of a standard memory device,
An object of the present invention is to provide an interface board, an inspection system and an inspection method for inspecting a non-standard memory device in an actual operating environment, which can improve the efficiency of the inspection process.

[0011]

One aspect of the present invention relates to an inspection system for inspecting non-standard memory devices in an actual operating environment. The inspection system comprises an interface board having a first side, a second side and a pin matching circuit. The socket formed on the first side allows the non-standard memory device to be combined with the pin matching circuit, and the second side is
A pin matching circuit is configured to mate with the standard pin configuration. The second side of the interface board can be directly mounted on the test board. Also, the socket formed on the second surface of the interface board is used to couple the pin matching circuit with the test board.

In the pin matching circuit, a signal having a standard pin configuration is made to correspond to a signal having a non-standard pin configuration on a one-to-one basis.
It has a matching unit. The pin matching circuit has a second matching unit that selectively assigns a signal having a standard pin configuration to a signal having a non-standard pin configuration. Another aspect of the present invention relates to a test method for testing a non-standard memory device having a non-standard pin configuration in an actual operating environment. The test method includes the steps of coupling the interface board with the non-standard memory device such that the non-standard pin configuration of the non-standard memory device matches the standard pin configuration of the test substrate, and activating the test substrate.

Another aspect of the present invention relates to an interface board for testing a non-standard memory device in an actual operating environment. The interface board has a circuit board including a first surface, a second surface, and a circuit wiring layer. Also, the interface board has a first socket formed on the first surface of the circuit board to mount the non-standard memory element and electrically connect the mounted non-standard memory element to the circuit wiring layer. The interface board also has a second socket formed on the second surface of the circuit board and electrically connecting the circuit wiring layer and the standard inspection board. In particular, the interface board has a pin matching circuit formed on the circuit wiring layer to match the standard pin configuration of the standard test board with the non-standard pin configuration of the non-standard memory device.

The pin matching circuit has a first matching section and a second matching section. The first matching unit assigns the standard input of the control signal and the address signal of the standard pin configuration to the non-standard output of the control signal and the address signal of the non-standard pin configuration in a one-to-one correspondence. The second matching unit selectively assigns the standard input of the data input / output signal of the standard pin configuration to the non-standard output of the data input / output signal of the non-standard pin configuration and continuously interleaves the links.

The interface board has a clock inversion circuit formed in a circuit wiring layer by selectively or simultaneously operating two clock signal pins having a non-standard pin configuration with respect to one clock signal pin having a standard pin configuration. . Another aspect of the invention relates to a test system in a real operating environment for non-standard memory devices. The test system has a standard test board that includes multiple components to provide the actual test environment for non-standard memory devices. Inspection system
It has an interface board including a circuit board, first and second sockets, and a pin matching circuit.

The circuit board has a first surface, a second surface and a circuit wiring layer. The first socket is formed on the first surface of the circuit board to mount the non-standard memory device, and electrically connects the memory device and the circuit wiring layer. The second socket is formed on the second surface of the circuit board and electrically connects the circuit wiring layer and the standard inspection board. The pin matching circuit is formed on the circuit wiring layer and matches the standard pin configuration of the standard test board with the nonstandard pin configuration of the nonstandard memory device.

In the inspection system, the interface board has a clock inverting circuit formed in the circuit wiring layer, and selectively selects two clock signal pins of non-standard pin configuration from one clock signal pin of standard pin configuration. Or both at the same time. The interface board can be mounted on any surface of a standard test board, which is the surface on which the plurality of components are formed or the opposite surface.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 2 is a schematic diagram showing an inspection system according to an embodiment of the present invention. The inspection system of FIG. 2 includes a non-standard memory device 50 to be inspected, an interface board 100, and an inspection board 170. In the preferred embodiment, the non-standard memory device 50 is a board product such as a memory module and the test board 170 corresponds to the motherboard of the computer system. Also,
Non-standard memory devices 50 are non-standard or custom devices, while test board 170 is designed to accommodate standard memory devices. For example, a non-standard memory device 50
Is a 200-pin DIMM, and the inspection board 170 has 16
A motherboard suitable for mounting an 8-pin DIMM. The interface board 100 is a type of test board, and is designed to easily mount and separate the non-standard memory device 50.

The interface board 100 includes a support material 15
It is fixed to the inspection board by 0. The interface board 100 includes the second socket 120 and the socket 140.
Also, it is electrically connected to the inspection board 170 via the connection board 130. Other components mounted on the inspection board 170 are not shown in FIG. 2 to simplify the drawing.

In the inspection system of FIG. 2, the non-standard memory device 50 is mounted on the interface board 100, and the inspection board 1
The non-standard memory device 50 can be inspected in an actual operating environment by electrically connecting the interface substrate 100 to 70 and operating the inspection substrate 170. Figure 2
Shows a system designed to create the actual test conditions for a memory element of a computer motherboard, but is only one example. Other types of semiconductor devices can be mounted and tested on other test boards such as servers, communication equipment, motherboards of exchanges.

As shown in FIGS. 2 and 3, the interface board 100 includes a circuit board on which a circuit wiring layer is formed. The first and second sockets 110 and 120 are the first and second surfaces 102 and 1 of the interface board 100, respectively.
It is formed in 04. The second surface 104 is the inspection board 17
It is facing 0. The interface board 100 is preferably a multilayer circuit board having, for example, a power layer, a ground layer, at least one signal layer and an insulating layer such as a glass fiber layer interposed between said layers.

The non-standard memory device 50 is mounted on the first socket 110, and the connection substrate 13 is mounted on the second socket 120.
0 is implemented. The first socket 110 has a structure suitable for easily mounting and separating the non-standard memory device 50, and electrically connects the non-standard device 50 and a circuit wiring layer of the interface board 100. Similarly, the second socket 120 has a structure suitable for easily mounting and separating the connection board 130, and electrically connects the interface board 100 and the inspection board 170.

Each of the first and second sockets 110 and 120 has a flexible connection type pin (not shown) and has a DIP (du
It has the same footprint as the al inline package). The first socket 110 has a groove 112 in which a connection type pin is formed and a non-standard memory device 50 is inserted. The two handles 114 are formed at both ends of the groove 112 and are connected by a pivot. When the non-standard memory element 50 is inserted into the groove 112, the handle 114 is rotated above the pivot axis and the connecting pin bends to maintain the connection with the non-standard memory element 50. Then, the handle 114 is pushed down to easily separate the non-standard memory element 50 in the groove 112 from the groove 112. Such a structure of the first socket 110 not only facilitates the separation of the non-standard memory device 50, but also extends the average life of the first socket 110.

The first socket 110 is a 200-pin DIM.
Whereas the second socket 120 has a pin configuration suitable for non-standard memory modules such as M, the second socket 120 has a pin configuration suitable for standard memory modules such as 168-pin DIMM. The 168-pin DIMM is currently used in most desktop computers. 168-pin DI
MM is FPM, EDO and SDRAM (synchronous DRA
It is implemented with at least three memory types of M). These configurations have wide data paths of 64-bit, 72-bit, and 80-bit, and ECC (Error Check Cod)
e) or non-ECC, memory size is 1
6, 32, 64, 128, 256, 512 and 1024
There is a format of MB.

In order to test the non-standard memory device 50 in an actual operating environment, it is necessary to match the pin configuration of the non-standard memory device 50 with the pin configuration of the standard socket, that is, the second socket 120. Below, the interface board 1
A pin matching circuit for 00 will be described. The interface board 100 has impedance, signal integrity (si
It is preferable to create an accurate inspection environment for semiconductor devices and eliminate the effects of signal distortion and noise by using components that have been verified by gnal integrity) measurements. In addition, the interface board 100 includes a case where the non-standard memory device 50 is directly mounted on the inspection board 170 and a case where the non-standard memory device 50 includes the first and second sockets 110 and 12.
It is preferably designed to compensate for the difference in environment from the case of being connected to the inspection board 170 via the connection board 130 and the connecting board 130. Such environmental compensation includes timing adjustment of clock signals, timing margin adjustment of control signals, AC parameter adjustment of signals, adjustment of power supply signals, and the like.

A pin matching circuit according to an embodiment of the present invention is shown in FIG. The pin matching circuit 200 formed on the circuit wiring layer of the interface board described above has a non-standard pin configuration (for example, 200 pin configuration) and a standard pin configuration (for example, 16 pin configuration).
8 pin configuration). The pin matching circuit 200 includes a first matching unit 20 for control signals and address signals.
2, a second matching unit 204 for the data input / output signal (DQ), and a third matching unit 206 for the power supply signal (Vcc / GND). In the preferred embodiment, the first matching section 202 includes a standard pin configuration 21.
0 control signal and address signal non-standard pin configuration 220
The control signals and the address signals are assigned to correspond one-to-one. The second matching unit 204 transfers the data input / output signal of the standard pin configuration 210 to the non-standard pin configuration 220.
Data input / output signals are selectively assigned and continuously interleaved.

In the embodiment for matching the 200 pin output to the 168 pin input, the control / address signal is W
E (Write Enable), DQM (Data Input / Output Mas
k), CS (Chip Select), CLK (System Clock),
CKE (Clock Enable), RAS (Row Address Strob)
e), CAS (Column Address Strobe), SDA (Seri
al Data I / O), SCL (Serial Clock), SA (Addre
ss in EEPROM), WP (Write Protection), A0-A
12 (address) and BA0 to BA1 (BankSelect Ad
dress) is included. For example, No. 27
The input pin is a No. designated WE. No. corresponding to 148 output pins and named CLK0. 42 input pins are
No. CLK0. Corresponds to 151 output pins. On the other hand, the DQ signal input pins named DQ0 to DQ63 and the CB0 to CB7 (check bit) are continuously named DQ0 to DQ71 in the interleaving order.
It is linked to the Q signal output pin. For example, DQ0-3,
DQ4 ~ 7 and DQ8 ~ 11 input pins are DQ64 ~ 6
7, DQ60-63 and DQ48-51 output pins, respectively.

The interface board according to the present embodiment further includes a clock inverting circuit. FIG. 5 is a block diagram showing the clock inverting circuit 230, and FIG. 6 is an output signal waveform diagram of the clock inverting circuit. The clock inversion circuit 23 formed in the circuit wiring layer of the interface board described above.
0 is the pin CLK0 (No. 4 of the 168-pin DIMM).
2) input terminal 232 connected to pin CLK0 (20
No. 0 pin DIMM No. 151) and the first output terminal 234, as well as the pin CLK1 (200 pin DIM).
M No. 150) and has a second output terminal 236 connected thereto.

The clock inversion circuit 230 has two resistance circuits 240 and 250 connected in parallel between the positive power supply terminal Vdd and the ground terminal Vss. First resistance circuit 240
Is a first resistor R1 connected between the power supply terminal Vdd and the first node N1, and the first node N1 and the ground terminal Vs.
It has a second resistor R2 connected between s. Similarly, the second resistance circuit 250 includes a power supply terminal Vdd and a second node N2.
And a fourth resistor R2 connected between the second node N2 and the ground terminal Vss, and a fourth resistor R2 similar to the second resistor. It is preferable that the first and third resistors R1 have a much smaller resistance value than the second and fourth resistors R2. For example, R1 is 100Ω and R2 is 10 kΩ. The first node N1 is connected to the input terminal 232 and the first output terminal 234, and the second node N2 is connected to the second output terminal 236.

The clock inversion circuit 230 shown in FIG.
Enables testing of 00-200 pin devices and PC133-200 pin devices. Here, PC100 and PC133
Is the CPU of the computer system (or inspection board)
And the data processing speed between the memory modules are 100 MHz and 133 MHz, respectively. Other processing speeds can also be applied. 200 pin-PC
100 modules have system clock signal pin CLK
0 (CLK1 is not connected in this case (NC))
200 pin-PC13 configured to use only
The three modules are configured to use system clock signal pins CLK0 and CLK1. The clock inversion circuit 230 separates CLK1 when testing the 200-pin-PC100 module,
When testing 33 modules, CLK0 and CLK1 are simultaneously operated.

When a 3.3V power supply voltage is applied to the clock inverting circuit 230, 1 connected to the input terminal 232.
The 68-pin DIMM CLK0 is set high or low. When CLK0 is high level, the first node N1 maintains high level, and therefore the first output terminal 23
CLK0 of the 4- and 200-pin DIMMs also stay high. On the other hand, when CLK0 of the 168-pin DIMM is low level, CLK0 of the 200-pin DIMM also falls to low level, so that the value of R1 becomes smaller than R2.

Since the first and second resistance circuits 240 and 250 have the common power supply terminal Vdd, the 200-pin DI
MM CLK1 follows the level change of 168 pin DIMM CLK0. However, the power supply terminal Vd
Since the charge supplied from d always flows in parallel with the first resistance circuit 240, the change in CLK1 of the 200-pin DIMM is much smaller than the change in CLK0 of the 200-pin DIMM, and therefore the charge flowing in the second resistance circuit 250. Is
It is limited by the voltage level of the first node N1. This is confirmed by the waveform shown in FIG.

FIG. 7 shows an example of a test board used to provide an actual operating environment in this embodiment. The inspection board 170 includes an ISA connector 262, a PCI connector 264, a PCI audio controller 266, various line connectors 268, a back panel connector 270, a slot connector 272, a PCI / AGP controller 274, and a DIMM.
Socket 276, IDE connector 278, LED connector 280, diskette drive connector 282, power supply connector 284, IDE accelerator 286, battery 288, AGP connector 290, front panel connector 2
It has various parts such as 92. The components mounted on the inspection board 170 are not limited to those shown in FIG. 7, and various various components can be applied to the inspection board 170 depending on desired operating conditions for inspecting a semiconductor element.

FIG. 8 shows an inspection system according to another embodiment. Referring to FIG. 8, the inspection system 300 includes a standard inspection board 170 on which a plurality of components 310 are mounted.
The component 310 provides the actual test condition to the non-standard memory device 50. The inspection board 170 includes a top surface 302 and a bottom surface 3
Have 04. The top surface 302 mounts not only the component 310 but also the interface board 100. Support material 150
Fixes the interface board 100 on which the non-standard memory device 50 is mounted to the inspection board 170. The electrical connection between the non-standard memory device 50 and the test board 170 is performed by the first and second sockets 110 and 12 of the interface board 100.
0, the connection board 130, and the socket 140 of the inspection board 170.

FIG. 9 shows an inspection system 400 according to yet another embodiment. As shown in FIG. 9, the component 310,
320 is mounted on the bottom surface 304 of the inspection board 270, while the interface board 100 is directly mounted on the top surface 302. Therefore, such an alignment provides a space that facilitates mounting and separation of the interface board 100, and allows easy replacement of devices when testing a large number of devices.

The present invention can be implemented in various other forms without departing from the technical idea of the present invention.
The above-mentioned embodiments are merely for clarifying the technical contents of the present invention, and should not be construed in a narrow sense by limiting only to such specific examples. Various modifications can be made within the range.

[0037]

According to the present invention, a memory element can be inspected in the actual operating environment of the non-standard memory element with the non-standard or custom memory element mounted on the standard inspection board. Therefore, it is possible to reduce the cost and procedure required for mounting inspection of the non-standard memory device, improve the reliability of the non-standard memory device, and increase the productivity of the inspection process for the non-standard memory device. it can.

[Brief description of drawings]

FIG. 1 is a schematic view showing a conventional process for inspecting a semiconductor device.

FIG. 2 is a schematic sectional view showing an inspection system according to an embodiment of the present invention.

FIG. 3 is an exploded perspective view showing an interface board according to an exemplary embodiment of the present invention.

FIG. 4 is a block diagram showing a pin matching circuit of an interface board according to an exemplary embodiment of the present invention.

FIG. 5 is a block diagram showing a clock inversion circuit of an interface board according to an embodiment of the present invention.

FIG. 6 is a waveform diagram showing an output signal of the clock inverting circuit according to the embodiment of the present invention.

FIG. 7 is a plan view showing an inspection board according to an embodiment of the present invention.

FIG. 8 is a schematic sectional view showing an inspection system according to another embodiment of the present invention.

FIG. 9 is a schematic cross-sectional view showing an inspection system according to another embodiment of the present invention.

[Explanation of symbols]

50 Non-standard memory device 100 interface board 102 First side 104 Second side 110 First socket 120 Second socket 130 connection board 140 socket 150 support material 170 inspection board 200-pin matching circuit 230 clock inversion circuit 240, 250 First and second resistance circuits 232 input terminal 234, 236 First and second output terminals 300, 400 mounting inspection system

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Kim Good Pillar             555-2 Ssangyong-dong, Cheonan-si, Chungcheongnam-do, South Korea             Nsunsun Apartment 102, No. 401 (72) Inventor Park Hye             874 Sinho-dong, Cheonan-si, Chungcheongnam-do, South Korea             Shi Saemaru Apartment 204 Building No. 1305 (72) Inventor Xu Zhan             South Korea Chungcheongnam-do Cheonan-si Sangryu-dong 1-dong resident Apa             510 510 1502 F-term (reference) 2G132 AA08 AA20 AB20 AE21 AG08                       AJ07 AL06 AL29 AL33                 5L106 DD21 GG01 GG05

Claims (35)

[Claims] 1. An interface board for inspecting a non-standard memory device in an actual operating environment, the circuit board having a first surface, a second surface and a circuit wiring layer, and a first surface of the circuit board. A first socket formed to mount a non-standard memory element and electrically connecting the non-standard memory element to the circuit wiring layer; and a second socket formed on the second surface of the circuit board, the circuit wiring layer and the standard A second socket electrically connecting to a test board; and a pin matching circuit formed on the circuit wiring layer for matching the standard pin configuration of the standard test board with the non-standard pin configuration of the non-standard memory device. An interface board comprising. 2. A clock inversion circuit formed in the circuit wiring layer and operating two clock signal pins of the non-standard pin configuration continuously or selectively with respect to one clock signal pin of the standard pin configuration. The interface board according to claim 1, further comprising: 3. The pin matching circuit includes a first matching unit that assigns the control signal and the address signal of the standard pin configuration to the control signal and the address signal of the non-standard pin configuration to make one-to-one correspondence. The interface board according to claim 1, wherein the interface board is provided. 4. The second matching unit, wherein the pin matching circuit selectively assigns the data input / output signal of the standard pin configuration to the data input / output signal of the non-standard pin configuration and continuously interleaves links. The interface board according to claim 3, wherein the interface board is provided. 5. The circuit wiring layer includes a power supply layer, a ground layer, and at least one signal layer electrically insulated from each other and having a multilayer structure.
Interface board according to. 6. The interface board according to claim 1, wherein the first socket is formed in a form adapted to a board type product in which the non-standard memory device is used. 7. The interface board according to claim 1, wherein the first socket has a groove formed with a connection pin that can be temporarily connected to the non-standard memory device. 8. The clock inverting circuit comprises: an input terminal connected to the clock signal pin having the standard pin configuration; and a first clock signal pin and a second clock signal pin having the non-standard pin configuration, respectively. 1 output terminal and 2nd
The interface board according to claim 2, further comprising an output terminal, a first resistance circuit and a second resistance circuit connected in parallel between the power supply terminal and the ground terminal. 9. The first resistance circuit has a first resistance connected between the input terminal and the power supply terminal, and a second resistance connected between the input terminal and the ground terminal. The second resistance circuit has a third resistance connected between the second output terminal and the power supply terminal, and a fourth resistance connected between the second output terminal and the ground terminal. The interface board according to claim 8, wherein the first output terminal is directly connected to the input terminal. 10. The first resistor and the third resistor have the same resistance value, the second resistor and the fourth resistor have the same resistance value, and the first resistor is more resistive than the second resistor. The interface board according to claim 9, which has a small value. 11. The interface board according to claim 1, wherein the non-standard memory device is a 200-pin memory module, and the standard test board is a system motherboard for mounting a 168-pin memory module. 12. When the non-standard memory device is a PC100 device, only one clock signal pin of the non-standard pin configuration operates, and the non-standard memory device is a PC13 device.
3. The interface board according to claim 2, wherein two clock signal pins of the non-standard pin configuration operate simultaneously in the case of three elements. 13. A test system comprising a standard test board having a plurality of parts for providing a non-standard memory device with an actual test environment, and an interface board for testing the non-standard memory device in the actual operating environment. The interface board includes a circuit board having a first surface, a second surface, and a circuit wiring layer, and a non-standard memory element formed on the first surface of the circuit board, the non-standard memory element being mounted on the circuit board. A first socket for electrically connecting the circuit wiring layer, a second socket formed on a second surface of the circuit board for electrically connecting the circuit wiring layer and the standard inspection board, and the circuit An inspection system, comprising: a pin matching circuit formed on a wiring layer to match a standard pin configuration of the standard inspection board with a non-standard pin configuration of the non-standard memory device. 14. The interface board is formed in the circuit wiring layer, and selectively or simultaneously operates two clock signal pins of the non-standard pin configuration with respect to one clock signal pin of the standard pin configuration. 14. The inspection system according to claim 13, further comprising a clock inverting circuit. 15. The inspection system according to claim 13, wherein the interface board is mounted on a surface of the standard inspection board on which a plurality of components are formed. 16. The inspection system according to claim 13, wherein the interface board is mounted on a surface opposite to a surface of the standard inspection board on which a plurality of components are formed. 17. The pin matching circuit includes a first matching unit that assigns a control signal and an address signal of the standard pin configuration to a control signal and an address signal of the non-standard pin configuration to make one-to-one correspondence, and the standard matching unit. 14. The second matching unit according to claim 13, further comprising a second matching unit for selectively allocating a data input / output signal having a pin configuration to the data input / output signal having the non-standard pin configuration and continuously interleaving a link. Inspection system. 18. The clock inverting circuit comprises: an input terminal connected to the clock signal pin having the standard pin configuration; and a first clock signal pin and a second clock signal pin having the non-standard pin configuration. The inspection system according to claim 14, further comprising a first output terminal and a second output terminal, and a first resistance circuit and a second resistance circuit connected in parallel between the power supply terminal and the ground terminal. 19. The first resistance circuit has a first resistance connected between the input terminal and the power supply terminal, and a second resistance connected between the input terminal and the ground terminal. The second resistance circuit has a third resistance connected between the second output terminal and the power supply terminal, and a fourth resistance connected between the second output terminal and the ground terminal. The first output terminal is directly connected to the input terminal, the first resistance and the third resistance have the same resistance value, and the second resistance and the fourth resistance have the same resistance value, The first
The inspection system according to claim 18, wherein the resistance has a resistance value smaller than that of the second resistance. 20. The inspection system of claim 13, wherein the non-standard memory device is a 200-pin memory module, and the standard test board is a system motherboard for mounting a 168-pin memory module. 21. An inspection system for inspecting a non-standard memory device in an actual operating environment, comprising: an interface substrate having a first surface, a second surface and a pin matching circuit; and a non-standard formed on the first surface. An inspection system, comprising: a socket for coupling a memory device with the pin matching circuit, wherein the second surface is configured to couple the pin matching circuit with a standard pin configuration. 22. The inspection system according to claim 21, further comprising an inspection board directly mounted on the second surface of the interface board. 23. The socket is a first socket, and further comprises a second socket formed on the second surface of the interface board for coupling the pin matching circuit to an inspection board. Inspection system described in. 24. The inspection system of claim 23, further comprising an inspection board coupled to the second socket. 25. The inspection system according to claim 23, further comprising a connection board coupled between the second socket and the inspection board. 26. The inspection system according to claim 25, wherein the inspection board has a third socket configured to mount the connection board. 27. The inspection system of claim 25, further comprising a support material configured to attach the interface board to the inspection board. 28. The interface board according to claim 21, further comprising a clock inverting circuit for operating two clock signal pins having a non-standard pin configuration with respect to one clock signal pin having the standard pin configuration. Inspection system described. 29. The pin matching circuit has a first-to-one correspondence between the signals of the standard pin configuration and the non-standard pin configuration.
The inspection system according to claim 21, further comprising a matching unit. 30. The inspection system according to claim 29, wherein the pin matching circuit includes a second matching unit that selectively assigns the signal of the standard pin configuration to the signal of the non-standard pin configuration. 31. A test method for testing a non-standard memory device having a non-standard pin configuration in an actual operating environment, wherein the non-standard pin configuration of the non-standard memory device is adapted to the standard pin configuration of a test board. And connecting the interface board to the non-standard memory device, and activating the test board. 32. The step of coupling the non-standard memory device with the interface board includes coupling the non-standard memory element with a socket formed on a first surface of the interface board. Item 31
Inspection method described in. 33. The interface board has a pin matching circuit coupled to the socket, and a second surface configured to couple the pin matching circuit to a standard pin configuration of the test board. The inspection method according to claim 32. 34. The inspection method according to claim 31, wherein the interface board is connected to the inspection board by a connection board. 35. The interface board is directly mounted on the inspection board.
Inspection method described in.