JP4154226B2 - Interface board, inspection system, and inspection method for inspecting non-standard memory device in actual operating environment - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device inspection technique, and more particularly to an interface board, an inspection system, and an inspection method for inspecting a non-standard memory device in an actual operating environment.
[0002]
[Prior art]
FIG. 1 is a diagram for explaining a conventional process for manufacturing and inspecting a semiconductor integrated circuit element and a printed circuit board on which the semiconductor integrated circuit element is mounted. First, a plurality of semiconductor elements are formed on the semiconductor wafer 10. The semiconductor elements are inspected at the wafer level, and defective elements are selectively marked for removal in a classification process. Thereafter, the good quality elements are separated from the wafer.
[0003]
Each semiconductor device that passes the wafer level inspection is assembled in a package. The package element 20 is inspected at the package level by a burn-in test that eliminates initial defective elements under high voltage and high temperature conditions, and a function test is performed to determine the electrical characteristics of the element. High-quality elements that pass the package level inspection are assembled into a printed circuit board type product (for example, the memory module 30 in FIG. 1). An inspection process is also performed after assembly on a printed circuit board type product.
[0004]
The conventional inspection process described above has a problem that the inspection conditions do not always match the actual operating environment of the semiconductor element. Therefore, even a semiconductor element that has passed the burn-in inspection and the function inspection may have a defect that could not be detected until the element was assembled in a substrate type product. The production cost increases due to the cost required for repair and re-inspection of the board product, and if the repair cannot be performed, the board product must be discarded.
[0005]
For example, a plurality of semiconductor memory devices are assembled into a substrate type memory module such as a single inline memory module (SIMM) or a dual inline memory module (DIMM). Such memory modules are installed on a system level board such as a motherboard of a computer system. Even if the memory module has only one memory element that does not work properly, after installation of the memory module, it takes a lot of money to remove the defective memory element soldered to the memory module and switch to a normal memory element Therefore, the entire memory module must be discarded.
[0006]
Another problem with the conventional inspection process is that the conventional inspection equipment is very complex, occupies a lot of space and is expensive. In general, manufacturers of semiconductor memory devices use a HP 83000 inspection device from Hewlett-Packard ("Hewlett-Packard" is a registered trademark) or an inspection facility from Advan ("Advan" is a registered trademark) to package memory devices. Inspect. These inspection apparatuses generate inspection signal patterns including memory bus signals (for example, RAS, CAS, data signals, and address signals) received from a CPU or a chipset when a memory element is mounted on a system level board. . Such an inspection signal is supplied to a terminal lead of a test memory element (DUT), and the inspection apparatus analyzes the signal received from the memory element to determine whether the electrical characteristics of the memory element are correct. Such an inspection apparatus is highly compatible and can inspect various characteristics, but cannot provide the same environment as the mounting environment in which the memory element actually operates. In order to provide such compatibility, the inspection device becomes more complex, more difficult and expensive to operate and program.
[0007]
In order to provide an inspection environment closer to the actual operating environment, a substrate product such as a memory module can be inspected on a system level inspection substrate that provides an inspection environment comparable to the actual operating environment. For example, the board-type element can be mounted on a motherboard of a computer system used as an inspection board, and the board-type element can be inspected in an actual operating environment. In general, a board product conforms to an international standard such as JEDEC (Joint Electron Device Engineering Council), and a system level inspection board such as a motherboard of a computer system has a socket for mounting the board product.
[0008]
The test board used for the actual test is suitable for the JEDEC standard memory module, but not for the non-standard memory module, i.e. the custom memory module. For example, when a 200-pin DIMM, which is a custom module for a high-performance server, is mounted on a test board for a JEDEC standard 168-pin DIMM used in a desktop computer, the operating environment provided by the test board is 200-pin DIMM. The memory device does not operate correctly because it is different from the actual operating environment.
[0009]
[Problems to be solved by the invention]
An object of the present invention is to provide an interface board, an inspection system, and an inspection method that can be mounted and inspected in an actual operating environment by mounting a nonstandard memory element on a standard inspection board.
[0010]
It is another object of the present invention to provide an interface board, an inspection system, and an inspection method for inspecting a non-standard memory device in an actual operating environment that can improve the reliability of the non-standard memory device. Still another object of the present invention is to implement a non-standard memory device in an actual operation by performing a mounting inspection of the non-standard memory device using a test substrate of the standard memory device, thereby increasing the efficiency of the inspection process. An object of the present invention is to provide an interface board, an inspection system, and an inspection method for inspecting in an environment.
[0011]
[Means for Solving the Problems]
One aspect of the present invention relates to an inspection system for inspecting non-standard memory devices in an actual operating environment. The inspection system includes an interface board having a first surface, a second surface, and a pin matching circuit. A socket formed on the first surface can couple the non-standard memory device with the pin matching circuit, and the second surface is configured such that the pin matching circuit couples with the standard pin configuration. The second surface of the interface board can be directly mounted on the inspection board. A socket formed on the second surface of the interface board is used to couple the pin matching circuit to the inspection board.
[0012]
The pin matching circuit includes a first matching unit that makes a standard pin configuration signal correspond to a non-standard pin configuration signal on a one-to-one basis. The pin matching circuit includes a second matching unit that selectively assigns a standard pin configuration signal to a non-standard pin configuration signal.
Another aspect of the present invention relates to an inspection method for inspecting a non-standard memory device having a non-standard pin configuration in an actual operating environment. The inspection method includes coupling the interface board with the non-standard memory element to match the non-standard pin configuration of the non-standard memory element with the standard pin configuration of the test board and operating the test board.
[0013]
Another aspect of the present invention relates to an interface board for testing non-standard memory devices in an actual operating environment. The interface board has a circuit board including a first surface, a second surface, and a circuit wiring layer. The interface board includes a first socket formed on the first surface of the circuit board for mounting the non-standard memory element and electrically connecting the mounted non-standard memory element and the circuit wiring layer. The interface board has a second socket that is formed on the second surface of the circuit board and electrically connects the circuit wiring layer and the standard inspection board. In particular, the interface board is formed in a circuit wiring layer and has a pin matching circuit that matches the standard pin configuration of the standard test board with the non-standard pin configuration of the non-standard memory device.
[0014]
The pin matching circuit includes a first matching unit and a second matching unit. The first matching unit assigns the standard input of the standard pin configuration control signal and the address signal to the control signal of the non-standard pin configuration and the non-standard output of the address signal on a one-to-one basis to correspond to each other. The second matching unit selectively assigns the standard input of the data input / output signal having the standard pin configuration to the non-standard output of the data input / output signal having the non-standard pin configuration, and continuously interleaves the links.
[0015]
The interface board selectively or simultaneously operates two clock signal pins having a non-standard pin configuration with respect to one clock signal pin having a standard pin configuration, and has a clock inverting circuit formed in a circuit wiring layer.
Another aspect of the invention relates to an inspection system in an actual operating environment for non-standard memory devices. The inspection system has a standard inspection board that includes a plurality of components to provide an actual inspection environment for non-standard memory devices. The inspection system includes an interface board including a circuit board, first and second sockets, and a pin matching circuit.
[0016]
The circuit board has a first surface, a second surface, and a circuit wiring layer. The first socket is formed on the first surface of the circuit board, is mounted with a non-standard memory element, and electrically connects the memory element and the circuit wiring layer. The second socket is formed on the second surface of the circuit board, and electrically connects the circuit wiring layer and the standard inspection board. The pin matching circuit is formed in the circuit wiring layer and matches the standard pin configuration of the standard test board with the non-standard pin configuration of the non-standard memory device.
[0017]
In the inspection system, the interface board includes a clock inversion circuit formed in a circuit wiring layer, and selectively or simultaneously two clock signal pins having a non-standard pin configuration with respect to one clock signal pin having a standard pin configuration. Make it work.
The interface board can be mounted on any surface of a standard test board, which is the surface on which a plurality of components are formed or the opposite surface.
[0018]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
FIG. 2 is a schematic view schematically showing an inspection system according to an embodiment of the present invention. The inspection system of FIG. 2 includes a non-standard memory device 50 to be inspected, an interface substrate 100, and an inspection substrate 170. In the preferred embodiment, the non-standard memory device 50 is a board product such as a memory module, and the test board 170 corresponds to the motherboard of the computer system. Also, the non-standard memory element 50 is a non-standard or custom-type element, whereas the test board 170 is designed to accommodate standard memory elements. For example, the non-standard memory device 50 is a 200-pin DIMM, and the test board 170 is a motherboard suitable for mounting a 168-pin DIMM. The interface board 100 is a kind of inspection board and is designed to easily mount and separate the non-standard memory device 50.
[0019]
The interface board 100 is fixed to the inspection board by a support material 150. The interface board 100 is electrically connected to the inspection board 170 through the second socket 120, the socket 140, and the connection board 130. Other components mounted on the inspection board 170 are not shown in FIG. 2 in order to simplify the drawing.
[0020]
In the inspection system of FIG. 2, the non-standard memory device 50 is mounted on the interface board 100, the interface board 100 is electrically connected to the inspection board 170, and the inspection board 170 is operated. The memory element 50 can be inspected. FIG. 2 shows a system designed to create actual test conditions for a computer motherboard memory device, but is only an example. Other types of semiconductor elements can be mounted and tested on other test boards such as servers, communication equipment, switchboard motherboards.
[0021]
As shown in FIGS. 2 and 3, the interface board 100 includes a circuit board on which a circuit wiring layer is formed. The first and second sockets 110 and 120 are formed on the first and second surfaces 102 and 104 of the interface board 100, respectively. The second surface 104 faces the inspection substrate 170. The interface board 100 is preferably a multilayer circuit board having, for example, a power supply layer, a ground layer, at least one signal layer, and an insulating layer such as a glass fiber layer inserted between the layers.
[0022]
A non-standard memory element 50 is mounted on the first socket 110, and a connection board 130 is mounted on the second socket 120. The first socket 110 has a structure suitable for easily mounting and separating the non-standard memory device 50 and electrically connects the non-standard device 50 and the circuit wiring layer of the interface board 100. Similarly, the second socket 120 has a structure suitable for easily mounting and separating the connection board 130, and electrically connects the interface board 100 and the inspection board 170.
[0023]
The first and second sockets 110 and 120 have flexible connection pins (not shown) and have a footprint similar to that of a dual inline package (DIP). The first socket 110 has a groove 112 in which a connection type pin is formed and into which the non-standard memory device 50 is inserted. The two handles 114 are formed at both ends of the groove 112 and are connected by a pivot shaft. When the non-standard memory element 50 is inserted into the groove 112, the handle 114 is rotated above the pivot axis and the connection type pins are bent to maintain a connection with the non-standard memory element 50. Thereafter, when the handle 114 is pushed down, the non-standard memory element 50 in the groove 112 can be easily separated from the groove 112. Such a structure of the first socket 110 not only facilitates the separation of the non-standard memory device 50 but also can extend the average life of the first socket 110.
[0024]
The first socket 110 has a pin configuration suitable for a non-standard memory module such as a 200-pin DIMM, while the second socket 120 has a pin configuration suitable for a standard memory module such as a 168-pin DIMM. . 168-pin DIMMs are currently used in most desktop computers. The 168-pin DIMM is implemented with at least three memory types: FPM, EDO, and SDRAM (synchronous DRAM). These configurations have a wide data path of 64-bit, 72-bit, and 80-bit, and are configured by ECC (Error Check Code) or non-ECC, and the memory size is 16, 32, 64, 128. There are 256, 512 and 1024 MB formats.
[0025]
In order to test the non-standard memory device 50 in an actual operating environment, it is necessary to match the pin configuration of the non-standard memory device 50 with the pin configuration of the standard socket, that is, the second socket 120. Hereinafter, a pin matching circuit for the interface board 100 will be described. The interface board 100 preferably uses components verified by impedance and signal integrity measurements to create an accurate inspection environment for semiconductor devices and eliminate the effects of signal distortion and noise. . In addition, the interface board 100 is connected to the inspection board 170 via the first and second sockets 110 and 120 and the connection board 130 when the non-standard memory element 50 is directly mounted on the inspection board 170. It is preferably designed to compensate for environmental differences from when connected. Such environmental compensation includes clock signal timing adjustment, control signal timing margin adjustment, signal AC parameter adjustment, power supply signal adjustment, and the like.
[0026]
A pin matching circuit according to an embodiment of the present invention is shown in FIG. The pin matching circuit 200 formed on the circuit wiring layer of the interface board described above adapts the non-standard pin configuration (for example, 200-pin configuration) to the standard pin configuration (for example, 168-pin configuration). The pin matching circuit 200 includes a first matching unit 202 for a control signal and an address signal, a second matching unit 204 for a data input / output signal (DQ), and a third matching for a power signal (Vcc / GND). Part 206. In the preferred embodiment, the first matching unit 202 assigns the control signal and address signal of the standard pin configuration 210 to the control signal and address signal of the non-standard pin configuration 220, respectively, so as to correspond one-to-one. The second matching unit 204 selectively assigns the data input / output signals of the standard pin configuration 210 to the data input / output signals of the non-standard pin configuration 220 and continuously interleaves the links.
[0027]
In the embodiment for matching the 200-pin output to the 168-pin input, the control / address signals are WE (Write Enable), DQM (Data Input / Output Mask), CS (Chip Select), CLK (System Clock), CKE. (Clock Enable), RAS (Row Address Strobe), CAS (Column Address Strobe), SDA (Serial Data I / O), SCL (Serial Clock), SA (Address in EEPROM), WP (Write Protection), A0 to A12 (Address) and BA0 to BA1 (Bank Select Address). For example, No. named WE. The 27th input pin is No. WE named. Corresponds to the No. 148 output pin and is designated No. CLK0. The 42 input pin is a No. 42 named CLK0. Corresponds to the 151 output pin. On the other hand, DQ signal input pins named DQ0 to DQ63 and CB0 to CB7 (check bit) are linked to DQ signal output pins named DQ0 to DQ71 sequentially in interleaving order. For example, DQ0-3, DQ4-7, and DQ8-11 input pins correspond to DQ64-67, DQ60-63, and DQ48-51 output pins, respectively.
[0028]
The interface board according to this embodiment further includes a clock inverting circuit. FIG. 5 is a block diagram showing the clock inverting circuit 230, and FIG. 6 is an output signal waveform diagram of the clock inverting circuit. The clock inverting circuit 230 formed on the circuit wiring layer of the interface board described above is connected to the input terminal 232 connected to the pin CLK0 (168-pin DIMM No. 42) and to the pin CLK0 (200-pin DIMM No. 151). And a second output terminal 236 connected to the pin CLK1 (No. 150 of the 200-pin DIMM).
[0029]
The clock inverting circuit 230 includes two resistance circuits 240 and 250 connected in parallel between the positive power supply terminal Vdd and the ground terminal Vss. The first resistance circuit 240 includes a first resistor R1 connected between the power supply terminal Vdd and the first node N1, and a second resistor R2 connected between the first node N1 and the ground terminal Vss. Similarly, the second resistor circuit 250 is connected between the power supply terminal Vdd and the second node N2, and is connected between the third resistor R1 similar to the first resistor, and between the second node N2 and the ground terminal Vss. The fourth resistor R2 is the same as the second resistor. The first and third resistors R1 preferably have a very small resistance value compared to the second and fourth resistors R2. For example, R1 is 100Ω and R2 is 10 kΩ. The first node N1 is connected to the input terminal 232 and the first output terminal 234, and the second node N2 is connected to the second output terminal 236.
[0030]
The clock inverting circuit 230 of FIG. 5 enables inspection of the PC100-200 pin element and the PC133-200 pin element. Here, the PC 100 and the PC 133 mean the data processing speed between the CPU and the memory module of the computer system (or inspection board), and are 100 MHz and 133 MHz, respectively. Other processing speeds can also be applied. The 200-pin-PC100 module is configured to use only the system clock signal pin CLK0 (in this case, CLK1 is not connected (NC)), and the 200-pin-PC133 module uses the system clock signal pins CLK0 and CLK1. Configured to use. The clock inversion circuit 230 separates CLK1 when inspecting the 200-pin-PC100 module, and operates CLK0 and CLK1 simultaneously when inspecting the 200-pin-PC133 module.
[0031]
When a power supply voltage of 3.3 V is applied to the clock inverting circuit 230, CLK0 of the 168 pin DIMM connected to the input terminal 232 is set to a high level or a low level. When CLK0 is at a high level, the first node N1 maintains a high level, and therefore, the first output terminal 234 and the CLK0 of the 200-pin DIMM also maintain a high level. On the other hand, when CLK0 of the 168-pin DIMM is at a low level, CLK0 of the 200-pin DIMM also falls to a low level, so that the value of R1 is smaller than R2.
[0032]
Since the first and second resistance circuits 240 and 250 have a common power supply terminal Vdd, CLK1 of the 200-pin DIMM follows the change in the level of CLK0 of the 168-pin DIMM. However, since the charge supplied from the power supply terminal Vdd always flows in parallel with the first resistor circuit 240, the change in CLK1 of the 200-pin DIMM is much smaller than the change in CLK0 of the 200-pin DIMM, and thus the second resistor circuit The charge flowing through 250 is limited by the voltage level of the first node N1. This is confirmed by the waveform shown in FIG.
[0033]
FIG. 7 shows an example of an inspection board used in this embodiment to provide an actual operating environment. The inspection board 170 includes an ISA connector 262, a PCI connector 264, a PCI audio controller 266, various line connectors 268, a back panel connector 270, a slot connector 272, a PCI / AGP controller 274, a DIMM socket 276, an IDE connector 278, and an LED connector. 280, a diskette drive connector 282, a power supply connector 284, an IDE accelerator 286, a battery 288, an AGP connector 290, and a front panel connector 292. The components mounted on the inspection substrate 170 are not limited to those shown in FIG. 7, and various various components can be applied to the inspection substrate 170 depending on desired operating conditions for inspecting the semiconductor element.
[0034]
FIG. 8 shows an inspection system according to another embodiment. Referring to FIG. 8, the inspection system 300 includes a standard inspection board 170 on which a plurality of components 310 are mounted. Component 310 provides actual test conditions for non-standard memory device 50. The inspection substrate 170 has a top surface 302 and a bottom surface 304. The top surface 302 mounts the interface substrate 100 as well as the component 310. The support member 150 fixes the interface substrate 100 on which the nonstandard memory element 50 is mounted to the inspection substrate 170. The non-standard memory device 50 and the test board 170 are electrically connected by the first and second sockets 110 and 120 of the interface board 100, the connection board 130, and the socket 140 of the test board 170.
[0035]
FIG. 9 shows an inspection system 400 according to yet another embodiment. As shown in FIG. 9, the components 310 and 320 are mounted on the bottom surface 304 of the inspection substrate 270, while the interface substrate 100 is directly mounted on the top surface 302. Accordingly, such an alignment provides a space that facilitates mounting and separation of the interface board 100, and allows the elements to be easily replaced when inspecting a large number of elements.
[0036]
The present invention can be implemented in various other forms without departing from the technical idea of the present invention. The foregoing embodiments are merely to clarify the technical contents of the present invention, and should not be construed in a narrow sense as being limited to such specific examples. It can be implemented with various changes within the range.
[0037]
【The invention's effect】
According to the present invention, it is possible to inspect a memory element in an actual operating environment of a non-standard memory element with a non-standard or custom-type memory element mounted on a standard inspection board. Accordingly, it is possible to reduce the cost and procedure required for mounting and inspecting the non-standard memory device, increase the reliability of the non-standard memory device, and increase the productivity of the inspection process for the non-standard memory device. it can.
[Brief description of the drawings]
FIG. 1 is a schematic view showing a conventional process for inspecting a semiconductor element.
FIG. 2 is a schematic cross-sectional view showing an inspection system according to an embodiment of the present invention.
FIG. 3 is an exploded perspective view illustrating an interface board according to an embodiment of the present invention.
FIG. 4 is a block diagram illustrating a pin matching circuit of an interface board according to an embodiment of the present invention.
FIG. 5 is a block diagram illustrating a clock inverting circuit of an interface board according to an embodiment of the present invention.
FIG. 6 is a waveform diagram showing an output signal of a clock inverting circuit according to one embodiment of the present invention.
FIG. 7 is a plan view showing an inspection substrate according to an embodiment of the present invention.
FIG. 8 is a schematic cross-sectional view showing an inspection system according to another embodiment of the present invention.
FIG. 9 is a schematic cross-sectional view showing an inspection system according to another embodiment of the present invention.
[Explanation of symbols]
50 Non-standard memory device 100 Interface board 102 First face 104 Second face 110 First socket 120 Second socket 130 Connection board 140 Socket 150 Support material 170 Inspection board 200 Pin matching circuit 230 Clock inversion circuit 240, 250 First, first 2-resistance circuit 232 Input terminals 234, 236 First and second output terminals 300, 400 Mounting inspection system

Claims (31)

An interface board for testing non-standard memory devices in an actual operating environment,
A circuit board having a first surface, a second surface and a circuit wiring layer;
A first socket formed on the first surface of the circuit board for mounting a non-standard memory device and electrically connecting the non-standard memory device and the circuit wiring layer;
A second socket formed on the second surface of the circuit board and electrically connecting the circuit wiring layer and a standard inspection board;
A pin matching circuit formed in the circuit wiring layer and configured to match a standard pin configuration of the standard test board with a non-standard pin configuration of the non-standard memory device;
A clock inverting circuit that is formed in the circuit wiring layer and that continuously or selectively operates two clock signal pins of the non-standard pin configuration with respect to one clock signal pin of the standard pin configuration;
An interface board comprising: The pin matching circuit includes a first matching unit that assigns the control signal and the address signal of the standard pin configuration to the control signal and the address signal of the non-standard pin configuration to correspond one-to-one. 2. The interface board according to 1. The pin matching circuit includes a second matching unit that selectively assigns the data input / output signals of the standard pin configuration to the data input / output signals of the non-standard pin configuration and continuously interleaves the links. The interface board according to claim 2 . 2. The interface board according to claim 1 , wherein the circuit wiring layer includes a power supply layer, a ground layer, and at least one signal layer that is electrically insulated from each other and has a multilayer structure . The interface board according to claim 1, wherein the first socket is formed in a form suitable for a board-type product in which the non-standard memory device is used . The interface board according to claim 1, wherein the first socket has a groove formed with a connection pin that can be temporarily connected to the non-standard memory device. The clock inverting circuit includes an input terminal coupled to the clock signal pin having the standard pin configuration, a first output terminal coupled to the first clock signal pin and the second clock signal pin having the non-standard pin configuration, and a first output terminal 3. The interface board according to claim 2 , further comprising two output terminals and a first resistance circuit and a second resistance circuit connected in parallel between the power supply terminal and the ground terminal . The first resistor circuit includes a first resistor connected between the input terminal and the power supply terminal, and a second resistor connected between the input terminal and the ground terminal,
The second resistance circuit includes a third resistor connected between the second output terminal and the power supply terminal, and a fourth resistor connected between the second output terminal and the ground terminal.
The interface board according to claim 7 , wherein the first output terminal is directly connected to the input terminal . The first resistor and the third resistor have the same resistance value, the second resistor and the fourth resistor have the same resistance value, and the first resistor has a smaller resistance value than the second resistor. 9. The interface board according to claim 8, wherein 2. The interface board according to claim 1 , wherein the non-standard memory device is a 200-pin memory module, and the standard test board is a system motherboard for mounting a 168-pin memory module . When the non-standard memory device is a PC100 device, only one clock signal pin having the non-standard pin configuration operates. When the non-standard memory device is a PC133 device, two clocks having the non-standard pin configuration are operated. The interface board according to claim 1, wherein the signal pins operate simultaneously . An inspection system comprising a standard inspection board having a plurality of parts for providing an actual inspection environment for a non-standard memory device, and an interface board, and inspecting the non-standard memory element in an actual operating environment,
  The interface board includes a circuit board having a first surface, a second surface, and a circuit wiring layer, and a non-standard memory element formed on the first surface of the circuit board, and the non-standard memory element and the circuit wiring. A first socket that electrically connects a layer, a second socket that is formed on the second surface of the circuit board, and that electrically connects the circuit wiring layer and the standard inspection board; and the circuit wiring layer A pin matching circuit formed on the circuit wiring layer and configured to match a standard pin configuration of the standard test board with a non-standard pin configuration of the non-standard memory device, and for one clock signal pin of the standard pin configuration And a clock inverting circuit that selectively or simultaneously operates the two clock signal pins having the non-standard pin configuration. The inspection system according to claim 12, wherein the interface board is mounted on a surface on which a plurality of components of the standard inspection board are formed. The inspection system according to claim 12 , wherein the interface board is mounted on a surface opposite to a surface on which a plurality of components of the standard inspection board are formed . The pin matching circuit includes a first matching unit that assigns the control signal and the address signal of the standard pin configuration to the control signal and the address signal of the non-standard pin configuration, respectively, and a data input of the standard pin configuration. The inspection system according to claim 12 , further comprising: a second matching unit that selectively assigns output signals to the data input / output signals of the non-standard pin configuration and continuously interleaves links . The clock inverting circuit includes an input terminal coupled to the clock signal pin having the standard pin configuration, a first output terminal coupled to the first clock signal pin and the second clock signal pin having the non-standard pin configuration, and a first output terminal The inspection system according to claim 12 , further comprising two output terminals, and a first resistance circuit and a second resistance circuit connected in parallel between the power supply terminal and the ground terminal . The first resistor circuit includes a first resistor connected between the input terminal and the power supply terminal, and a second resistor connected between the input terminal and the ground terminal,
The second resistance circuit includes a third resistor connected between the second output terminal and the power supply terminal, and a fourth resistor connected between the second output terminal and the ground terminal.
The first output terminal is directly connected to the input terminal;
The first resistor and the third resistor have the same resistance value, the second resistor and the fourth resistor have the same resistance value, and the first resistor has a smaller resistance value than the second resistor. The inspection system according to claim 16, which is characterized by: 13. The inspection system according to claim 12 , wherein the non-standard memory device is a 200-pin memory module, and the standard inspection board is a system motherboard for mounting a 168-pin memory module . An inspection system for inspecting non-standard memory devices in an actual operating environment,
  An interface board having a first surface, a second surface and a pin matching circuit;
  A socket formed on the first surface and coupling a non-standard memory device to the pin matching circuit;
  The inspection system, wherein the second surface is configured to couple the pin matching circuit with a standard pin configuration. The inspection system according to claim 19 , further comprising an inspection board mounted directly on the second surface of the interface board . The socket is a first socket;
The inspection system of claim 19 , further comprising a second socket formed on the second surface of the interface board and coupling the pin matching circuit to the inspection board . The inspection system according to claim 21, further comprising an inspection board coupled to the second socket . The inspection system according to claim 21, further comprising a connection substrate coupled between the second socket and the inspection substrate . 24. The inspection system according to claim 23, wherein the inspection board includes a third socket configured to receive the connection board . The inspection system according to claim 23, further comprising a support member configured to affix the interface substrate to the inspection substrate . The inspection system according to claim 19 , wherein the interface board includes a clock inverting circuit that operates two clock signal pins having a non-standard pin configuration with respect to one clock signal pin having the standard pin configuration . The inspection system according to claim 19 , wherein the pin matching circuit includes a first matching unit that makes a one-to-one correspondence between signals of the standard pin configuration and the non-standard pin configuration . 28. The inspection system according to claim 27 , wherein the pin matching circuit includes a second matching unit that selectively assigns the standard pin configuration signal to the non-standard pin configuration signal . An inspection method for inspecting a non-standard memory device having a non-standard pin configuration in an actual operating environment,
The non-standard memory element is coupled to the matching circuit of the interface board through a socket formed on the first surface of the interface board, and the matching circuit is connected to the inspection board through the second surface of the interface board. Combining the non-standard pin configuration of the non-standard memory device with the standard pin configuration of the test board;
  Activating the inspection substrate;
  The inspection method characterized by including. 30. The inspection method according to claim 29, wherein the interface board is coupled to the inspection board by a connection board . 30. The inspection method according to claim 29, wherein the interface board is directly mounted on the inspection board.

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