KR100576176B1 - Apparatus and Method for Memory module test - Google Patents

Abstract

Disclosed are a test apparatus and a method for testing a semiconductor memory device in a mounted state. a first slot into which a memory module to be measured having n (2 ≦ n) chip select terminals is inserted; one or more second slots into which a dummy memory module having only serial nonvolatile memory is inserted, m (1 ≦ m A tester for generating <n) chip select signals and dividing the memory area of the memory module under test by testing, the first slot and the second slots are mounted, and the nm chip select pins of the first slot are at least one second. And a motherboard connected to the m chip select pins of the slots, respectively. By dividing the memory area of the memory module under measurement by the number of slots used in each slot, it is possible to test a memory device having a plurality of ranks.

Description

Apparatus and Method for Memory module test             

1 is a diagram showing the structure of a general DIMM.

2 is a diagram illustrating a test board of a semiconductor memory module according to a first embodiment of the present invention.

3 is a diagram illustrating a test board of a semiconductor memory module according to a second embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

120, 210, 310: Motherboard

140, 220, 230, 360, 370: slot

160: DIMM 180: DRAM

240: dummy memory module 250, 330: ROM

280, 380: memory module for measurement 320: interface printed circuit board

The present invention relates to a test of a semiconductor memory module, and more particularly, to an apparatus and a method for testing a memory module in a mounted state.

In general, when memory is actually used, it is used as a module. A module refers to a functional unit having independent functions as a part of a system. A memory module refers to a package device such as a plurality of semiconductor elements attached to a printed circuit board and connected to a panel by a plurality of contact terminals.

In the semiconductor memory module, each module is divided into a single in-line memory module (SIMM) and a dual in-line memory module (DIMM) according to a data bus and a data transmission method of the processor.

SIMM has 30-pin modules with 8-bit bandwidth and 72-pin modules with 32-bit bandwidth. Lately, the use of 168-pin DIMMs has been increasing, because 72-pin SIMMs support 32-bit bandwidth because of the Pentium's 64-bit bandwidth, two SIMMs must be used. In other words, since two 72-pin SIMMs have been formed to form 64-bit bandwidth, the use of DIMMs is increasing.

Because DIMMs have 64-bit bandwidth, they can improve overall system speed by avoiding delays when DIMMs work with the central prosessing unit (CPU). In addition, since the DIMM slot used to attach the memory module on the mother board occupies only half the space compared to the SIMM slot, it is used in various electronic products in the trend of small size and light weight. This is because DIMMs use both sides of the PCB and SIMM uses only one side. The SIMM is also intended to generate electrical contact on both sides, but it generates the same signal with one pin. DIMMs, on the other hand, are electrically separated on both sides of the PCB and exchange their data.

In general, in order to check the characteristics and reliability of the internal circuit after the assembly process of the semiconductor memory, the assembled semiconductor element is mounted in a slot, and then tested using specialized equipment for expensive semiconductor memory test. However, the system for testing the semiconductor memory has a disadvantage in that the cost of one semiconductor memory test increases. In addition, since the test is not performed under the conditions in which the semiconductor memory is actually installed and used, the test is not properly performed on the characteristics under the conditions such as noise generated in the actual computer motherboard, and thus the accuracy of the test is lowered. And so on.

Due to these problems, a test method for increasing the reliability of a memory module by using a test in a state in which a semiconductor memory is mounted on an actually used motherboard has been widely used.

FIG. 1 is a diagram illustrating a DIMM having a two rank structure generally used.

Referring to FIG. 1, the slot 140 on which the DIMM 160 for the DRAM 180 is mounted is mounted on the motherboard 120. DRAM elements in one DIMM 160 are divided into two ranks. This rank is mainly divided by a chip select pin (/ CS [i], i≥0 integer) into which the chip select signal is input. One / CS [i] controls one rank. For example, a two rank DIMM requires two chip select signals. Accordingly, two / CS [0 ~ 1] pins are formed in the slot 140 to support this.

Currently commonly used modules are composed of one rank or two ranks. However, the module with the largest data capacity has a data capacity of Giga Bytes. Therefore, some DIMMs use modules that increase the number of ranks of the module to 4 ranks in order to have a large data capacity while maintaining the existing configuration. However, current test equipment for testing memory modules only supports two / CS [0 ~ 1] for each slot. Therefore, to test a 4 rank module in a mounted state, a device supporting / CS [0 ~ 3] is required. However, since the development of such equipment is still in its infancy, there is a need for a method of testing a memory module in a mounted state using existing equipment.

An object of the present invention for solving the above problems is to test a memory module composed of a plurality of ranks by connecting some of / CS [i] of slots in which the semiconductor memory module is mounted to / CS [i] of another slot. To provide a test apparatus and method that can be.

The present invention for achieving the above object is disclosed a test apparatus and method that can test a semiconductor memory device in a mounted state. a first slot into which a memory module to be measured having n (2 ≦ n) chip select terminals is inserted; one or more second slots into which a dummy memory module having only serial nonvolatile memory is inserted, m (1 ≦ m A tester for generating <n) chip select signals and dividing the memory area of the memory module under test by testing, the first slot and the second slots are mounted, and the nm chip select pins of the first slot are at least one second. And a motherboard connected to the m chip select pins of the slots, respectively.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

 FIG. 2 is a diagram illustrating a test board of a semiconductor memory module according to a first embodiment of the present invention.

Referring to FIG. 2, a test board of a semiconductor memory module according to the present invention includes a mother board 210, a first slot 260, a second slot 270, a module printed circuit board 240, and a serial nonvolatile memory 250. It is composed of

For example, the serial nonvolatile memory 250 uses EEPROM.

The first slot 220 includes four / CS [0 ~ 3], and the / CS [0 ~ 3] is mounted so as to correspond to the chip select terminals of the memory module 280 to be measured, respectively. 210 is mounted. The second slot 230 may be formed to include one or more / CS [i]. In the present invention, a slot including / CS [0 ~ 3] is basically used. In the second slot 230, a dummy memory module 240 in which only the Y pyrom 250 is mounted is mounted. Y pyrom 250 is mounted for testing under the same condition as the actual mounting environment. Also, / CS [2] and / CS [3] of the first slot 220 are connected to / CS0 and / CS [1] when the second slot 270 provides / CS [0 ~ 1], respectively. Form into a structure. In addition, when the second slot 270 provides only / CS [0], a slot must be added to test / CS [0 ~ 3] mounted on the first slot 260. That is, since the tester for testing the current memory module supports only / CS [0 ~ 1] for each slot, it is impossible to test the 4-rank structure of the memory module 280 mounted in the first slot 220. Therefore, by connecting / CS [i] of the second slot 230 to / CS [i], which cannot be tested in the first slot 220, a 4 rank memory module can be tested.

When the memory module is tested in the form shown in FIG. 2, 1/2 of the total bias of the memory module 280 to be measured having four / CS [i] mounted in the first slot 220. Fill in with Similarly, the dummy memory module 240 of the second slot 270 is also written at 1/2 of the total bias of the memory module 280 to be measured. When the bias is written into the memory module 280 and the dummy memory module 240 to be measured by the above method, the tester recognizes that the half of the total bias module is mounted in each slot. The entire memory module 280 may be tested.

3 is a diagram illustrating a test apparatus of a semiconductor memory module according to a second embodiment of the present invention.

Referring to FIG. 3, a test board of a semiconductor memory module according to the present invention includes a motherboard 310, a third slot 360, a second slot 370, an interface printed circuit board 340, and a serial nonvolatile memory 250. It is composed of

For example, the serial nonvolatile memory 330 uses EEPROM. In addition, the serial nonvolatile memory 250 is formed in a controllable structure through a control means.

The test board of the memory module illustrated in FIG. 3 is a test board for testing a memory module using a motherboard 310 mounted on various devices in an inverted form currently being applied in mass production. Since the motherboard 310 is reversed, it is difficult to directly mount the memory module 380 for measurement. Accordingly, an interface printed circuit board 320 equipped with a third slot having the same structure as that of the first slot is provided for mounting the memory module under measurement. In the manufacturing of the interface printed circuit board 320, / CS [0] and / CS [1] of the second slot 370 mounted on the motherboard 310 and / CS [2] of the third slot 360 It is formed into a structure connected to / CS [3]. In addition, the EPI 330 is mounted on the interface printed circuit board 320. The Y pyrom 330 is mounted to perform the same role as the Y pyrom 250 mounted on the dummy memory module 240 shown in FIG. 2. That is, the Y pyrom 330 is mounted in connection with the second slot for the purpose of the tester to recognize that the memory module is mounted in the second slot. The chip select pins of the respective slots mounted on the interface printed circuit board 320 and the motherboard 310 are connected to correspond to each other. Therefore, the semiconductor memory device having four / CS [i] can be tested without mounting the dummy memory module 240 shown in FIG. 2 in the second slot 370. In addition, the Y pyrom 330 may be connected to a control means to control the connection with the second slot. In one example, the control means uses various switches. The Y pyrom 330 may be connected to the second slot 370 according to the on / off operation of the switch. That is, the interface circuit board 340 and the second slot 370 may be connected to each other to test a memory module having four chip select terminals by turning on a switch connected to the Y pyrom 330. When the switch of the switch 330 is turned on, the interface circuit board 340 and the second slot 370 are blocked from each other, so that the tester recognizes only the memory module mounted in the first slot 360. You can test a memory module with 1]. In other words, by appropriately adjusting the control means, it is possible to test using memory modules having different / CS [i] in parallel.

Although described above with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below I can understand that you can.

According to the present invention as described above, when testing a memory module having two or more chip select terminals, it is possible to test the memory module using an existing tester supporting one or two chip select signals.

In addition, by selectively connecting the test system and the slot other than the slot in which the test module is mounted, it is possible to test the module having a 1 rank or 2 rank structure.

Claims (4)

The m (1 ≦ m <n) first chip select terminals of the memory module under measurement having n (2 ≦ n) chip select terminals are connected to m chip select pins, respectively. The remaining second chip select terminals may include a first slot inserted to be connected to the remaining chip select pins, respectively; One or more second slots, each of which includes a dummy memory module having only a serial nonvolatile memory mounted thereon for testing under the same condition as the actual mounting environment; A motherboard mounted with the first slot and the second slots, the remaining chip select pins of the first slot being connected to m chip select pins of the at least one second slots, respectively; And and a tester for generating m chip selection signals and dividing and testing memory areas of the memory module under measurement by the number of the first slot and the at least one second slot through the motherboard. Memory module test system. The m (1 ≦ m <n) first chip select terminals of the memory module under measurement having n (2 ≦ n) chip select terminals are connected to m chip select pins, respectively. The remaining second chip select terminals may include a third slot inserted to be connected to the remaining chip select pins, respectively; The third slot and the same number of serial nonvolatile memories as the at least one or more second slots, and the remaining chip select pins of the third slot are provided in m chip select pins of the at least one or more second slots. An interface printed circuit board each connected, the serial nonvolatile memories respectively connected with corresponding second slots, each serial nonvolatile memories being connected to a control means; A mother board on which a first slot and at least one second slot are mounted on a first surface, and the interface printed circuit board is mounted on a second surface facing the first surface; And a tester for generating m chip select signals and dividing and testing the memory area of the memory module under measurement by the number of the third slot and the at least one second slot through the motherboard and the interface printed circuit board; Memory module test system, characterized in that provided. Providing a motherboard in which the remaining chip select pins except for m of the n chip select pins of the first slot are respectively connected to the m chip select pins of the at least one or more second slots; The at least one dummy memory module having only the serial nonvolatile memory mounted therein for inserting the memory module under measurement having n chip select terminals into the first slot and being tested under the same conditions as the actual mounting environment. Inserting each into two slots; And And dividing and testing a memory area of the memory module under measurement by the number of the first slot and the at least one second slot through the motherboard. Providing a motherboard having a first slot and a second slot on a first surface; Equipped with a third slot and the same number of serial nonvolatile memories as the at least one second slot, wherein the remaining chip select pins of the third slot are connected to m chip select pins of the at least one second slots, respectively. Providing an interface printed circuit board, each of the serial nonvolatile memories connected to corresponding second slots; Coupling the interface printed circuit board to a corresponding position on a second surface facing the first surface of the motherboard such that the second slots of the motherboard and the third slot of the interface printed circuit board are connected to each other; inserting a memory module for measurement having n chip select terminals into the third slot; Selectively activating the serial nonvolatile memories by control means; And generating m chip selection signals and dividing and testing the memory area of the memory module under measurement by the number of the third slot and the at least one second slot through the motherboard and the interface printed circuit board; Memory module test method, characterized in that provided.

Images