JP2003234350A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enhance pressure resistance by increasing the threshold energy of impact ionization in a semiconductor device which has at least one p-n junction which is composed on a GaAs semiconductor substrate, for example, a heterojunction bipolar transistor (HBT). <P>SOLUTION: The direction (arrow 43) that is the main direction of travel electron for electrons in an n-type layer, that is, a collector layer 33, is set so as to substantially be the direction <111> of a GaAs semiconductor substrate 31, and in an HBT30, a collector breakdown voltage (collector withstanding voltage) is raised up. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having at least one pn junction formed on a GaAs semiconductor substrate and a method for manufacturing the same, and more particularly to increasing a reverse breakdown voltage in the semiconductor device. Related to the improvement of.

[0002]

2. Description of the Related Art Heterojunction bipolar transistors (H
Since BT) can realize high-speed and highly efficient operation, it is used in, for example, a power amplifier of a mobile phone. Since the power amplifier needs to output a large amount of power, it is desirable that the collector breakdown voltage is high.

Conventionally, such an HBT has been manufactured through the steps shown in FIG.

First, as shown in FIG. 8A, {00
A semi-insulating GaAs semiconductor substrate 1 whose main surface is the 1} plane is prepared. The {001} plane means any of crystallographically equivalent (001) plane, (010) plane and (100) plane, and is used to generically refer to these three planes.

Next, as shown in FIG.
A collector contact layer 2 made of n ⁺ -GaAs is formed on the semiconductor substrate 1 by a crystal growth method such as MOCVD.
A collector layer 3 made of n-GaAs, a base layer 4 made of p ⁺ -GaAs, an emitter layer 5 made of n-InGaP, and an emitter contact layer 6 made of n ⁺ -GaAs are sequentially formed.

Next, as shown in FIG. 8C, wet etching or dry etching is applied to give a mesa shape to the emitter contact layer 6 and the emitter layer 5, whereby the emitter mesa 7 is formed and the base layer is formed. 4 and the collector layer 3 are provided with a mesa shape, thereby forming a base mesa 8, and further, the collector contact layer 2 and a part of the GaAs semiconductor substrate 1 are provided with a mesa shape, thereby forming a collector mesa 9. The collector mesa 9 is also for separating the elements.

Next, as shown in FIG. 8 (4), the emitter electrode 10 is formed so as to be connected to the emitter contact layer 6.
Is formed, a base electrode 11 is formed so as to be connected to the base layer 4, and a collector electrode 12 is further formed so as to be connected to the collector contact layer 2.

In this way, the HBT 13 is
It is formed on the semiconductor substrate 1.

Such an HBT 13 is often used in a grounded-emitter system. When the emitter voltage is Ve, the base voltage is Vb, and the collector voltage is Vc, in the grounded-emitter system, a bias is applied so that Ve = 0 and 0 <Vb <Vc. At this time, the emitter
The base junction is biased in the forward direction and the base-collector junction is biased in the reverse direction.

Under such a bias condition, since the collector contact layer 2 has a low resistance, the potential of the collector contact layer 2 becomes substantially uniform, and most of the electrons in the collector layer 3 of the HBT 13 are shown in FIG. As indicated by the arrow 14, from the emitter layer 5 to <00 of the GaAs semiconductor substrate 1.
It travels in the 1> direction and is absorbed by the collector contact layer 2.

[0011]

Generally, in HBT,
When the voltage (Vc-Vb) applied between the base and the collector becomes high, the electric field in the collector layer becomes high, and the high electric field accelerates the electrons in the collector layer to be in a high energy state. Electrons in a high energy state equal to or higher than the threshold energy generate electron-hole pairs by giving the energy to the atoms constituting the semiconductor (impact ionization). The newly generated electrons are also accelerated by the electric field to obtain energy and further generate electron-hole pairs, so that the carriers multiply like an avalanche and reach the breakdown.

As shown in FIG. 9, in the conventional HBT 13, the electrons in the collector layer 3 are
Since it travels in the <001> direction, there is a problem in that the threshold value of energy at which impact ionization occurs is relatively small, and therefore breakdown occurs at a relatively low base-collector voltage.

The same problem can be encountered not only in the HBT 13 described above, but also in other semiconductor devices having at least one pn junction formed on a GaAs semiconductor substrate, such as a diode.

FIG. 10 shows a conventional pn junction diode 1
7 shows a sectional structure of No. 7.

Referring to FIG. 10, the diode 17 is
It is formed on a deterministic insulating GaAs semiconductor substrate 18 whose main surface is the {001} plane.

On the GaAs semiconductor substrate 18, n ⁺ -G
a lower contact layer 19 made of aAs, an n-type layer 20 made of n-GaAs, a p-type layer 21 made of p-GaAs,
And an upper contact layer 22 made of p ⁺ -GaAs are sequentially formed.

Further, etching is applied to give the upper contact layer 22, the p-type layer 21, and the n-type layer 20 a mesa shape, thereby forming a pn junction mesa 23, and a lower contact layer. 19 and a part of the GaAs semiconductor substrate 18 are provided with a mesa shape, whereby an element isolation mesa 24 is formed.

An n-type ohmic electrode 25 is formed so as to be connected to the lower contact layer 19, and a p-type ohmic electrode 26 is formed so as to be connected to the upper contact layer 22.

Also in such a pn junction diode 17, electrons mainly travel in the direction of arrow 27, that is, in the <001> direction of the GaAs semiconductor substrate 18,
Similar to the case of the HBT 13 described above, there is a problem that the threshold value of energy at which impact ionization occurs is relatively small and therefore the breakdown voltage is also relatively low.

Therefore, an object of the present invention is to provide a semiconductor device and a method of manufacturing the same which can solve the above-mentioned problems.

[0021]

[Means for Solving the Problems] The threshold energy of electron impact ionization has a crystal direction dependence,
The <111> direction is the largest, and about 1.
The present invention has been completed based on the finding that the number is five times.

The present invention is first directed to a semiconductor device having at least one pn junction formed on a GaAs semiconductor substrate, and in order to solve the above-mentioned technical problem, an n-type layer Is characterized in that the main traveling direction of the electrons is substantially the <111> direction of the semiconductor substrate.

Thus, impact ionization can be suppressed by making the main traveling direction of electrons substantially the <111> direction, and when the present invention is applied to, for example, a bipolar transistor, an n-type layer is used. The collector breakdown voltage provided by a certain collector layer can be increased.

The present invention has the following two typical embodiments.

In the first embodiment, as the semiconductor substrate,
The one having the {111} plane as the principal plane is used. In this case, the semiconductor substrate <11
The 1> direction is a direction perpendicular to the main surface of the semiconductor substrate.

In the second embodiment, as the semiconductor substrate,
The one whose main surface is the {001} plane is used. In this case, the semiconductor substrate is provided with a trapezoidal convex portion serving as a current impermeable region, and the <111> direction of the semiconductor substrate, which is the main traveling direction of electrons, is the direction along the slope of the convex portion.

When the second embodiment described above is adopted in a bipolar transistor, the n-type layer is a collector layer, the collector layer is formed under the emitter mesa, and the current impermeable region is located in the collector layer. To be done.

When the second embodiment is applied to a diode, an n-type layer is formed under the p-type layer mesa, in which the above-mentioned current interruption region is located.

The present invention is also directed to a method for manufacturing a semiconductor device as described above.

A method of manufacturing a semiconductor device according to the present invention is
In order to obtain the semiconductor device according to the first embodiment described above, a step of preparing a GaAs semiconductor substrate having a {111} plane as a main surface and a main traveling direction of electrons in the n-type layer are So that it is substantially in the <111> direction of the semiconductor substrate,
And a step of forming a semiconductor device having at least one pn junction on a semiconductor substrate.

A method of manufacturing a semiconductor device according to the present invention is
When applied to obtain the semiconductor device according to the second embodiment described above, GaA having the {001} plane as the main surface is used.
s The step of preparing a semiconductor substrate and <11
1> The step of providing a trapezoidal convex portion that becomes a current impermeable region so that the direction is along the slope, and the main traveling direction of electrons in the n-type layer is substantially the <111> direction of the semiconductor substrate. So that a semiconductor device having at least one pn junction is formed on the semiconductor substrate.

[0032]

BEST MODE FOR CARRYING OUT THE INVENTION In order to explain the present invention more specifically, as a first embodiment, an embodiment relating to the bipolar transistor according to the first embodiment described above, and a second embodiment
Of the diode according to the first embodiment, an embodiment of the bipolar transistor according to the second embodiment described above as a third embodiment, and a second embodiment of the fourth embodiment.
Each of the embodiments related to the diode according to the embodiment will be described.

1 and 2 are for explaining the first embodiment. Here, FIG. 1 shows a heterojunction bipolar transistor (HBT) according to the first embodiment.
It is sectional drawing which shows the typical process implemented in order to manufacture 30, and FIG. 2 is sectional drawing which shows the obtained HBT30 with the main traveling direction of an electron.

In order to manufacture such an HBT 30, first, as shown in FIG. 1A, a semi-insulating GaAs semiconductor substrate 31 having a {111} plane as a main surface is prepared. The <111> direction of the GaAs semiconductor substrate 31 is a direction perpendicular to the main surface of the GaAs semiconductor substrate 31, as shown in FIG.

As described above, the GaAs semiconductor substrate 31 having the {111} plane as the main surface is used, which is a big difference from the above-described conventional manufacturing method shown in FIG. Subsequent steps shown in FIGS. 1 (2) to (4) are substantially the same as the steps shown in FIG. 8 (2) to (4).

That is, next, as shown in FIG. 1B, a collector contact layer 32 made of n ⁺ -GaAs and n-GaAs are formed on the GaAs semiconductor substrate 31 by a crystal growth method such as MOCVD. Collector layer 3
3, p ⁺ -GaAs base layer 34, n-InG
An emitter layer 35 made of aP and an emitter contact layer 36 made of n ⁺ -GaAs are sequentially formed.

Next, as shown in FIG. 1C, wet etching or dry etching is applied to give a mesa shape to the emitter contact layer 36 and the emitter layer 35, thereby forming an emitter mesa 37,
The base layer 34 and the collector layer 33 are provided with a mesa shape, whereby a base mesa 38 is formed, and further,
Collector contact layer 32 and GaAs semiconductor substrate 3
A part of 1 is provided with a mesa shape, thereby forming a collector mesa 39 for separating elements.

Next, as shown in FIG. 1 (4), the emitter electrode 4 is connected to the emitter contact layer 36.
0 is formed, a base electrode 41 is formed so as to be connected to the base layer 34, and a collector electrode 42 is formed so as to be connected to the collector contact layer 32.

As described above, G having the {111} plane as the principal plane
When the HBT 30 formed on the aAs semiconductor substrate 31 is used in the grounded-emitter system, a large number of electrons injected from the emitter layer 35 and passing through the base layer 34 are generated by the collector layer as shown by an arrow 43 in FIG. It travels substantially through 33 in the <111> direction of GaAs semiconductor substrate 31 and is absorbed by collector contact layer 32. Therefore, as compared with the case of the HBT 13 shown in FIG. 9, the threshold energy at which impact ionization occurs becomes higher and the collector breakdown voltage can be increased.

FIG. 3 is a sectional view showing a pn junction diode 47 according to the second embodiment of the present invention together with the main traveling direction of electrons.

Referring to FIG. 3, a pn junction diode 4
7 is the pn junction diode 17 shown in FIG.
Different from the above case, it is characterized in that it is formed on a semi-insulating GaAs semiconductor substrate 48 having a {111} plane as a main surface. <11 of such a GaAs semiconductor substrate 48
The 1> direction is a direction perpendicular to the main surface of the GaAs semiconductor substrate 48.

On the GaAs semiconductor substrate 48, the MOCV is substantially the same as the case of the diode 17 shown in FIG.
The lower contact layer 49 made of n ⁺ -GaAs and the n-type layer 5 made of n-GaAs are formed by a crystal growth method such as D method.
0, p-type layer 51 made of p-GaAs, and p ⁺ -G
The upper contact layer 52 made of aAs is sequentially formed.

Then, wet etching or dry etching is applied to give the upper contact layer 52, the p-type layer 51 and the n-type layer 50 a mesa shape, thereby forming a pn junction mesa 53, and A mesa shape is given to a part of the lower contact layer 49 and the GaAs semiconductor substrate 48, whereby an element isolation mesa 54 is formed.

Next, an n-type ohmic electrode 55 is formed so as to be connected to the lower contact layer 49, and a p-type ohmic electrode 56 is formed so as to be connected to the upper contact layer 52.

As described above, G having the {111} plane as the principal plane
In the pn junction diode 47 formed on the aAs semiconductor substrate 48, as shown by an arrow 57, the main electrons from the upper contact layer 52 to the lower contact layer 49 through the p-type layer 51 and the n-type layer 50. Since the traveling direction is substantially the <111> direction of the GaAs semiconductor substrate 48,
As compared with the case of the diode 17 shown in FIG. 10, the threshold energy at which impact ionization occurs can be increased, and thus the breakdown voltage can be increased.

FIG. 4 is a sectional view sequentially showing a typical process carried out for manufacturing the HBT 60 according to the third embodiment of the present invention, and FIG. 5 is the resulting HBT 60.
FIG. 3 is a cross-sectional view showing the above, together with a main traveling direction of electrons.

To manufacture the HBT 60, first, referring to FIG.
As shown in (1), the semi-insulating GaAs semiconductor substrate 61
Is prepared. This GaAs semiconductor substrate 61 is used for manufacturing the conventional HBT 13 shown in FIG.
Similar to the case of the aAs semiconductor substrate 1, the {001} plane is the main plane. The {001} plane is, as described above,
Any of crystallographically equivalent (001) plane, (010) plane and (100) plane may be used.

Next, as shown in FIG. 4A, G
A mask material 62 is formed on the aAs semiconductor substrate 61. The mask material 62 serves as a mask in the etching and crystal growth steps described later, and is formed with a thin film made of a stable material in these steps. Examples of the material for the mask material 62 include SiN _x and SiO _2.
Is preferably used. Further, the patterning of the mask material 62 is set so that the upper side of the trapezoid formed in the etching step described later has a desired size, and has the same size as an emitter mesa formed in a later step. To be done.

Next, as shown in FIG.
The semiconductor substrate 61 is etched. By this etching, the trapezoidal protrusions 6 are formed on the GaAs semiconductor substrate 61.
3 is formed. The etching mode for forming the protrusion 63 is selected so that the {211} plane along the <111> direction is exposed on the slope 64 of the protrusion 63. Therefore, the <111> direction of the GaAs semiconductor substrate 61 is as shown in FIG.
As shown in, the direction is along the slope 64 of the convex portion 63. The convex portion 63 is a current non-conductive area, as will be apparent from the description below.

Next, as shown in FIG. 4C, the MOCV
By a crystal growth method such as D method, a collector contact layer 65 made of n ⁺ -GaAs and a first collector layer 66 made of n-GaAs are formed. The etching depth in the above-described etching step is adjusted to be approximately the same as the total thickness of the collector contact layer 65 and the first collector layer 66. The crystal growth for forming the collector contact layer 65 and the first collector layer 66 is performed by the side surface of the convex portion 63 and the mask material 62.
Surface ({001}
(Surface) is performed under the condition such that it only arises. Therefore, the collector contact layer 65 and the first collector layer 66 grow in the manner as shown in FIG.

Next, after the mask material 62 is removed, FIG.
As shown in (4), the second collector layer 67 made of n-GaAs, the base layer 68 made of p ⁺ -GaAs, n
-InGaP emitter layer 69 and n ⁺ -G
The emitter contact layer 70 made of aAs is MOCV
They are sequentially formed by a crystal growth method such as D method.

Next, as shown in FIG. 4 (5), wet etching or dry etching is applied to give a mesa shape to the emitter contact layer 70 and the emitter layer 69, thereby forming an emitter mesa 71,
Base layer 68 and first and second collector layers 66
And 67 are provided with a mesa shape, thereby forming a base mesa 72, and a collector contact layer 6
5 and a part of the GaAs semiconductor substrate 61 are given a mesa shape, whereby a collector mesa 7 for element isolation is formed.
3 is formed.

Next, as shown in FIG. 4 (6), the emitter electrode 7 is formed so as to be connected to the emitter contact layer 70.
4 is formed, a base electrode 75 is formed so as to be connected to the base layer 68, and a collector electrode 76 is formed so as to be connected to the collector contact layer 65.

In this way, the HBT 60 becomes {00
It is formed on a GaAs semiconductor substrate 61 whose main surface is the 1} plane.

In such an HBT 60, the protrusion 63 is formed in the collector layers 66 and 67 below the emitter mesa 71.
Since no current flows through this convex portion 63, the main traveling path of electrons is formed along the slope 64 of the trapezoidal convex portion 63 as shown by the arrow 77 in FIG. The main traveling direction of the GaAs semiconductor substrate 61 is substantially
<111> direction. Therefore, compared with the HBT 13 shown in FIG. 9 described above, the threshold energy at which impact ionization occurs becomes higher, and the collector breakdown voltage can be increased.

FIG. 6 is a sectional view sequentially showing a typical process performed for manufacturing a pn junction diode 80 according to the fourth embodiment of the present invention, and FIG. 7 is obtained. It is sectional drawing which shows the diode 80 with the main traveling direction of an electron.

In order to manufacture the pn junction diode 80, first, a semi-insulating GaAs semiconductor substrate 81 is prepared. This GaAs semiconductor substrate 81 has the {001} plane as the main surface, as in the case of the diode 17 shown in the third embodiment or FIG.

Next, as shown in FIG. 6A, G
A mask material 82 is formed on the aAs semiconductor substrate 81. The mask material 82 has the same function as the mask material 62 in the third embodiment, and can be made of the same material. The patterning of the mask material 82 is set so that the upper side of the trapezoid formed in the subsequent etching step has a desired size, and the patterning is similar to that of the p-type layer mesa formed in the subsequent step. To be.

Next, as shown in FIG. 6 (2), GaAs
The semiconductor substrate 81 is etched to form a trapezoidal convex portion 83. The manner of etching for forming the convex portion 83 is the same as the case of the convex portion 63 in the above-described third embodiment.
It is chosen to expose the 1} plane. Therefore, Ga
The <111> direction of the As semiconductor substrate 81 is the direction along the slope 84 of the convex portion 83, as shown in FIG. 7.

Next, as shown in FIG. 6C, the MOCV
By the crystal growth method such as D method, the lower contact layer 85 made of n ⁺ -GaAs and the first n-type layer 86 made of n-GaAs are formed. The thickness and growth conditions of the lower contact layer 85 and the first n-type layer 86 are as follows.
This is substantially the same as the case of the collector contact layer 65 and the first collector layer 66 in the third embodiment described above.

Next, after removing the mask material 82, as shown in FIG.
As shown in (4), the second n-type layer 87 made of n-GaAs, the p-type layer 88 made of p-GaAs, and p ⁺
-The upper contact layer 89 made of GaAs is MOCV
They are sequentially formed by a crystal growth method such as D method.

Next, as shown in FIG. 6 (5), wet etching or dry etching is applied to give the upper contact layer 89 and the p-type layer 88 a mesa shape, thereby forming the p-type layer mesa 90. The second n
A mesa shape is imparted to the mold layer 87 and the first n-type layer 86, thereby forming an n-type layer mesa 91, and
A mesa shape is given to a part of the lower contact layer 85 and the GaAs semiconductor substrate 81, whereby an element isolation mesa 92 is formed.

Next, as shown in FIG. 6 (6), an n-type ohmic electrode 93 is formed so as to be connected to the lower contact layer 85, and p is formed so as to be connected to the upper contact layer 89. A type ohmic electrode 94 is formed.

In this way, the pn junction diode 8
0 is a GaAs semiconductor substrate 8 whose main surface is the {001} plane
Configured on one.

In such a diode 80, a trapezoidal convex portion 83 is located in the n-type layers 86 and 87 formed under the p-type layer mesa 90, and no current flows through this convex portion 83. As shown by an arrow 95 in FIG. 7, a main traveling path of electrons is formed along the slope 84 of the trapezoidal convex portion 83, and the main traveling direction of the electrons is substantially the GaAs semiconductor substrate 81. It becomes the <111> direction. Therefore, for example, in comparison with the conventional diode 17 shown in FIG.
The threshold energy at which impact ionization occurs is increased, and thus the breakdown voltage can be increased.

[0066]

As described above, according to the present invention, Ga
At least one pn configured on an As semiconductor substrate
In a semiconductor device having a junction, the main traveling direction of electrons in the n-type layer is substantially the <111> direction of the semiconductor substrate, so that the threshold energy at which impact ionization occurs is increased. Therefore, the breakdown voltage can be increased. Therefore, when the present invention is applied to a bipolar transistor, the collector breakdown voltage can be increased.

In the present invention, as the semiconductor substrate,
When the one having the {111} plane as the main surface is used, the <111> direction of the semiconductor substrate becomes a direction perpendicular to the main surface of the semiconductor substrate. Therefore, the n-type layer and the p-type The mold layer can be formed and requires no particular changes in the manufacturing process.

On the other hand, in the present invention, when the semiconductor substrate whose main surface is the {001} plane is used, the semiconductor substrate generally used in the conventional semiconductor device can be used as it is. Also in the manufacturing process, the semiconductor device according to the present invention can be obtained only by adding a process for providing a trapezoidal convex portion which becomes a current impermeable region on the semiconductor substrate.

[Brief description of drawings]

1A to 1D are cross-sectional views sequentially showing typical steps performed to manufacture an HBT 30 according to a first embodiment of the present invention.

FIG. 2 is an HBT3 obtained through the manufacturing process shown in FIG.
It is sectional drawing which shows 0 with the main traveling direction of an electron.

FIG. 3 is a diode 4 according to a second embodiment of the present invention.
FIG. 7 is a cross-sectional view showing 7 together with the main traveling direction of electrons.

FIG. 4 is a sectional view sequentially showing a typical process performed for manufacturing an HBT 60 according to the third embodiment of the present invention.

FIG. 5 is an HBT6 obtained through the manufacturing process shown in FIG.
It is sectional drawing which shows 0 with the main traveling direction of an electron.

FIG. 6 is a diode 8 according to a fourth embodiment of the present invention.
FIG. 7 is a cross-sectional view sequentially showing a typical process performed for manufacturing 0.

7 is a cross-sectional view showing a diode 80 obtained through the manufacturing process shown in FIG. 6 together with the main traveling direction of electrons.

FIG. 8 is a sectional view sequentially showing a typical process performed for manufacturing the conventional HBT 13 which is of interest to the present invention.

9 is an HBT1 obtained through the manufacturing process shown in FIG.
FIG. 3 is a cross-sectional view showing 3 along with a main traveling direction of electrons.

FIG. 10 is a cross-sectional view showing a conventional diode 17 which is of interest to the present invention together with the main traveling direction of electrons.

[Explanation of symbols]

30, 60 HBT 31, 48, 61, 81 Semi-insulating GaAs semiconductor substrate 32, 65 Collector contact layer 33, 66, 67 Collector layer 34, 68 Base layer 35, 69 Emitter layer 36, 70 Emitter contact layer 37, 71 Emitter mesa 38,72 Base Mesa 39,73 Collector Mesa 40,74 Emitter Electrode 41,75 Base Electrode 42,76 Collector Electrode 43,57,77,95 Arrows 47,80 Pn Junction Diodes 49,85 showing the main traveling direction of electrons Lower contact layer 50, 86, 87 n-type layer 51, 88 p-type layer 52, 89 upper contact layer 53 pn junction mesa 54, 92 element isolation mesa 55, 93 n-type ohmic electrode 56, 94 p-type ohmic electrode 63,83 Convex portion 64,84 Slope 90 p-type layer mesa 91 n-type layer mesa

Claims (8)

[Claims] 1. A semiconductor device having at least one pn junction formed on a GaAs semiconductor substrate, wherein a main traveling direction of electrons in an n-type layer is substantially equal to that of the semiconductor substrate. 111> The semiconductor device is formed so as to have the (111) direction. 2. The semiconductor device according to claim 1, wherein the semiconductor device is a bipolar transistor, and the n-type layer is a collector layer. 3. The semiconductor substrate has a {111} plane as a main surface, and a <111> direction of the semiconductor substrate is perpendicular to a main surface of the semiconductor substrate. The semiconductor device according to claim 1. 4. The semiconductor substrate has a {001} plane as a main surface, and the semiconductor substrate is provided with a trapezoidal convex portion serving as a current impermeable region.
The semiconductor device according to claim 1 or 2, wherein the 11> direction is along the slope of the convex portion. 5. The semiconductor device is a bipolar transistor, the n-type layer is a collector layer, the collector layer is formed under an emitter mesa, and the current impermeable region is located in the collector layer. Item 5. The semiconductor device according to item 4. 6. The semiconductor device is a diode, and p
The semiconductor device according to claim 4, wherein an n-type layer is formed below the type-layer mesa, and the current non-conductive region is located in the n-type layer. 7. A step of preparing a GaAs semiconductor substrate having a {111} plane as a main surface, and a main traveling direction of electrons in an n-type layer is substantially the <111> direction of the semiconductor substrate. And a step of forming a semiconductor device having at least one pn junction on the semiconductor substrate. 8. A step of preparing a GaAs semiconductor substrate having a {001} plane as a main surface, and <11
1> The step of providing a trapezoidal convex portion which becomes a current impermeable region so that the direction is along the slope, and the main traveling direction of electrons in the n-type layer is substantially the <111> direction of the semiconductor substrate. And a step of forming a semiconductor device having at least one pn junction on the semiconductor substrate.