JP2003233360A - Liquid crystal device, electro-optical device, driving circuit and method therefor, and electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the number of voltage levels of data signals and also simplify the generation processing therefor in gradation display using an MLS driving method. <P>SOLUTION: A scanning electrode driving circuit 350 selects three pieces of scanning electrodes 312 n times for one vertical scanning period. In each selection, voltage selected according to the three pieces of elements of the columns corresponding to that selection from the scanning pattern with 3 rows by n columns is applied to each scanning electrode 312. During each selection period in which the three pieces of scanning electrodes 312 are selected, a signal electrode driving circuit 250 makes a comparison between the bit string responsive to the column elements corresponding to the selection from the scanning pattern and the bit string consisting of each order bit included in the gradation data D of the three pieces of pixels corresponding to the intersections of the signal electrodes 212 and the three pieces of scanning electrodes 312, and generates conversion data Dt according to the result of this comparison. Then, for the period responsive to the conversion data Dt in each selection period, voltage +Vx is applied to the signal electrodes 212, and voltage -Vx is applied thereto for the rest of the period. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal device, an electro-optical device, a driving circuit thereof, a driving method, and an electronic device for simultaneously selecting a plurality of scanning electrodes and performing gradation display.

[0002]

2. Description of the Related Art Liquid crystal devices can be classified into various types according to the electrode structure and driving method. The matrix type includes active matrix type using switching elements such as transistors and diodes, and switching type. 2 of passive matrix type without using elements
It can be roughly divided into types. Among them, the passive matrix type has advantages that it is suitable for low power consumption because it does not use a switching element, and that it is easy to manufacture and low cost.

As a driving method of such a passive matrix type liquid crystal device, conventionally, a method of simultaneously selecting a plurality of scanning electrodes in order to achieve high contrast and low voltage driving (hereinafter, referred to as “MLS driving method”). ))
It has been known.

By the way, in the driving method of simultaneously selecting a plurality of scanning electrodes, when the number of scanning electrodes to be simultaneously selected increases, the number of voltage levels that the data signal supplied to the signal electrode can take also increases. For example, if a method of simultaneously selecting four scan electrodes is adopted, the data signal can have five voltage levels. When the number of voltage levels of the data signal increases in this way, problems such as a complicated structure of the signal electrode drive circuit, an increase in manufacturing cost, and an increase in power consumption may occur.

Therefore, the prior application of the present applicant (see Patent Document 1) discloses a technique for solving the above problem relating to an increase in the number of voltages and performing gradation display by using the MLS driving method. There is. According to the technique disclosed in this publication, the number of simultaneous selections is L, the number of gradations is N, the gradation data is D, and the orthogonal coefficient is F. Data can be obtained that indicates how long either voltage should be applied to the signal electrode. Therefore, it is possible to perform gradation display while suppressing the number of voltage levels of the data signal.

[Patent Document 1] Japanese Patent Laid-Open No. 10-133630

[0006]

However, when this technique is adopted, an arithmetic circuit shown in FIG. 19 for performing complicated arithmetic processing is required. Therefore, new problems such as an increase in manufacturing cost due to the complicated circuit configuration and an enlargement of the circuit scale may occur.

The present invention has been made in view of the above-described circumstances, and when performing gradation display using the MLS driving method, the number of voltage levels of a data signal is reduced and the data signal is generated. It is an object of the present invention to provide a liquid crystal device, an electro-optical device, a driving circuit and a driving method thereof, and an electronic apparatus using the liquid crystal device, which can simplify the processing for achieving the above.

[0008]

In order to solve the above problems, the present invention provides a liquid crystal device for displaying a pixel corresponding to an intersection of a scanning electrode and a signal electrode in gradation based on gradation data composed of a plurality of bits. Driving method, the three scanning electrodes are selected n times in one vertical scanning period according to a predetermined scanning pattern of 3 rows and n columns (n is an integer of 3 or more), and in each selection, the scanning is performed. A selection voltage corresponding to each of the three elements in the column corresponding to the selection in the pattern is applied to each of the three scan electrodes, and in each of the selection periods in which the three scan electrodes are selected, A bit string corresponding to an element of a column corresponding to the selection in the scanning pattern, and a bit of each position included in grayscale data of three pixels corresponding to the intersection of the signal electrode and the three scanning electrodes are arranged. Duplicate Of each of the bit strings, and conversion data corresponding to the comparison result is generated, and a first voltage is applied to the signal electrode in a period having a time length corresponding to the conversion data in the selection period. , A second voltage different from the first voltage in the remaining period
The voltage is applied to the signal electrode.

In such a driving method, the bit string corresponding to the gradation data of the three pixels corresponding to the intersection of the three scanning electrodes and the one signal electrode selected at the same time, and the element of the column of the scanning pattern. By comparing with the corresponding bit string, the conversion data that determines the voltage applied to the signal electrode and the application period thereof is generated. Therefore, according to the present embodiment, it is not necessary to perform a complicated calculation process when determining the voltage applied to the signal electrode. Therefore, for example, the circuit configuration for driving the signal electrode can be further simplified. On the other hand, the voltage applied to the signal electrode is the two of the first voltage and the second voltage.
Since it is a type, it is possible to prevent problems caused by an increase in the number of voltage levels applied to the signal electrodes, such as an increase in power consumption and a complicated circuit configuration.

As a specific method for generating conversion data by comparing bit strings in the above-mentioned driving method, it corresponds to the selection of the scanning pattern in each of the selection periods for selecting the three scanning electrodes. A bit string corresponding to an element of a column is compared with a plurality of bit strings formed by arranging bits of each position included in grayscale data of three pixels corresponding to the intersection of the signal electrode and the three scanning electrodes. Then, it is conceivable that a bit string formed by arranging bits corresponding to the number of mismatches (or the number of matches) of the bits obtained in each comparison is used as the conversion data.

In the above driving method, the first
Is applied to the signal electrodes during the period including the start of the period for selecting the three scan electrodes, or the period during which the second voltage is applied to the signal electrodes is set to three. It is desirable that the period including the start of the period for selecting the scan electrodes is alternately switched for each of the n periods. In this way, the number of times the voltage applied to the signal electrode is switched is reduced, and power consumption is further reduced.

Further, in addition to this switching, the first
The voltage application period is near the start of the selection period and the second voltage application period is near the end of the selection period, or the second voltage application period is Whether to set the period near the start of the selection period and the period near the end of the selection period to the period near the end of the selection period is alternated in each of n selections (fields) for the three scan electrodes. You may make it switch. In this way, display unevenness due to the difference in the effective value of the voltage applied to the liquid crystal can be suppressed, and good display quality can be secured. From the same reason, the application period of the first voltage is set to a period near the start of the selection period and the application period of the second voltage is set to a period near the end of the selection period, or The application period of the second voltage is set to a period near the start of the selection period, and
Whether or not the voltage application period is set to a period near the end of the selection period may be alternately switched for each of the one or more vertical scanning periods (frames). Furthermore, the first
The voltage application period is near the start of the selection period and the second voltage application period is near the end of the selection period, or the second voltage application period is Whether to set the period near the start of the selection period and the period near the end of the selection period to the first voltage application period may be alternately switched for each of the one or more signal electrodes.

In order to solve the above-mentioned problems, the present invention is a drive circuit for a liquid crystal device, which displays a pixel corresponding to an intersection of a scanning electrode and a signal electrode in gray scale based on gray scale data consisting of a plurality of bits. A scan electrode drive circuit for selecting three of the scan electrodes n times in one vertical scanning period in accordance with a predetermined scan pattern of 3 rows and n columns (n is an integer of 3 or more). , A scan electrode driving circuit for applying a selection voltage corresponding to each of the three elements in the column corresponding to the selection in the scan pattern to each of the three scan electrodes, and selecting the three scan electrodes In each of the selection periods to be performed, the bit string corresponding to the element of the column corresponding to the selection in the scanning pattern and the grayscale data of the three pixels corresponding to the intersection of the signal electrode and the three scanning electrodes are obtained. Included A conversion data output circuit for comparing each of a plurality of bit strings formed by arranging bits of each place and outputting conversion data corresponding to the comparison result, and a time length corresponding to the conversion data in the selection period. A first voltage is applied to the signal electrode during the period, and a second voltage different from the first voltage during the rest period.
And a voltage application circuit for applying the voltage of 1 to the signal electrode.

According to this drive circuit, the number of voltages applied to the signal electrode is reduced and the amount of calculation for generating this signal is reduced for the same reason as described in the above drive method. You can In this drive circuit, the conversion data output circuit includes a bit string corresponding to an element of a column corresponding to the selection in the scan pattern in each of the selection periods for selecting the three scan electrodes, And comparing each of the plurality of bit strings formed by arranging the bits of each position included in the gradation data of the three pixels corresponding to the intersection of the signal electrode and the three scanning electrodes,
It is conceivable that a bit string formed by arranging bits corresponding to the number of mismatches (or the number of matches) of bits obtained in each comparison is output as the conversion data.
Further, the voltage application circuit sets the application period of the first voltage to a period near the start of the selection period and sets the application period of the second voltage to a period near the end of the selection period, or , The selection period of the second voltage is set to a period near the start of the selection period, and the application period of the first voltage is set to a period near the end of the selection period. If it is configured to switch,
The number of times the voltage applied to the signal electrode is switched can be reduced.

Further, the present invention can be implemented as a liquid crystal device provided with the above drive circuit. That is, this liquid crystal device is a liquid crystal device that performs gradation display of pixels corresponding to the intersections of the scanning electrodes and the signal electrodes based on gradation data composed of a plurality of bits, and has a predetermined 3 rows and n columns ( n is 3
3 of the scan electrodes according to the scan pattern
A scan electrode drive circuit for selecting a book n times in one vertical scanning period, and in each selection, a selection voltage corresponding to each of the three elements in the column corresponding to the selection in the scan pattern is selected. A scan electrode drive circuit applied to each of the scan electrodes, and a bit string corresponding to an element of a column corresponding to the selection in the scan pattern in each of the selection periods for selecting the three scan electrodes, and the signal. The conversion data corresponding to the comparison result is compared with each of a plurality of bit strings formed by arranging bits of each position included in the gradation data of the three pixels corresponding to the intersection of the electrode and the three scanning electrodes. A converted data output circuit for outputting a first voltage is applied to the signal electrode in a period having a time length corresponding to the converted data in the selection period, and the first voltage is applied in the remaining period. A second voltage different from the first voltage, characterized by comprising a voltage applying circuit for applying to the signal electrodes. Also in this liquid crystal device, it is possible to reduce the number of voltage levels applied to the signal electrodes and simplify the process for generating the data signal.

Further, the driving method of the electro-optical device according to the present invention drives the electro-optical device in which the pixel corresponding to the intersection of the scanning electrode and the signal electrode is gradation-displayed based on the gradation data composed of a plurality of bits. In the method, three of the scan electrodes are selected n times in one vertical scanning period according to a predetermined scan pattern of 3 rows and n columns (n is an integer of 3 or more), and in each selection, the scan pattern of the scan pattern is selected. Of the three scanning electrodes, the selection voltage corresponding to each of the three elements in the column corresponding to the selection is applied to each of the three scanning electrodes, and the scanning is performed in each of the selection periods in which the three scanning electrodes are selected. A bit string corresponding to the element of the column corresponding to the selection in the pattern, and each bit included in the gradation data of three pixels corresponding to the intersection of the signal electrode and the three scanning electrodes are arranged. Narudou Of each of the bit strings, and conversion data corresponding to the comparison result is generated, and a first voltage is applied to the signal electrode in a period having a time length corresponding to the conversion data in the selection period. , A second voltage different from the first voltage in the remaining period
Is applied to the signal electrode. Further, the drive circuit of the electro-optical device according to the present invention is a drive circuit of the electro-optical device for displaying a pixel corresponding to the intersection of the scanning electrode and the signal electrode in gray scale based on gray scale data composed of a plurality of bits. Predetermined 3 rows and n columns (n is 3
3 of the scan electrodes according to the scan pattern
A scan electrode drive circuit for selecting a book n times in one vertical scanning period, and in each selection, a selection voltage corresponding to each of the three elements in the column corresponding to the selection in the scan pattern is selected. A scan electrode drive circuit applied to each of the scan electrodes, and a bit string corresponding to an element of a column corresponding to the selection in the scan pattern in each of the selection periods for selecting the three scan electrodes, and the signal. The conversion data corresponding to the comparison result is compared with each of a plurality of bit strings formed by arranging bits of each position included in the gradation data of the three pixels corresponding to the intersection of the electrode and the three scanning electrodes. A converted data output circuit for outputting a first voltage is applied to the signal electrode in a period having a time length corresponding to the converted data in the selection period, and the first voltage is applied in the remaining period. A second voltage different from the first voltage, characterized by comprising a voltage applying circuit for applying to the signal electrodes. Further, the electro-optical device according to the present invention is an electro-optical device that performs gradation display on the pixel corresponding to the intersection of the scanning electrode and the signal electrode based on gradation data composed of a plurality of bits, and is predetermined. According to the scanning pattern of 3 rows and n columns (n is an integer of 3 or more), one of the three scanning electrodes is
A scan electrode driving circuit that selects n times in a vertical scanning period, and in each selection, a selection voltage corresponding to each of the three elements in the column corresponding to the selection in the scan pattern is applied to the three scan electrodes. In each of the scan electrode driving circuit applied to each of the scan electrodes and the selection period of selecting the three scan electrodes, the bit string corresponding to the element of the scan pattern corresponding to the selection, the signal electrode, and Each of the plurality of bit strings formed by arranging the bits of each position included in the gradation data of the three pixels corresponding to the intersection of the three scanning electrodes is compared with each other, and the converted data corresponding to the comparison result is output. The conversion data output circuit applies the first voltage to the signal electrode during a period having a time length corresponding to the conversion data in the selection period, and the first voltage is applied during the remaining period. A second voltage different from the pressure, characterized by comprising a voltage applying circuit for applying to the signal electrodes. Furthermore, since the electronic apparatus according to the present invention includes the above liquid crystal device, it is possible to reduce the circuit scale and reduce power consumption. Further, since the electronic device according to the present invention includes the electro-optical device, it is possible to reduce the circuit scale and reduce the power consumption. Examples of such electronic devices include mobile phones and digital still cameras.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. Such an embodiment shows one aspect of the present invention, does not limit the present invention, and can be arbitrarily modified within the scope of the present invention.

<A: Configuration of Liquid Crystal Device> FIG. 1 is a block diagram showing an electrical configuration of a liquid crystal device according to an embodiment of the present invention. As shown in the figure, the liquid crystal device 100 includes a plurality of scan electrodes (common electrodes) 3 extending in the row (X) direction.
12 and a plurality of signal electrodes (segment electrodes) 212 extending in the column (Y) direction. Each scanning electrode 312 and each signal electrode 212 are strip electrodes. The pixel 130 is composed of a portion of the scanning electrode 312 and the signal electrode 212 that face each other, and a liquid crystal of TN (Twisted Nematic) type or STN (Super Twisted Nematic) type sandwiched between the portions. In the present embodiment, it is assumed that 120 scanning electrodes 312 and 160 signal electrodes 212 are provided. Therefore, although the resolution of the liquid crystal device 100 is 120 dots in the vertical direction × 160 dots in the horizontal direction, it does not mean that the liquid crystal device to which the present invention is applied is limited to this.

The signal voltage generating circuit 450 is provided for the scanning electrodes 312 and the signal electrodes 2 when driving the liquid crystal device 100.
12 is a circuit for generating a voltage applied to 12. More specifically, the signal voltage generation circuit 450 uses the scan electrodes 3
± Vy (selection voltage) and Vc (non-selection voltage) used as voltage applied to 12 are supplied to the scan electrode driving circuit 350, and ± Vx used as voltage applied to the signal electrode 212 is generated. And supplies it to the signal electrode drive circuit 250. The voltage Vc is also an intermediate value voltage between the voltages + Vx and −Vx used as the data signal.

The scan electrode driving circuit 350 simultaneously selects a plurality of scan electrodes 312 for each horizontal scanning period,
The scanning signals Y1, Y2, Y3, ... According to the selected state
Y120 is supplied to the corresponding scan electrodes 312. On the other hand, the signal electrode drive circuit 250 has data signals X1, X2, X3, ..., X160 corresponding to display contents of pixels corresponding to the intersections of the scan electrodes 312 selected by the scan electrode drive circuit 350 and the respective signal electrodes 212. Are supplied to the corresponding signal electrodes 212. The details of the scan electrode driving circuit 350 and the signal electrode driving circuit 250 will be described later.

Here, the liquid crystal device 10 according to the present embodiment.
The driving of 0 is performed by simultaneously selecting a plurality of scan electrodes 312 and selecting the scan electrodes 312 in a plurality of times within one vertical scanning period. In this driving, the following scanning pattern is used when applying the selection signal to the scanning electrodes 312. That is, this scanning pattern is a kind of matrix that defines the polarity of the selection signal to be supplied to each of the simultaneously selected scan electrodes,
Rows in the scan pattern are simultaneously selected scan electrodes 3
Twelve, columns correspond to selections in one frame,
Each element defines the polarity of the selection voltage.

For example, when the scanning pattern is represented by M rows and N columns (M and N are integers of 2 or more), the number of scanning electrodes simultaneously selected is M, and N selections are performed in one frame. The element in the m-th row and the n-th column (m is an integer satisfying 2 ≦ m ≦ M and n is an integer satisfying 2 ≦ n ≦ N) is 1 in the m-th scan electrode among the simultaneously selected scan electrodes. The polarity of the selection voltage to be applied in the nth selection of the frame is defined.

The condition required for this scanning pattern is to satisfy normality and orthogonality. The "normality" is a property that, when a scan electrode is selected according to a scan pattern and a select voltage is applied, the execution values of the select voltage applied to each scan electrode are equal to each other in a unit of one frame. . Further, “orthogonality” means a voltage amplitude applied to a certain scan electrode and a voltage amplitude applied to another arbitrary scan electrode when a scan electrode is selected according to a scan pattern and a selection voltage is applied. Is a property that the sum of products for one frame becomes zero.

Here, in the present embodiment, the number of scanning electrodes to be selected simultaneously is set to "3", so that the scanning pattern of 3 rows and 4 columns shown in FIG. 2B is used. In the scan pattern shown, for example, the element “+1” in 1 row and 4 columns
Means that the positive selection voltage should be applied to the first row scan electrode 312 among the three scan electrodes 312 selected at the same time in the fourth selection in one frame. Further, for example, the element “−1” in the third row and the third column has the negative polarity in the third selection in one frame with respect to the scanning electrode 312 in the third row among the three scanning electrodes 312 that are simultaneously selected. This means that a selection voltage should be applied. It will be easily understood that the illustrated scanning pattern satisfies the normality and orthogonality described above. (Here, the polarity is not necessarily based on 0 [V], and may be based on any potential. Positive polarity and negative polarity refer to the positive potential side with respect to the reference potential, respectively. , Means the potential on the negative polarity side.)

Regarding the selection of the scanning electrodes 312,
There are two methods: (1) a method that is temporally dispersed in one frame, and (2) a method that is temporally aggregated in one frame. In the present embodiment, the method (1) will be described, and the method (2) will be described in a modification described later.

In order to carry out such driving, the timing signal generation circuit 106 generates necessary control signals and clock signals. More specifically, the timing signal generation circuit 106 includes a frame start pulse YD, a field start pulse FP, a frame signal FR, and a clock signal YC.
K, the gradation control signal GCP, the reset signal RES, and the odd-even signal SS are generated respectively. A brief description of these signals is as follows.

First of all, the frame start pulse YD is
As shown in FIG. 2A, one vertical scanning period (frame)
This is the pulse output at the beginning of 1F. Secondly, the field start pulse FP is, as shown in FIG. 2A, the fields f1 and f obtained by equally dividing one frame (1F) into four.
It is the first pulse output at 2, f3 and f4.
Thirdly, the frame signal FR is a signal whose level is inverted every frame (1F). Fourth, the clock signal Y
CK is a clock signal having a cycle of one horizontal scanning period (see FIG. 4).

Fifth, the reset signal RES is a pulse which falls at the beginning of one horizontal scanning period (1H) as shown in FIG. Sixth, the grayscale control signal GCP is as shown in FIG.
As shown in 0, the pulses are arranged at a time point corresponding to the level of the intermediate gradation in one horizontal scanning period. Here, in the present embodiment, it is assumed that the gradation data D for instructing the density of the pixel is represented by 3 bits and 8-gradation display is performed. If (000) of the grayscale data D indicates white (off) while (111) indicates black (on), the grayscale control signal GCP indicates white display and black display. Excluding gradation data (001) to (110)
The pulses corresponding to the 6 gray scales are arranged corresponding to the intermediate gray scale levels. In the present embodiment, the gradation control signals GCP are arrayed at equal pitches. It is desirable to compensate for sex.

Seventh, the odd signal SS is a signal whose level is inverted every horizontal scanning period. Specifically, as shown in FIG. 14, in the fields f1 and f3 of one frame (1F), the odd number signal SS is at the H level in the odd-numbered horizontal scanning period (1H) of the field, It becomes L level during the even-numbered horizontal scanning period (1H). On the other hand, in the fields f2 and f4 of one frame (1F), the field f1 is
Contrary to the case of f3 and f3, it becomes L level in the odd-numbered horizontal scanning period of the field, while it becomes H-level in the even-numbered horizontal scanning period.

Next, the scan code generator 108 shown in FIG.
Is a frame start pulse YD and a field start pulse F
Based on P and the frame signal FR, the scan codes CY1, CY2 and CY3 shown in FIG. 2A are output.
Here, the scan codes CY1, CY2 and CY3 are the elements of the columns in the scan pattern, and are the fields f1,
It corresponds to each of f2, f3, and f4 in time series. That is, for example, the scan code CY1 in the period in which the frame signal FR is at the L level is, as shown in FIG. 2A, 1st row, 1st column, 1st row 2nd column, 1st row 3rd column of the scanning pattern, respectively.
It is output in fields f1, f2, f3 and f4 corresponding to each of the elements in the 1st row and the 4th column. Similarly, the scan codes CY2 and CY3 during the period when the frame signal FR is at the L level respectively correspond to the elements of 2nd row, 1st column to 2nd row, 4th column, and 3rd row, 1st column to 3rd row, 4th column of the scanning pattern. And fields f1, f2, f3 and f, respectively.
4 is output. On the other hand, the scan code CY generated in the frame in which the frame signal FR is at the H level
As shown in FIG. 2A, 1, CY2, and CY3 are the polarities of the scan codes CY1, CY2, and CY3 in the frame in which the frame signal FR is at the L level.

<Scan Electrode Driving Circuit> Next, the structure of the scan electrode driving circuit 350 will be described. FIG. 3 is a block diagram showing the configuration of the scan electrode driving circuit 350. In the figure, the shift register 3520 indicates that the number of scan electrodes is “12”.
This is a 40-bit shift register corresponding to the number "40" obtained by dividing "0" by the number "3" selected simultaneously, and as shown in FIG.
The field start pulse FP described above is shifted every horizontal scanning period and sequentially output as the transfer signals Ys1 to Ys40. Here, the transfer signal Ys1 is selected / unselected for the three scanning electrodes 312 in the first to third rows from the top in FIG. 1 (selected at H level, unselected at L level). ). Similarly, the transfer signal Ys2 is applied to the three scanning electrodes 31 in the fourth to sixth rows.
The transfer signal Ys40
Is the three scanning electrodes 31 in the 118th to 120th rows.
Instruct to select / deselect 2 items. Therefore, for example, in the first horizontal scanning period of one frame,
The scan electrodes 312 on the third row are simultaneously selected, and the scan electrodes 312 on the fourth to sixth rows are simultaneously selected in the next horizontal scanning period.

Further, as shown in FIG. 3, in the subsequent stage of the shift register 3520, a number (40) of decoding units 3540, level shift units 3560, which correspond to a set of three scanning electrodes 312 that are simultaneously selected, And a selection unit 3580 is provided. Each decode unit 3540, based on the transfer signal supplied from the shift register 3520 and the scan codes CY1, CY2, and CY3 supplied from the scan code generator 108,
A voltage selection signal corresponding to each scan electrode 312 is output.
The voltage selection signal is a signal indicating which of the voltages + Vy, Vc or -Vy should be applied to each of the three scan electrodes 312 that are simultaneously selected. More specifically, each of the decoding units 3540 includes a shift register 3
In the period in which the transfer signal supplied from 520 is at the H level (that is, the horizontal scanning period in which the corresponding scan electrode 312 is selected), the scan codes CY1 and C are generated.
Depending on the levels of Y2 and CY3, it outputs a voltage selection signal instructing selection of either the selection voltage + Vy or -Vy. On the other hand, in the period in which the transfer signal is at the L level (that is, the period in which the corresponding scan electrode 312 is not selected), each decode unit 354
0 outputs a voltage selection signal instructing selection of the voltage Vc.

On the other hand, each level shift unit 3560
Is to expand the voltage amplitude of the voltage selection signal output by the decoding unit 3540 in the preceding stage. Then, the selection unit 3580 is for actually selecting the selection voltage instructed by the voltage selection signal having the enlarged voltage amplitude and applying it to the corresponding scanning electrode 312.

<Signal Electrode Driving Circuit> As described above, in the present embodiment, a driving method in which the three scanning electrodes 312 are selected at the same time and the scanning electrodes 312 are selected a plurality of times within one frame. adopt. In this driving method, generally, the j-th column (j is 1 ≦ j ≦ 160
The voltage to be applied to the signal electrode 212 of
I omit the details because I need a mathematical argument,
In summary, it is decided as follows. That is, the j-th
The voltage to be applied to the signal electrode 212 of the column is the pixel located at the intersection of the element of the column corresponding to the selection of the scanning pattern and the scanning electrode 312 selected at the same time as the signal electrode 212 of the jth column. The elements of and are multiplied by the corresponding ones,
The sum of them is calculated (sum of products), and the sum is multiplied by an appropriate coefficient to obtain a value.

However, in the present embodiment, the gradation data given to each of the three pixels located at the intersections of the three scanning electrodes 312 to be simultaneously selected and one arbitrary signal electrode 212. D and scan codes CY1 and CY2
And CY3 are compared with each other, and PWM (pulse width modulation) processing is performed using the conversion data Dt generated according to the comparison result, so that gradation display according to the gradation data D is performed. ing. Hereinafter, a specific configuration of the signal electrode driving circuit 250 will be described with reference to FIG.

As shown in FIG. 5, the signal electrode drive circuit 25
0 is the frame memory 251 and the row address generator 25
2, a conversion data output circuit 254, and a PWM circuit 255
And a level shifter group 257 and a selector group 258. Of these, the frame memory 251 has 120 rows x 1
Dual port R having a region corresponding to 60 columns of pixels
AM. That is, on the write side of the frame memory 251, the grayscale data D supplied from a processing circuit (not shown) (not shown) is supplied to the designated write address Wa.
written to d. On the other hand, on the read side of the frame memory 251, the gradation data D is read according to the row address Rad designated by the row address generation unit 252.

The row address generator 252 uses the row address R
The ad is reset by the field start pulse FP supplied first in the fields f1, f2, f3, and f4, and is incremented by the clock signal YCK having a cycle of one horizontal scanning period. That is, for example, in the first horizontal scanning period in one field, the first horizontal scanning period counted from the top in FIG.
Pixels for three rows (“3 rows × 1
The row address Rad for reading out the (60 columns) pieces of gradation data D is generated, and in the subsequent second horizontal scanning period, it corresponds to the fourth to sixth rows counted from the top in FIG. The row address Rad for reading the gradation data D of the pixels for the three rows is generated.

The gradation data D of the pixels for three rows thus read out are lines A1 to A160, B1 to B160, provided corresponding to the number of the signal electrodes 212, respectively.
And C1 to C160. Of these lines, A1 to A160 are lines to which the grayscale data D of 160 pixels belonging to the first row of the read grayscale data D of three rows are respectively output. Similarly, lines B1 to B160 and lines C1 to C16
0 is a line to which the grayscale data D of 160 pixels belonging to each of the second and third rows of the read grayscale data D of three rows is output. An integer j (1≤j that specifies any one of the signal electrodes 212
≤160), the grayscale data D of the three pixels belonging to the j-th column out of the read grayscale data D of three rows are respectively represented by lines Aj, Bj, and C.
output to j.

Here, the row address Rad is stepped by the clock signal YCK having the same cycle as one horizontal scanning period. Therefore, as shown in FIG. 6, for each horizontal scanning period that constitutes one field, the 1st row, the 4th row, the 7th row, ... The gradation data D of the pixel to which the pixel belongs belongs to the line A1
.About.A160 (generally indicated as Aj in FIG. 6) to the converted data output circuit 254. Similarly, as shown in FIG. 6, in each horizontal scanning period, the second row counted from the top in FIG.
The grayscale data D of the pixels belonging to the fifth row, the eighth row, ... From the third row to the sixth row, the ninth row, ..., And the 120th row, the grayscale data D of the pixels is converted data output circuit 254 via lines C1 to C160, respectively.
Is output to.

On the other hand, the converted data output circuit 25 shown in FIG.
4 has 160 data conversion units 2540 corresponding to the number of signal electrodes 212. Each data conversion unit 2540 compares the gradation data D for three pixels supplied from the frame memory 251 with the scan codes CY1, CY2 and CY3 supplied from the scan code generator 108, and the comparison result. Is a circuit for outputting converted data Dt according to the above. Here, FIG. 7 is a block diagram showing a configuration of each data conversion unit 2540. As shown in the figure, the data conversion unit 2540
Is an MSB comparison unit 2541 and a 2SB comparison unit 2542.
And an LSB comparison unit 2543.

The MSB comparing section 2541 scans the most significant bit (MSB) contained in each of the gradation data D for three pixels supplied from the frame memory 251 and the scan code CY.
The bits corresponding to the levels of 1, CY2, and CY3 are compared, and the bit having the value of (0) or (1) according to the comparison result is converted into the conversion data Dt.
Is output as the most significant bit. Hereinafter, this comparison method will be described in detail.

First, the MSB comparing section 2541 determines the gradation data D for three pixels supplied from the frame memory 251.
Of each of the scan codes CY1, CY2 and CY3 (1 if the scan code is H level, (0) if the scan code is L level). ), The bits at each position are compared with each other, and the number of unmatched bits (hereinafter, referred to as “mismatched number”) is counted. That is, for example, one data conversion unit 25
The gradation data for 3 pixels supplied to the
n1 (MSB1, 2SB1, LSB1), Dn2 (MS
B2, 2SB2, LSB2), Dn3 (MSB3, 2S
B3, LSB3), the MSB comparison unit 2541
Is a bit string (MSB
1, MSB2, MSB3) and scan codes CY1, CY
The number of disagreements is calculated by comparing the bits of each position with the bit string consisting of three bits corresponding to each of 2 and CY3. Then, the MSB comparison unit 2541
Outputs bit (0) as the most significant bit of the conversion data Dt if the number of mismatches is "0" or "1" and if the number of mismatches is "2" or "3". . Although the number of mismatches is calculated here, the number of matches may be calculated instead of this. That is, if the number of matches is “0” or “1”, the bit (1) is output, and if the number of matches is “2” or “3”, the bit (0) is output as the most significant bit of the conversion data Dt, respectively. It may be done.

Similarly, the 2SB comparing section 2542 has a bit string corresponding to the levels of the scan codes CY1, CY2 and CY3 and a bit string formed by arranging the second significant bits included in each of the gradation data D of three pixels. Bit (1) or (0) is converted data D according to the number of mismatches between
Output as the second bit of t. Taking the above case as an example, the 2SB comparison unit 2542 outputs bits according to the number of mismatches between the bit string (2SB1, 2SB2, 2SB3) in which the second-order bits are arranged and the bit string corresponding to the scan code. is there. Further, the LSB comparison unit 2543 is
Depending on the number of mismatches between the bit string formed by arranging the least significant bits (LSB) included in each of the gradation data D for three pixels and the bit string corresponding to the levels of the scan codes CY1, CY2 and CY3 (1) or (0)
Is output. Taking the above case as an example, the LSB comparing unit 2
543 is a bit string (LSB) in which the least significant bits are arranged.
1, LSB2, LSB3) and a bit string corresponding to the number of mismatches between the bit string corresponding to the scan code are output. In this way, the bit string formed by arranging the three bits output from each of the MSB comparing unit 2541, the 2SB comparing unit 2542 and the LSB comparing unit 2543 is output to the PWM circuit 255 as the conversion data Dt.

Next, as shown in FIG. 5, the PWM circuit 255 has 160 stages of PW corresponding to the number of signal electrodes 212.
It has an M unit 2550 and an inverter 2554. Each PWM unit 2550 outputs the voltage selection signal VSP based on the conversion data Dt supplied from the data conversion unit 2540 in the previous stage. This voltage selection signal VSP is converted data D in one horizontal scanning period.
A signal indicating that either the voltage + Vx or −Vx should be applied to the signal electrode 212 for the time length corresponding to the content of t, while the other voltage should be applied for the remaining time length. is there. As shown in FIG. 5, an odd-numbered stage (first stage, third stage, ...) Of the 160-stage PWM unit 2550 forming the PWM circuit 255.
The odd-numbered signal SS is input to the PWM unit 2550 at the 159th stage, while the even-numbered stages (the second stage, the fourth stage,
.. (160th stage), the inverted oddness signal / SS obtained by inverting the level of the oddness signal SS by the inverter 2554 is input to the PWM unit 2550.

Here, FIG. 8 shows each PWM unit 255.
It is a block diagram which shows the structure of 0. In addition, here, the odd-numbered PWM unit 25 to which the odd-even signal SS is input
50 is illustrated. As shown in the figure, the PWM unit 2
550 has a counter 2551 and a decoder 2552. Of these, the counter 2551 has a reset signal RE.
After being reset at the falling edge of S, that is, at the start of one horizontal scanning period, the gradation control signal GCP
Is counted up and the obtained count value (3 bits) is output to the decoder 2552. On the other hand, the decoder 2552 uses the PW shown in FIGS. 9A and 9B.
In accordance with the M table and the odd signal SS supplied from the timing signal generation circuit 106, the data conversion unit 2
The voltage selection signal VSP corresponding to the content of the conversion data Dt supplied from 540 and the count value output from the counter 2551 is output. The details are as follows.

That is, in the horizontal scanning period in which the odd-numbered signal SS is at the H level, the decoder 2552 is operated as shown in FIG.
According to the PWM table shown in (a), as shown in FIG. 10, during the period from the start of the horizontal scanning period until the count value becomes the value to be the conversion data Dt, the L level indicating the selection of the voltage −Vx is set. While outputting the voltage selection signal VSP, the voltage + Vx is maintained from the count value becomes a value corresponding to the conversion data Dt to the end of one horizontal scanning period.
The H-level voltage selection signal VSP for instructing the selection is output.

On the other hand, during the horizontal scanning period when the odd signal SS is at the L level, the decoder 2552 operates as shown in FIG.
According to the PWM table shown in (b), as shown in FIG. 10, during the period from the start of one horizontal scanning period until the count value becomes the value corresponding to the conversion data Dt, the H level of the voltage + Vx is selected. While the voltage selection signal VSP is being output, the voltage − during the period from when the count value becomes the value corresponding to the conversion data Dt until the end of the horizontal scanning period.
An L level voltage selection signal VSP for instructing selection of Vx is output.

As is apparent from the above, the strange signal SS
Regardless of whether it is H level or L level, the time length of the period instructing the selection of the voltage + Vx (or -Vx) is the time length according to the content of the conversion data Dt. As described above, the odd-even signal SS is a signal for switching between a period including the start time point and the end time point of each horizontal scanning period for selecting the voltage −Vx. However, as shown in FIG. 9 and FIG.
When the conversion data Dt is (000), the M unit 2550 has an L level voltage selection signal VSP instructing selection of the voltage −Vx over one horizontal scanning period.
When the converted data Dt is (111), the H level voltage selection signal VSP for instructing selection of the voltage + Vx is output over the entire one horizontal scanning period.

In the following, the voltage of the data signal for turning on the pixel 130 corresponding to the intersection of the scanning electrode 312 of the first row and the signal electrode 212 of the first column in the first horizontal scanning period of each frame. Is referred to as “on-voltage”.
For example, in the first frame shown in FIG. 11, that is, in the frame in which the frame signal FR is at the L level, the voltage −Vx of the data signal corresponds to the “on voltage”. On the other hand, in the second frame following the frame, that is, in the frame in which the frame signal is at the H level, the selection voltage applied to the scan electrode 312 has the opposite polarity to that in the first frame. In the second frame, the voltage + Vx of the data signal is the "on voltage"
Becomes Further, in this specification, when focusing on one horizontal scanning period, the start side is described as “left” and the end side is described as “right”. For example, when the period in which the data signal has an on-voltage is a period including the beginning of one horizontal scanning period, it is expressed as “leftward with respect to the horizontal scanning period” and the period in which the data signal has an on-voltage. Is 1
When the period includes the end of the horizontal scanning period, it is described as “rightward with respect to the horizontal scanning period”.

Although the odd-numbered PWM unit 2550 is illustrated here, the even-numbered PWM unit 25 is illustrated.
50 also has a similar function. However, even-numbered PWM
The unit 2550 includes, as shown in brackets in FIG.
The inverted oddness signal / SS is input. Therefore, in the horizontal scanning period in which the odd-numbered PWM unit 2550 generates the voltage selection signal VSP that becomes H level in the leftward period of the horizontal scanning period, the even-numbered PWM unit 2550 determines the horizontal scanning period in the horizontal scanning period. The voltage selection signal VSP that is at the H level in the rightward period is generated. Similarly, in the horizontal scanning period in which the odd-numbered PWM unit 2550 generates the voltage selection signal VSP that becomes H level in the rightward period of the horizontal scanning period, the even-numbered PWM unit 2550 generates the voltage selection signal VSP in the horizontal scanning period. H during the leftward period
The voltage selection signal VSP that becomes the level is generated.

Referring again to FIG. 5, the level shifter group 257
The level shift unit 2570 constituting the
The voltage amplitude of the voltage selection signal VSP output from the unit 2550 is expanded and output. In addition, the selection unit 2580 that constitutes the selector group 258 has the voltage selection signal VS output from the level shift unit 2570.
Depending on the level of P, either the voltage + Vx or −Vx is selected and applied to the signal electrode 212. More specifically, the selection unit 2580 determines that the voltage selection signal VSP is H level.
If it is at level, voltage + Vx is selected, while if it is at L level, voltage -Vx is selected. Therefore, during a certain horizontal scanning period, the period during which the data signal becomes the voltage + Vx is
Depending on the content of the voltage selection signal VSP, it becomes to the right or to the left with respect to the horizontal scanning period.

<B: Operation of Liquid Crystal Device> Next, the operation of the above-described liquid crystal device will be described. In the following description, in each horizontal scanning period (1H) included in one field, the kth position (k is 1 ≦ k ≦ 4 from the start of the field).
When paying attention to the horizontal scanning period of (integer satisfying 0), this horizontal scanning period may be described as “horizontal scanning period hk”.

<Voltage Waveform of Scan Signal> First, in the field f1 of the frame in which the frame signal FR is at L level, the scan code generator 108 has the elements “+1” and “−” which are the elements of the first column in the scan pattern. 1 ”,“ +1 ”
In response, the scan codes CY1, CY2, CY3 are output as H, L, H levels, respectively (see FIGS. 2A and 2B).

On the other hand, when the field start pulse FP is supplied, the shift register 35 of the scan electrode driving circuit 350 is supplied.
As shown in FIG. 4, the 20 sequentially latches the field start pulse FP at the rising edge of the clock signal YCK and outputs it as transfer signals Ys1, Ys2, ..., Ys40. For example, in the first horizontal scanning period h1, only the transfer signal Ys1 is at the H level, and the selection of the scanning electrodes 312 of the first row, the second row, and the third row is instructed. In this case, the first line, the second line and the third line
The decoder 3540 corresponding to the scan electrode 312 in the row is
As a voltage to be applied to these scan electrodes 312, a voltage selection signal indicating any one of voltages + Vy or −Vy corresponding to scan codes CY1, CY2 and CY3 is output. On the other hand, the decoder 3540 corresponding to the other scan electrodes 312 (that is, L
The decoder 3540, to which the level transfer signal is applied,
A voltage selection signal indicating a voltage Vc as a voltage to be applied to these scan electrodes 312 is output. As a result, as shown in FIGS. 11 and 14, the field f1
In the first horizontal scanning period h1 in, the scanning signals Y1, Y2, and Y3 are at the voltages + Vy and −Vy, respectively.
And + Vy, while the other scanning signals have a voltage Vc.

When one cycle of the clock signal YCK has elapsed, the shift register 3520 sets only the transfer signal Ys2 to the H level in the second horizontal scanning period h2. This instructs the selection of the scanning electrodes 312 on the fourth, fifth, and sixth rows. In this case, the decoder 3 corresponding to the three scan electrodes 312 selected
540 outputs a voltage selection signal indicating one of voltages + Vy or −Vy corresponding to scan codes CY1, CY2, and CY3 as a voltage to be applied to these scan electrodes 312. On the other hand, the decoder 3540 corresponding to the other scan electrodes 312 is
A voltage selection signal indicating a voltage Vc as a voltage to be applied to these scan electrodes 312 is output. As a result, as shown in FIGS. 11 and 14, the field f1
In the second horizontal scanning period h2, the scanning signals Y4, Y5, and Y6 have voltages + Vy and −Vy, respectively.
And + Vy, while the other scanning signals have a voltage Vc. Thereafter, the same operation is performed in the field f1 by the fourth operation.
The process is repeated until the 0th horizontal scanning period h40.

Next, in the field f2, the scan code generator 108 corresponds to the elements "-1", "+1", "+1" of the second column in the scan pattern, corresponding to the scan codes CY1, CY1 ,. CY2 and CY3 are respectively L,
Output at H and H levels (FIGS. 2A and 2B)
reference). Therefore, in the first horizontal scanning period h1 in which only the transfer signal Ys1 is at the H level, the scanning signals Y1, Y2, and Y3 are the voltages −Vy, + Vy, and + Vy, respectively, while the other scanning signals are the voltage Vc. Become. Then, the second signal in which only the transfer signal Ys2 becomes H level
In the second horizontal scanning period h2, the scanning signals Y4, Y
5 and Y6 are voltages -Vy, + Vy and + V, respectively.
On the other hand, the other scanning signal becomes the voltage Vc while the y signal becomes y. Less than,
In field f2, the same operation is repeated until the 40th horizontal scanning period h40.

Similar processing is performed in the subsequent fields f3 and f4. That is, as shown in FIG. 11, in each of the 40 horizontal scanning periods included in one field, the scanning signal output to the three scanning electrodes 312 designated by the H-level transfer signal is in that field. Scan codes CY1, CY2 and C
The scan signal of the other scan electrodes 312 becomes the voltage Vc, while the voltage becomes either + Vy or −Vy selected according to Y3.

Further, in the next frame in which the frame signal FR becomes H level, the scan code generator 108.
Outputs, as the scan codes CY1, CY2 and CY3, signals obtained by inverting the polarities of the scan codes CY1, CY2 and CY3 during the period when the frame signal FR is at the L level.
Therefore, as shown in FIG. 11, the scanning signal Y1, which is output during the period when the frame signal FR is at the H level,
Y2, Y3, ..., Y120 are obtained by inverting the polarities of the scanning signals output during the period when the frame signal FR is at the L level.

<Voltage Waveform of Data Signal> Next, the data signals X1 and X output from the signal electrode drive circuit 250.
The voltage waveforms of 2, X3, ..., X160 will be described.
Here, as shown in FIG. 12, three scanning electrodes 312 from the first row to the third row intersect two signal electrodes 212 in the first and second rows. Located at 6
It is assumed that attention is paid to the number of pixels, and the case where the gray scale display according to the gray scale data D shown in FIG.

First, the operation will be described by focusing on the first horizontal scanning period h1 of the field f1 of the frame in which the frame signal FR becomes L level. This horizontal scanning period h
In 1, the gradation data D corresponding to the pixels on the first row, the second row, and the third row is read from the frame memory 251. Among the grayscale data D for three rows read out in this way, the grayscale data D of the pixel belonging to the j-th column is input through the lines Aj, Bj, and Cj, respectively, and the data conversion unit 2540 at the j-th stage. Is supplied to. For example, in FIG.
Focusing on the grayscale data D for 6 pixels shown in FIG. 2, the grayscale data D (000), (001), and (011) corresponding to the pixels of 1st row, 1st column, 2nd row, 1st column, and 3rd row, 1st column ) Is supplied to the first-stage data conversion unit 2540, and the gradation data D (101), (110), and (111) corresponding to the pixels of 1st row, 2nd column, 2nd row, 2nd column, and 3rd row, 2nd column are supplied. ) Is supplied to the second-stage data conversion unit 2540.

On the other hand, when the gradation data D of the three pixels belonging to the same column are supplied in this way, the data conversion unit 2
The MSB comparison unit 2541, the 2SB comparison unit 2542, and the LSB comparison unit 2543 that compose 540 include scan codes CY1 and CY2 supplied from the scan code generation unit 108.
And 3 bits corresponding to the levels of CY3 and the most significant bit (MSB), the second most significant bit (2SB) and the least significant bit (LSB) included in the grayscale data D, respectively, and compare each. The bits corresponding to the result are output as the bits forming the conversion data Dt. Less than,
A specific example of the operation of the data conversion unit 2540 will be described with reference to FIG. Note that only the six pixels shown in FIG. 12 are focused here, but the same processing is executed for the other pixels belonging to the three rows selected.

First, 1st row and 1st column, 2nd row and 1st column, and 3rd row and 1st column
Grayscale data (000), (0
The operation of the first-stage data conversion unit 2540 supplied with (01) and (011) will be described. Here, in the field f1 of the frame in which the frame signal FR is at the L level, the scan codes CY1, CY2, and CY3 are at the H, L, and H levels, respectively, and the corresponding bit string is (101). Therefore, the MSB comparison unit 254 of the data conversion unit 2540
1 compares bits of each position between this bit string (101) and a bit string (000) formed by arranging the most significant bit (MSB) included in each of the gradation data D for three pixels. . In this case, the number of mismatches is "2".
Therefore, the MSB comparison unit 2541 outputs bit (1) as the most significant bit of the conversion data Dt. on the other hand,
The 2SB comparison unit 2542 is arranged between the bit string (101) corresponding to the scan code and the bit string (001) formed by arranging the second significant bits (2SB) included in each of the gradation data D of three pixels. , Count the number of mismatches between bits. In this case, the number of mismatches is "1",
The 2SB comparison unit 2541 converts the bit (0) into the conversion data D
Output as the second bit of t. Similarly, the LSB comparing unit 2543 causes the bit string (10
The bit (1) is set according to the number of mismatches “2” between 1) and the bit string (011) formed by arranging the least significant bits included in each of the gradation data D for three pixels. The converted data Dt is output as the least significant bit. As a result, in the field f1, as shown in FIG. 13, the gradation data D for three pixels and the scan codes CY1, CY2 and CY are displayed.
From 3, the converted data Dt of (101) is obtained.

1 × 2, 2 × 2, and 3 × 2, 3
Gradation data D (101), (110), corresponding to pixels
The same process is performed in the second-stage data conversion unit 2540 which has received (111) and (111). That is, in this case, the bit string (111) composed of the most significant bit, the bit string (011) composed of the second most significant bit, and the bit string (101) composed of the least significant bit of the gradation data D for three pixels are respectively Scan code CY1,
It is compared with the bit string (101) corresponding to CY2 and CY3, and the bit string (010) corresponding to the number of mismatches "1", "2", and "0" obtained as a result.
Is output as converted data Dt.

Next, when the conversion data Dt is supplied from each data conversion unit 2540, the PWM unit 2550 forming the PWM circuit 255 outputs the voltage + Vx or -Vx according to the conversion data Dt in the horizontal scanning period h1. It outputs a voltage selection signal VSP instructing either selection. For example, the first-stage PWM unit 2550 is now supplied with the conversion data Dt of (101) and the odd-level odd signal SS of H level. In this case, according to the PWM table shown in FIG. 9A, the PWM unit 2550 becomes the L level instructing the selection of the voltage −Vx in the first two periods of the period obtained by dividing the horizontal scanning period h1 into seven, In the remaining five periods, it outputs the voltage selection signal VSP at the H level that instructs selection of the voltage + Vx. After that, in the selection unit 2580 in the first stage, either the voltage + Vx or -Vx is selected according to the voltage selection signal VSP, and as a result, the voltage waveform of the data signal X1 becomes as shown in FIG. At this time, the voltage −Vx corresponding to the ON voltage is leftward with respect to the horizontal scanning period h1.

On the other hand, in this horizontal scanning period h1, 2
The conversion data Dt of (010) and the inversion oddity signal / SS of L level are supplied to the PWM unit 2550 of the stage. Therefore, this PWM unit 2550
According to the PWM table shown in FIG. 9B, the voltage selection signal becomes H level in the first two periods of the horizontal scanning period h1 divided into seven, and becomes L level in the remaining five periods. Generate VSP. As a result, the voltage waveform of the data signal X2 in the horizontal scanning period becomes as shown in FIG. Although only the operation related to the data signals X1 and X2 has been described here, the same operation is performed for the other data signals X3 to X160. Therefore, whether the period in which the data signal is on-voltage is leftward or rightward with respect to the horizontal scanning period h1 is alternately switched for each one of the signal electrodes 212.

Next, the operation in the second horizontal scanning period h2 in the field 1f will be described. In the horizontal scanning period h2, as shown in FIG. 11, the scanning signals Y4, Y5, and Y6 are the voltages + Vy and −V, respectively.
y and + Vy, while the other scanning signals have voltage Vc. That is, the fourth to sixth rows from the top in FIG.
The three scan electrodes 312 up to the row are selected at the same time.

Here, the three scan electrodes 312 and the first
Focusing on the six pixels corresponding to the intersections with the signal electrodes 212 in the second and second columns, the same gradation data D as shown in FIG. 12 is given to these pixels, respectively. Imagine the case. In this case, the conversion data Dt given to each PWM unit 2550 in the horizontal scanning period h2 is the above-mentioned first horizontal scanning period h1.
The contents are the same as in the case of. However, in the second horizontal scanning period h2 and the first horizontal scanning period h1, the level of the odd-even signal SS (and the inverted odd-even signal / SS) is inverted. Therefore, the voltage selection signal VSP output from the odd-numbered PWM unit 2550 has an L level period to the right of the horizontal scanning period h2 (FIG. 1).
5). On the other hand, the voltage selection signal VSP output from the even-numbered PWM unit 2550 has an L level period to the left of the horizontal scanning period h2.

That is, the converted data Dt of (101)
And a PWM unit 2550 of the first stage (corresponding to the data signal X1) to which the odd-level signal SS of L level is supplied.
According to the PWM table shown in FIG. 9B, the voltage selection signal VSP that becomes H level in the first 5 periods of the horizontal scanning period h2 is divided into 7 and becomes L level in the remaining 2 periods. Output (Fig. 15
reference). On the other hand, the PWM unit 2550 at the second stage (corresponding to the data signal X2) to which the converted data Dt of (010) and the inverted odd-even signal / SS of H level are supplied,
According to the PWM table shown in FIG. 9A, a voltage selection signal VSP that has an L level during the first five periods of the seven horizontal scanning periods h2 and an H level during the remaining two periods is output. To do. As a result, as shown in FIG. 15, the voltage of the data signal X1 is -V.
The period of x is to the right of the horizontal scanning period h2, and the period of time of the voltage of the data signal X2 is -Vx is to the left of the horizontal scanning period h2. As described above, in the present embodiment, the voltage of the data signal is −Vx (or +).
Whether the period of Vx) is leftward or rightward with respect to one horizontal scanning period is alternately switched for each horizontal scanning period.

As described above, the horizontal scanning period h in the field 1f
Although the operation in 1 and h2 has been described, the same operation is executed in each of the subsequent third to 40th horizontal scanning periods h3 to h40. That is, in each horizontal scanning period, (1) the grayscale data D of the pixels for three rows is read from the frame memory 251 and (2) the bits of each position constituting each of these grayscale data D are arranged. Bit string and scan codes CY1, CY2 and CY
The respective bits are compared with the bit string corresponding to the level of 3, and the conversion data Dt corresponding to the number of disagreements of the bits obtained by this comparison are generated.
(3) A voltage selection signal VSP is generated in which the H level (or L level) period of the horizontal scanning period is determined according to the conversion data Dt, and (4) according to the voltage selection signal VSP. A data signal whose voltage + Vx or −Vx is determined is supplied to each signal electrode 212.

Further, similar processing is performed on the field f2, the fields f3 and f4 following the field f1. However, as described above, the scan code CY
Since 1, CY2 and CY3 change for each field, the conversion data Dt and the data signal generated based on this change for each field.
For example, in the field f2, the scan code CY
The levels of 1, CY2, and CY3 are L, H, and H levels (see FIG. 2A). Therefore, the field f
In the first horizontal scanning period h1 within 2, the bit string (011) corresponding to the scan code CY1, CY2, and CY3 and the same gradation as that read out in the first horizontal scanning period h1. The bit string of each bit of the data (three pixels) is compared. As a result, as shown in FIG. 13, in the horizontal scanning period, the first
The conversion data Dt of (100) is output to the PWM unit 2550 of the second stage, and the conversion data Dt of (001) is output to the PWM unit 2550 of the second stage.

Then, in the field f2, (10
When the converted data Dt of 0) is output, the PWM unit 2550 of the first stage outputs the PWM shown in FIG. 9B.
As a result of operating according to the table, the voltage of the data signal X1 becomes + Vx in the first four periods of the period obtained by dividing the horizontal scanning period into seven, as shown in FIG.
It becomes −Vx in the remaining three periods. Similarly, when the converted data Dt of (001) is output to the second-stage PWM unit 2550, the voltage of the data signal X2 is the first of the periods obtained by dividing the horizontal scanning period into seven, as shown in FIG. While it is −Vx in the six periods, it is + Vx in the remaining one period.

By repeating the above operation over the fields f1 to f4, the effective voltage value applied to the liquid crystal of each pixel in one frame becomes a value corresponding to the gradation data D. As a result, as shown in FIG. 14, gradation display according to the gradation data D is realized for each pixel.

Here, as shown in FIG. 15, in the field f1 (and f3), the odd-numbered signal SS becomes the H level in the odd-numbered horizontal scanning periods (h1, h3, ..., H39), and the even-numbered signal. Horizontal scanning period (h2, h
4, ... h40), the level becomes L level. On the other hand, in the fields f2 and f4, the odd signal S
S becomes L level during the odd-numbered horizontal scanning period and becomes H level during the even-numbered horizontal scanning period.
Therefore, in the fields f2 and f4, the relationship between the odd-numbered or even-numbered horizontal scan period and the leftward or rightward shift with respect to the horizontal scan period in the period in which the data signal has the voltage −Vx is the same in the fields f1 and f3. It will be the opposite of the relationship. For example, when focusing on the data signal X1, in the odd-numbered horizontal scanning period of the field f1 (and the field f3), the period of the voltage −Vx of the data signal X1 is leftward with respect to the horizontal scanning period. In the even-numbered horizontal scanning period, the period of the voltage −Vx of the data signal X1 is to the right of the horizontal scanning period. On the other hand, in the odd-numbered horizontal scanning period of the field f2 (and the field f4), the data signal X1
Of the voltage −Vx is to the right of the horizontal scanning period, while in the even-numbered horizontal scanning period,
The period in which the voltage of the data signal X1 is −Vx is leftward with respect to the horizontal scanning period.

As described above, in the present embodiment, the bit string consisting of each bit of the gradation data D corresponding to the three pixels to be simultaneously driven, and the scanning code C.
The number of mismatches of each bit with the bit strings corresponding to the levels of Y1, CY2, and CY3 is counted, and based on the number of mismatches, the PWM unit 25
The conversion data Dt used in 50 is generated. That is, according to the present embodiment, since the complicated arithmetic processing as shown in the conventional technique is unnecessary, it is possible to obtain the effects of reducing the circuit scale and speeding up the processing.

Focusing on one signal electrode 212, the data signal (and the voltage selection signal VSP) supplied to the signal electrode 212 is alternately switched to the right or left for each horizontal scanning period. Has become.
Therefore, when displaying with halftone, it is not necessary to change the polarity of the data signal at the boundary of each horizontal scanning period. That is, according to the present embodiment, the number of times the polarity of the data signal is switched can be reduced,
Low power consumption can be achieved.

Furthermore, in the present embodiment, the relationship between the odd-numbered or even-numbered horizontal scanning period and the rightward or leftward period during which the data signal becomes the ON voltage is switched for each field and for each frame. Therefore, it is possible to obtain the effect of preventing display unevenness and maintaining good display quality. Hereinafter, this effect will be described in detail.

For example, when the absolute value of the voltage applied to the liquid crystal in the period including the beginning of one horizontal scanning period is higher than the absolute value of the voltage applied to the liquid crystal in the period including the end of one horizontal scanning period. When it is low, a slight brightness difference occurs due to the effect of the waveform rounding or the change of the polarity of the data signal, and the result is recognized as display unevenness by the observer. On the other hand, in the present embodiment, FIG.
As shown in FIG. 4, right-justification and left-justification are switched every one field of the fields f1 to f4 and every one frame. Therefore, the absolute value of the voltage applied to the liquid crystal is averaged in each horizontal scanning period, and it is possible to suppress a slight brightness difference, and thus it is possible to suppress the occurrence of display unevenness due to this brightness difference. Of.

<C: Modification> Although one embodiment of the present invention has been described above, the above embodiment is merely an example, and various modifications can be made to the above embodiment without departing from the spirit of the present invention. Can be added. For example, the following may be considered as modifications.

<C-1: Modification 1> In the above embodiment, one frame is equally divided into four fields f1 to f4 and the selection for each scan electrode is dispersed in time. The application of the present invention is not limited to such a liquid crystal device. For example, a non-distributed driving method in which each selection is concentrated in time may be adopted. FIG. 16 is a timing chart showing the relationship between frames and fields in this non-dispersive driving method. As shown in this figure, in the non-dispersive driving method, the scan code CY1,
In order to switch between CY2 and CY3, the periods for selecting the three scan electrodes 312 are the fields f1, f2,
It will include f3 and f4. For example, at the beginning of one frame, counting from the top in FIG.
The three scan electrodes 312 up to the row are selected, and the fields f1 to f constituting this selected period are selected.
4 each, scan codes CY1, CY2 and C
The level of Y3 switches according to the scanning pattern. On the other hand, in the signal electrode drive circuit 250, in each of these fields f1 to f4, a sequence of reading the gradation data D, generating the conversion data Dt, generating the voltage selection signal VSP, and applying a voltage to the signal electrode 212 is performed. Will be performed. Further, as shown in FIG. 16, when the selection period of the scan electrodes 312 from the first row to the third row elapses, the selection of the scan electrodes 312 from the fourth row to the sixth row is subsequently started. To be done. Thereafter, the same operation is performed on the scan electrodes 31 on the 118th to 120th rows.
It is executed up to 2, and one frame is completed. That is, in the non-dispersive driving method,
When the three scan electrodes 312 are selected, the scan codes CY1, CY2, and CY3 are collectively switched.

<C-2: Modification 2> In the above embodiment, the relationship between the odd-numbered or even-numbered horizontal scanning period and the rightward or leftward period of the ON period of the data signal is switched for each frame. Although a case has been described as an example, the period as a unit of this switching may be two or more frames. For example, in the first and second frames (fifth and sixth frames, ...), odd-numbered or even-numbered horizontal scanning periods and the right side of the period in which the data signal is turned on or While the relationship with the left side is the same, this relationship may be reversed in the third and fourth frames (the seventh and eighth frames, ...). As described above, by switching the rightward or leftward for every two frames, it is possible to include a period in which the data signal is rightward or leftward in the period in which the selection voltage is positive, and a period in which the selection voltage is negative. Also in the above, since it is possible to include a period in which the data signal is shifted to the right or to the left, the display unevenness is further reduced.

In the above embodiment, the case where the leftward or rightward side of the data signal is switched for each signal electrode 212 has been described as an example, but the number of signal electrodes 212 serving as a unit for this switching may be two or more. For example, to the left or right of the data signal applied to the signal electrodes 212 of the first and second columns (the two signal electrodes 212 of the fifth and sixth columns, ...), Even if the data signals applied to the signal electrodes 212 of the second and fourth columns (the two signal electrodes 212 of the seventh and eighth columns, ...) Are reversed to the left or right. Good. Alternatively, the right side or the left side may be reversed for every ten signal electrodes 212. As described above, the number of signal electrodes 212, which is a unit for reversing rightward or leftward, is arbitrary. However, from the viewpoint of reducing display unevenness, the number of signal electrodes 212 on the right side of the data signal and the signal electrode 212 on the left side of the data signal.
It is desirable that the number of lines and the number of lines are almost the same.

<C-3: Modified Example 3> In the above-described embodiment, the case where the TN type or STN type liquid crystal is used is exemplified, but in addition to this, BTN (Bi-stable Twisted Nemati) is used.
c) type, bistable type having a memory property such as ferroelectricity, polymer dispersion type, and further a dye (guest) having anisotropy in absorption of visible light in the major axis direction and the minor axis direction of the molecule. It is also possible to use a guest-host type liquid crystal in which the dye molecules are arranged in parallel with the liquid crystal molecules by dissolving the compound in a liquid crystal (host) having a certain molecular arrangement. In addition, a configuration of vertical alignment (homeotropic alignment) in which liquid crystal molecules are arranged vertically to both substrates when no voltage is applied, while liquid crystal molecules are arranged horizontally to both substrates when voltage is applied The parallel (horizontal) alignment (homogeneous alignment) is that the liquid crystal molecules are aligned horizontally with respect to both substrates when no voltage is applied, while the liquid crystal molecules are aligned vertically with respect to both substrates when no voltage is applied. It may be configured. As described above, various liquid crystals and alignment methods can be used as long as they are compatible with the driving method of the present invention. Furthermore, the present invention can be applied to any of a transmissive liquid crystal device, a reflective liquid crystal device, and a transflective liquid crystal device that uses both of them.

<D: Electronic Equipment> Next, electronic equipment using the liquid crystal device according to the present invention will be described.

<D-1: Mobile Phone> Next, an example in which the liquid crystal device according to the present invention is applied to the display portion of a mobile phone will be described. FIG. 17 is a perspective view showing the configuration of this mobile phone. As shown in FIG.
In addition to the operation buttons 2102, the earpiece 210
4. With the mouthpiece 2106, the liquid crystal device 100 described above
Equipped with.

<D-2: Digital Still Camera> Next,
A digital still camera using the above-described liquid crystal device 100 as a finder will be described. FIG. 18 is a perspective view showing the back surface of this digital still camera. In contrast to a normal silver-salt camera, which exposes a film to an optical image of a subject, a digital still camera 2200 photoelectrically converts an optical image of the subject by an image pickup device such as a CCD (Charge Coupled Device) to generate an image pickup signal. To do.

Here, on the back surface of the case 2202 in the digital still camera 2200, the above-described liquid crystal device 1 is provided.
00 is provided, and display is performed based on the image pickup signal from the CCD. Therefore, the liquid crystal device 100
Will function as a viewfinder for displaying the subject.

A light receiving unit 2204 including an optical lens and a CCD is provided on the front surface side (back surface side in FIG. 18) of the case 2202. Here, when the photographer confirms the subject image displayed on the liquid crystal device 100 and presses the shutter button 2206, the image pickup signal of the CCD at that time is transferred and stored in the memory of the circuit board 2208. Further, in this digital still camera 2200, a video signal output terminal 2212 for external display and an input / output terminal 2214 for data communication are provided on the side surface of the case 2202.

As the electronic equipment, in addition to the mobile phone shown in FIG. 17 and the digital still camera shown in FIG. 18, a television, a viewfinder type / monitor direct-view type video tape recorder, and a car navigation device are used. ,
Examples include a pager, an electronic notebook, a calculator, a word processor, a workstation, a videophone, a POS terminal, and a device equipped with a touch panel. Needless to say, the liquid crystal device according to the present invention can be applied to the display unit of these various electronic devices. Further, in the above description, the electro-optical device is described as a liquid crystal device, but the present invention is not limited to this, and the electrophoretic device, electroluminescence (EL), digital micromirror device (DMD), Alternatively, it is needless to say that the present invention can be applied to an electro-optical device using various electro-optical elements that use plasma emission, fluorescence due to electron emission, and the like, and electronic equipment including the electro-optical device.

[0089]

As described above, according to the present invention,
The number of voltage levels of the data signal can be reduced and the process for generating the data signal can be simplified. In addition, it is possible to reduce power consumption and improve display quality.

[Brief description of drawings]

FIG. 1 is a block diagram showing an electrical configuration of a liquid crystal device according to an embodiment of the invention.

FIG. 2A is a timing chart showing an output state of a scan code by a scan pattern generation unit of the liquid crystal device, and FIG. 2B is a diagram showing a scan pattern used in the liquid crystal device.

FIG. 3 is a block diagram showing a configuration of a scan electrode driving circuit in the liquid crystal device.

FIG. 4 is a timing chart for explaining an operation of a shift register which forms a scan electrode driving circuit.

FIG. 5 is a block diagram showing a configuration of a signal electrode drive circuit in the liquid crystal device.

FIG. 6 is a timing chart for explaining an operation of reading gradation data in the signal electrode drive circuit.

FIG. 7 is a block diagram showing a configuration of a data conversion unit that constitutes a signal electrode drive circuit.

FIG. 8 is a block diagram showing a configuration of a PWM unit that constitutes a signal electrode drive circuit.

FIG. 9 is a diagram showing the contents of a PWM table used in the PWM unit.

FIG. 10 is a timing chart for explaining the operation of the PWM unit.

FIG. 11 is a timing chart for explaining the operation of the scan electrode driving circuit in the liquid crystal device.

FIG. 12 is a diagram showing an example of display contents of six pixels for explaining the operation of the liquid crystal device.

FIG. 13 is a diagram for explaining the operation of the conversion data output circuit in the signal electrode drive circuit.

FIG. 14 is a timing chart for explaining the operation of the liquid crystal device.

FIG. 15 is a timing chart for explaining the operation of the liquid crystal device.

FIG. 16 is a timing chart showing the relationship between frames and fields according to a modification of the present invention.

FIG. 17 is a perspective view showing a configuration of a mobile phone which is an example of an electronic apparatus to which the liquid crystal device according to the invention is applied.

FIG. 18 is a perspective view showing a configuration of a digital still camera which is an example of an electronic apparatus to which the liquid crystal device according to the invention is applied.

FIG. 19 is a diagram showing an expression used when gradation display is performed using the MLS driving method in the conventional technique.

[Explanation of symbols]

100 ... Liquid crystal device, 108 ... Scan code generator, 1
30 ... Pixel, 212 ... Signal electrode, 250 ... Signal electrode drive circuit, 251 ... Frame memory, 252 ... Row address generation section, 254 ... Converted data output circuit, 25
40 ... Data conversion unit, 2541 ... MSB comparison section, 2542 ... 2SB comparison section, 2543 ... LSB comparison section, 255 ... PWM circuit (voltage application circuit), 255
0 ... PWM unit, 2551 ... Counter, 255
2 ... Decoder, 257 ... Level shifter group (voltage application circuit), 258 ... Selector group (voltage application circuit), 31
2 ... Scan electrode, 350 ... Scan electrode driving circuit, 210
0: Mobile phone (electronic device), 2200: Digital still camera (electronic device).

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) G09G 3/20 641 G09G 3/20 641C 641E 641K 660 660N F term (reference) 2H093 NA51 NC11 NC13 NC22 NC29 NC34 ND06 ND39 ND60 NE03 NE10 NF05 NF06 NF11 NF13 NF17 5C006 AA14 AA16 AA17 AC13 AC21 AC23 AF42 BB12 BC03 BC11 BF14 FA45 FA56 GA03 5C080 AA10 BB05 DD30 EE29 FF12 GG10 JJ02 JJ04 KK43 KK47 KK47

Claims (15)

[Claims] 1. A driving method of a liquid crystal device, wherein a pixel corresponding to an intersection of a scanning electrode and a signal electrode is gradation-displayed on the basis of gradation data composed of a plurality of bits. According to the scanning pattern (n is an integer of 3 or more), three of the scanning electrodes are selected n times in one vertical scanning period, and in each selection, the three elements of the column of the scanning pattern corresponding to the selection are selected. A selection voltage corresponding to each of the three scan electrodes is applied to each of the three scan electrodes, and, in each of the selection periods in which the three scan electrodes are selected, depending on the element of the column corresponding to the selection in the scan pattern. And a plurality of bit strings formed by arranging bits of respective positions included in grayscale data of three pixels corresponding to the intersection of the signal electrode and the three scanning electrodes, and the comparison is made. In the result Corresponding converted data is generated, and the first voltage is applied to the signal electrode in a period having a time length corresponding to the converted data in the selection period, and is different from the first voltage in the remaining period. A method of driving a liquid crystal device, which comprises applying a second voltage to the signal electrode. 2. A bit string corresponding to an element of a column corresponding to the selection in the scanning pattern, a signal electrode and the three scanning electrodes in each of the selection periods for selecting the three scanning electrodes. A plurality of bit strings formed by arranging the bits of the respective positions included in the gradation data of the three pixels corresponding to the intersections are respectively compared, and the numbers of bits do not match (or the number of matches) obtained in each comparison. The method of driving a liquid crystal device according to claim 1, wherein a bit string formed by arranging bits is used as the conversion data. 3. The application period of the first voltage is a period near the start of the selection period and the application period of the second voltage is a period near the end of the selection period, or Whether the application period of the second voltage is set to a period near the start of the selection period and the application period of the first voltage is set to a period near the end of the selection period, the scan electrode is set to 3
The driving method of the liquid crystal device according to claim 1, wherein the switching is alternately performed for each period for selecting the books one by one. 4. The application period of the first voltage is a period near the start of the selection period and the application period of the second voltage is a period near the end of the selection period, or Whether the application period of the second voltage is set to a period near the start of the selection period and the application period of the first voltage is set to a period near the end of the selection period is selected n times for the three scan electrodes. 4. The method for driving a liquid crystal device according to claim 3, wherein the switching is alternately performed in each of the above. 5. The application period of the first voltage is set to a period near the start of the selection period and the application period of the second voltage is set to a period near the end of the selection period, or Whether the application period of the second voltage is set to a period near the start of the selection period and the application period of the first voltage is set to a period near the end of the selection period is alternated for each one or more of the vertical scanning periods. 4. The method for driving a liquid crystal device according to claim 3, wherein the method is switched to. 6. The application period of the first voltage is set to a period near the start of the selection period and the application period of the second voltage is set to a period near the end of the selection period, or Whether the application period of the second voltage is set to a period near the start of the selection period and the application period of the first voltage is set to a period near the end of the selection period is alternately set for each of the one or more signal electrodes. The method for driving a liquid crystal device according to claim 3, wherein the method is switched. 7. A drive circuit of a liquid crystal device for displaying a pixel corresponding to an intersection of a scanning electrode and a signal electrode on the basis of gradation data composed of a plurality of bits, the driving circuit having predetermined 3 rows and n columns. A scan electrode drive circuit for selecting three of the scan electrodes n times in one vertical scanning period according to a scan pattern (n is an integer of 3 or more), and each selection corresponds to the selection of the scan pattern. A scan electrode driving circuit that applies a selection voltage corresponding to each of the three elements in the column to each of the three scan electrodes, and a scan pattern of the scan pattern in each of the selection periods for selecting the three scan electrodes. A plurality of bit arrays corresponding to the elements of the column corresponding to the selection, and a plurality of bits arranged in the gray scale data of the three pixels corresponding to the intersection of the signal electrode and the three scanning electrodes. Bit of A conversion data output circuit that compares the columns with each other and outputs conversion data corresponding to the comparison result, and a first voltage is applied to the signal electrode in a period having a time length corresponding to the conversion data in the selection period. And a voltage applying circuit that applies a second voltage different from the first voltage to the signal electrode during the remaining period. 8. The conversion data output circuit, in each of the selection periods for selecting the three scan electrodes, a bit string corresponding to an element of a column corresponding to the selection in the scan pattern, the signal electrode, and A plurality of bit strings formed by arranging the bits of each position included in the grayscale data of the three pixels corresponding to the intersection of the three scan electrodes are compared with each other, and the number of mismatched bits obtained in each comparison ( 8. The drive circuit for a liquid crystal device according to claim 7, wherein a bit string formed by arranging bits corresponding to the number of coincidences) is output as the conversion data. 9. The voltage application circuit sets the application period of the first voltage to a period near the start of the selection period and sets the application period of the second voltage to a period near the end of the selection period. For each selection period, whether or not the application period of the second voltage is a period near the start of the selection period and the application period of the first voltage is a period near the end of the selection period 8. The drive circuit for a liquid crystal device according to claim 7, wherein the drive circuit is alternately switched to. 10. A liquid crystal device for displaying a gray scale of a pixel corresponding to an intersection of a scanning electrode and a signal electrode based on gray scale data composed of a plurality of bits, wherein a predetermined 3 rows and n columns (n is A scan electrode driving circuit that selects three of the scan electrodes n times in one vertical scanning period in accordance with a scan pattern of 3 or more). In each selection, 3 of the columns corresponding to the selection in the scan pattern are selected.
A scan electrode driving circuit that applies a selection voltage corresponding to each of the three elements to each of the three scan electrodes, and a selection period of the scan pattern in each of a selection period in which the three scan electrodes are selected. And a plurality of bit strings formed by arranging each bit included in the gradation data of three pixels corresponding to the intersection of the signal electrode and the three scanning electrodes. And a conversion data output circuit that outputs conversion data corresponding to the comparison result, and a first voltage is applied to the signal electrode in a period having a time length corresponding to the conversion data in the selection period. On the other hand, the liquid crystal device further comprises a voltage applying circuit for applying a second voltage different from the first voltage to the signal electrode in the remaining period. 11. A driving method of an electro-optical device, wherein a pixel corresponding to an intersection of a scanning electrode and a signal electrode is gradation-displayed on the basis of gradation data composed of a plurality of bits. According to a scanning pattern of a column (n is an integer of 3 or more), three of the scanning electrodes are selected n times in one vertical scanning period, and in each selection, three elements of a column corresponding to the selection in the scanning pattern are selected. While applying the selection voltage corresponding to each of the three scan electrodes to the elements of the column corresponding to the selection in the scan pattern in each of the selection periods for selecting the three scan electrodes. The corresponding bit string is compared with a plurality of bit strings formed by arranging the bits of each position included in the gradation data of the three pixels corresponding to the intersection of the signal electrode and the three scanning electrodes, and Comparison The conversion data corresponding to the result is generated, and the first voltage is applied to the signal electrode in a period having a time length corresponding to the conversion data in the selection period, while the first voltage is applied in the remaining period. A different second voltage is applied to the signal electrode. 12. A drive circuit of an electro-optical device which performs gradation display on a pixel corresponding to the intersection of a scanning electrode and a signal electrode based on gradation data composed of a plurality of bits. A scan electrode driving circuit that selects three of the scan electrodes n times in one vertical scanning period according to a scan pattern of a column (n is an integer of 3 or more), and each selection corresponds to the selection of the scan pattern. Row of 3
A scan electrode driving circuit that applies a selection voltage corresponding to each of the three elements to each of the three scan electrodes, and a selection period of the scan pattern in each of a selection period in which the three scan electrodes are selected. And a plurality of bit strings formed by arranging each bit included in the gradation data of three pixels corresponding to the intersection of the signal electrode and the three scanning electrodes. And a conversion data output circuit that outputs conversion data corresponding to the comparison result, and a first voltage is applied to the signal electrode in a period having a time length corresponding to the conversion data in the selection period. On the other hand, the drive circuit of the electro-optical device, further comprising: a voltage application circuit that applies a second voltage different from the first voltage to the signal electrode in the remaining period. 13. An electro-optical device that performs gradation display on a pixel corresponding to the intersection of a scanning electrode and a signal electrode based on gradation data composed of a plurality of bits, and has a predetermined 3 rows and n columns (n Is a integer of 3 or more), and is a scan electrode drive circuit that selects three of the scan electrodes n times in one vertical scanning period according to a scan pattern. Three
A scan electrode drive circuit that applies a selection voltage corresponding to each of the three elements to each of the three scan electrodes, and a selection period of the scan pattern in each of a selection period that selects the three scan electrodes. And a plurality of bit strings formed by arranging each bit included in grayscale data of three pixels corresponding to the intersection of the signal electrode and the three scanning electrodes. And a conversion data output circuit that outputs conversion data corresponding to the comparison result, and a first voltage is applied to the signal electrode in a period having a time length corresponding to the conversion data in the selection period. On the other hand, the electro-optical device comprising: a voltage application circuit that applies a second voltage different from the first voltage to the signal electrode in the remaining period. 14. An electronic apparatus comprising the liquid crystal device according to claim 10. 15. An electronic apparatus comprising the electro-optical device according to claim 13.