JP2003233348A - Liquid crystal driving circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent deterioration in resolution caused by disturbed display of video signals RGB on a poly-silicon TFT-LCD panel and erroneous writing of pixel signals. <P>SOLUTION: The liquid crystal driving circuit is provided with a phase detection circuit 59 for detecting a delay amount between a signal SHOUT outputted from a shift register circuit 41 formed on the poly-silicon TFT-LCD panel and a horizontal shift clock signal CKH, to detect an internal delay amount of the shift register 41 with accuracy, and judges signal phases of sample hold signals SHR, SHG, SHB for sample-holding pixel signals at the optimal timing according to the result of the detection. Thus, a control circuit 20 outputs the sample hold signals SHR, SHG, SHB to a sample hold circuit 30 at the optimal timing according to the result of the judgment. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal drive circuit, and more particularly to a polysilicon T formed on an LCD panel.
The present invention relates to a liquid crystal drive circuit including a phase detection circuit that detects an internal delay amount of an integrated circuit configured by FT and determines an optimum timing of a sample hold signal of a video signal.

[0002]

2. Description of the Related Art In a polysilicon TFT-LCD module, taking advantage of the fact that an integrated circuit can be formed on an LCD panel, an integrated circuit such as an X-direction driver and a Y-direction driver is formed on the panel, reducing external parts. And the miniaturization of the liquid crystal display module has been realized.

FIG. 5 shows a conventional polysilicon TFT-LC.
It is a figure which shows the structure of a D panel and its drive circuit. 1
Is a horizontal start signal STH that counts the reference clock signal CLK and indicates a display start timing corresponding to one horizontal display period (1H) of the video signal.
A sample hold signal SH for sample-holding the horizontal shift clock signal CKH and the video signals R, G, B
R, SHG, SHB are output. Reference numeral 2 denotes a sample hold circuit, which is composed of latches 21 to 25, and video signals R, G, and B are sequentially sampled in accordance with the sample and hold signals SHR, SHG, and SHB.
The sampled video signal is the signal ROU at the same time.
It is output as T, GOUT and BOUT. 3 is LC
D panel module, which has a horizontal start signal STH
The shift register circuit 31 for shifting the signal according to the horizontal shift clock signal CKH is formed of a polysilicon TFT. Then, in the shift register circuit 31, the horizontal start signal S is generated according to the horizontal shift clock signal CKH.
TH is shifted, and video signals ROUT and G are displayed on the pixels of the display section.
Write signals for writing OUT and BOUT are sequentially output as signals a, b, .... Then, in the display unit 32, for example, the pixels Ra, Ga, and Ba corresponding to the signal a are
The video signals ROUT, GOUT, and BOUT are simultaneously written in. Next, when the write signal b is output from the shift register circuit 31, the pixels Ra,
Pixels Rb, Gb, and Bb at pixel positions next to Ga and Ba
The video signals ROUT, GOUT, and BOUT are written in. In this way, the video signals ROUT, GOUT, and BOUT are sequentially written to the pixels in the horizontal direction, so that the video is displayed.

FIG. 6 is a diagram for explaining the operation of the sample hold circuit 2. In the sample and hold circuit 2, as shown in FIGS.
The signal B is sequentially input. When the H-level pulse of the sample hold signal SHR is input as shown in FIG. 6C, the signal R1 is sampled by the latch 21, for example. Next, when the H level pulse of the sample hold signal SHG is input as shown in FIG. 6C, the signal G1 is sampled by the latch 22. When the H-level pulse of the sample hold signal SHB is input as shown in FIG. 6, the signal B1 is sampled by the latch 35, and the signals R1 and G1 sampled by the latches 21 and 22 are latched. Sampled at 33 and 34. As a result, in the latches 33 to 35, the sampled signals R1, G1, and B1 are shown in FIG.
The output signals ROUT, GOUT and BOUT are simultaneously output as shown in FIG. Further, in the shift register circuit 31, when the horizontal start signal STH is shifted according to the signal CKH and, for example, the write signal a is output at the point d in FIG.
Signals ROUT, GOUT, and BOUT, which are image data R1, G1, and B1 at point d, are written to pixels Ra, Ga, and Ba, for example, with respect to one pixel configured with one set of dots. In addition, in the shift register circuit 31, as shown in FIG.
As shown in, the horizontal start signal STH is sequentially shifted according to the rising and falling of the signal CKH, and the horizontal signals ROUT and G are sequentially output to the pixels in the horizontal direction corresponding to the shift amount.
OUT and BOUT are written.

By the way, the operating frequency of a polysilicon TFT formed at a low temperature is generally about 3 MHz. The number of pixels in the horizontal direction of the liquid crystal panel is required to be 520 pixels or more as the resolution is increased. Here, as is well known, the horizontal frequency of TV broadcasting is about 15.7 KHz in the NTSC system, and the video display area period excluding the horizontal synchronizing period of one horizontal period is 50 μm.
The period is shorter than about sec. In order to display the video data on a liquid crystal panel having 520 or more horizontal pixels, the pixel clock for sequentially writing the video signals R, G, B has a frequency of 11 MHz or more, for example. The frequency of the pixel clock corresponds to the frequency of the reference clock signal CLK in FIG. Then, in order to realize the display for the number of pixels of 520 pixels or more in the X direction, the 3 pixels of the video signals RGB are simultaneously written on the liquid crystal panel as described above, so that the X direction driver formed on the liquid crystal panel. It corresponds to the operation speed of 1/3 slower. This frequency reduced to 1/3 speed is the frequency of the horizontal shift clock signal CKH. As a result, the RGB signals input to the liquid crystal panel are preliminarily sampled and held by the sample hold circuit 2 in the sample hold circuit 2 without reducing the resolution of the number of pixels in the X direction. Has been done.

[0006]

However, in the characteristics of the polysilicon TFT, the grains (grain boundaries) existing inside the polysilicon are small and the crystallinity is poor, and many levels are present at the insulating film interface or grain boundary. Due to the existence and high carrier barrier, the mobility of the TFT is low, that is, the operation delay is large. As a result, the polysilicon T
When the operation delay of the shift register circuit 31 configured by the FT is large, the shift register circuit is compared with the timing when the signals ROUT, GOUT, and BOUT output from the sample hold circuit 2 described above are transmitted to the pixels of the display unit 32. The delayed timing of the write signals a, b, ... For writing to the pixels of the LCD panel output from the reference numeral 31, for example, the write signal at the point d in FIG.
There is a problem in that the video signal to be written in the pixel position to be originally written is written in the pixel position to be originally written after the delay. Then, due to this problem, the display quality of the liquid crystal panel is deteriorated or the resolution is lowered.

Therefore, an object of the present invention is to detect the delay amount of the shift register circuit which generates the write signal of the video signal formed by the polysilicon TFT, and to perform the sample hold circuit at the optimum timing corresponding to the detection result. It is an object of the present invention to provide a phase detection circuit that determines the phase timing of a sample hold signal from which a video signal is output to a pixel of a display unit.

[0008]

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and is characterized in that a sample and hold circuit for sampling and holding a plurality of video signals and a first signal are sequentially shifted. Then, in a shift circuit that generates a drive signal for each shift operation and in a liquid crystal drive circuit that causes a liquid crystal to display a video signal sampled and held in a pixel on a liquid crystal screen, the delay signal of the shift circuit causes the first signal. A phase detection circuit for detecting a phase shift and a control circuit for controlling a sample hold timing of the sample hold circuit so as to remove the delay characteristic according to a detection signal of the phase detection circuit are provided.

Further, the control circuit selects a sample hold suitable for removing the phase shift based on the detection signal of the phase detection circuit from among a plurality of sample hold signals, and outputs it to the sample hold circuit. It is characterized by doing.

Further, the phase detection circuit is characterized by setting a plurality of detection periods and detecting a phase shift depending on which detection period the change of the output signal of the shift circuit enters.

Further, the control circuit detects the detection signal of the phase detection circuit a plurality of times, and selects a sample hold suitable for removing the phase shift based on the plurality of detection signals detected a plurality of times. , And outputs to a sample hold circuit.

Further, the phase detection circuit detects a phase shift generated in the first signal for each horizontal period, and the control circuit, after the power supply of the liquid crystal drive circuit is turned on, makes a plurality of continuous lines in a region other than the image display region. It is characterized in that a sample hold signal suitable for removing the phase shift is selected from the plurality of sample hold signals based on the plurality of detection signals of the horizontal period, and is output to the sample hold circuit.

Further, during the plurality of detection periods, a plurality of pulses each having a clock width of the reference clock signal are synchronized with rising and falling of the reference clock signal for generating the shift clock signal used for the shift operation of the shift circuit. It is characterized by consisting of phases.

As described above, according to the present invention, the horizontal shift clock signal CKH input to the shift register circuit formed by the polysilicon TFT formed on the LCD panel and the signal S output from the shift register circuit.
By detecting the phase difference with HOUT, the operation delay amount of the shift register circuit is detected, and the phase detection circuit for determining and outputting the timing of sampling and holding the video data of the sample and hold circuit according to the detection result is provided.
Since the sample hold circuit samples the video signal at the optimum timing, it is possible to reliably optimize the phase timing between the write signal and the pixel signal for writing the pixel data in the pixel of the display section.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be specifically described with reference to the drawings. FIG. 1 is a diagram showing the configuration of the phase detection circuit of the present invention. In FIG. 1, reference numeral 10 denotes a counter circuit which counts a reference clock signal CLK and generates a horizontal start signal STH and a horizontal shift clock signal CKH signal, and at the same time, timing signals SH1 to SH6 for sampling and holding a video signal. Is output. Also,
The counter circuit 10 detects the detection timing signal T synchronized with the rising and falling edges of the reference clock signal CLK.
As the A to TF signals, pulses having a width of 1 clock of the reference clock signal CLK are sequentially output in a cycle of 3 clocks of the reference clock signal CLK. Reference numeral 20 denotes a control circuit, which is timing signals SH1 to S output from the counter circuit 10.
Any of H6 is selectively output as sample hold signals SHR, SHG, SHB signals of the video signals R, G, B according to a determination output signal output from the determination circuit 54 described later. 30 is a sample and hold circuit, which is a latch 3
1 to 35, and according to the sample hold signals SHR, SHG and SHB output from the control circuit 20,
The video signals R, G, and B are sequentially sampled, and the sampled video signals are simultaneously signal RO.
It is output as UT, GOUT and BOUT. Reference numeral 40 denotes a polysilicon TFT-LCD module, which is a display unit 42 including a shift register circuit 41 and display pixels.
With. In the shift register circuit 41, the horizontal start signal STH output from the counter circuit 10 is sequentially shifted according to the horizontal shift clock signal CKH, and the write signals a, b ... For the pixels of the display section 42 are sequentially output. Further, in the shift register circuit 41, the horizontal start signal STH is sequentially shifted according to the horizontal shift clock signal CKH, and is output as the signal SHOUT from the final stage of the shift register circuit 41. Signal SHOUT
Is output at the timing when the horizontal start signal STH shifted by the horizontal shift clock signal CKH includes the operation delay of the shift register circuit 41. The shift amount of the shift register circuit 41 is, for example, (188 × 3).
+2) Assume that it is set to CLK. Further, in the display unit 42, for example, the signal a for the write signals a, b ... Which are sequentially output from the shift register circuit 41.
Is output, the signals ROUT, GOUT, B output from the sample hold circuit 30 are output to the pixels Ra, Ga, Ba.
OUT is written and the video is displayed.

Reference numeral 50 is a phase detection circuit, which is composed of a latch circuit 51, a first detection circuit, a second detection circuit and a determination circuit 54. The latch circuit 51 latches the signal SHOUT in synchronization with the rising edge of the reference clock signal CLK and outputs the latched signal as a signal SHOUT2. Further, in the latch circuit 51, the signal SHOU
T is latched in synchronization with the fall of the reference clock signal CLK, and the latched signal is the signal SHOU
It is output as T3. In the first detection circuit 52, the signal S
It is detected whether HOUT2 is latched in any pulse period of the detection timing signals TA, TB, TC. The second detection circuit 53 detects whether the signal SHOUT3 is latched in the pulse period of any of the detection timing signals TD, TE, and TF. The determination circuit 54 outputs any of the pattern signals PT1 to PT6 indicating the timing phase condition of the sample hold signal in accordance with the detection results of the first and second detection circuits.

Next, the operation of FIG. 1 will be specifically described with reference to the time charts of FIGS. First, if the internal delay of the shift register circuit 41 is ideally zero, the shift amount of the shift register circuit 51 is (188 × 3 + 2).
Since it is CLK, the signal SHOUT rises at point a shown in FIG. Then, the timing phase condition of the sample hold signal at this time is set to the pattern signal PT1. The sample hold signals SHR, SHG, and SHB corresponding to the pattern signal PT1 have the same timing as the sample hold signal used in the conventional drive circuit.
The timings of the timing signals SH1, SH3, and SH5 shown in FIGS.

Next, due to the operation delay of the shift register circuit 41, for example, at the point b shown in FIG. 3D, the output signal SHOUT near the rising edge of the reference clock signal CLK.
Will be described, and also with reference to FIG. 2 and the relationship between the rising and the clock signal CLK, the operation will be described. As shown in FIG. 2A, the signal SHO is generated near the rising edge of the reference clock signal CLK.
When UT rises, the latch circuit 51 latches the signal SHOUT in response to the rise of the reference clock signal CLK. When the rising edge of the signal SHOUT is earlier than the rising edge of the clock signal CLK as indicated by X in FIG. 2A, the signal SHOUT is increased as shown in FIG.
It is output as 2. Then, in the first detection circuit 52,
A signal A indicating that the signal SHOUT2 is latched by the latch circuit 51 during the pulse period of the timing signal TA is output.

Further, the latch circuit 51 latches the signal SHOUT in response to the fall of the reference clock signal CLK. Since the signal SHOUT rises near the rising edge of the clock signal CLK as indicated by X in FIG. 2A, the signal SHO can be stably stabilized as shown in FIG.
It is output as UT3. Then, the second detection circuit 53 outputs the signal D indicating that the signal SHOUT3 is latched by the latch circuit 51 during the pulse period of the timing signal TD.

Then, in the discrimination circuit 54, during the pulse period of the detection timing signals TA and TD, the signal SHO is output.
A signal A indicating that the UT has been latched by the latch circuit 51.
And D, between the r point and the t point from the signal SHOUT2,
Further, since it is between the s point and the u point from the signal SHOUT3, it is determined that the rising of the signal SHOUT has occurred within the period between the s point and the t point in FIG. 2, and the phase timing condition of the sample hold signal is set. The signal PT6 shown is output as shown in FIG.

When the signal PT6 is output, the control circuit 20
Then, as shown in the table of FIG. 4, the signals SH6, SH2 and S
H4 is selected as the sample and hold signals SHR, SHG and SHB, respectively, and the sample and hold signals SHR, SHG and SHB are selected as shown by the solid lines in FIG.
Is output.

As described above, the operation delay amount of the shift register circuit 41 constituted by the polysilicon TFT is determined by the phase detection circuit 50 by detecting the phase difference between the horizontal clock signal CKH and the signal SHOUT, and the shift register circuit is detected. The pixel signal write signals a, b, ...
Since T and BOUT are set in a stable state, the pixel signals ROUT, GOUT, and BOU can be reliably applied to the pixels at the pixel positions of the display section 42 corresponding to the write signals a, b, ....
T can write.

On the other hand, when the rising edge of the signal SHOUT is slower than the rising edge of the clock signal CLK as shown by Y in FIG. 2A, the signal SHOUT is shown as shown in FIG.
It is output as 2 '. Then, in the first detection circuit 52, the signal B indicating that the signal SHOUT2 ′ has been latched by the latch circuit 51 during the pulse period of the timing signal TB.
Is output.

The latch circuit 51 latches the signal SHOUT in response to the fall of the reference clock signal CLK. Since the signal SHOUT rises near the rising of the clock signal CLK as shown by Y in FIG. 2A, the signal SHOUT is stably latched and output as the signal SHOUT3 as shown in FIG.
Then, the second detection circuit 53 outputs a signal D indicating that the signal SHOUT3 is latched by the latch circuit 51 during the pulse period of the detection timing signal TD.

Then, in the discrimination circuit 54, during the pulse period of the detection timing signals TB and TD, the signal SHO is output.
A signal B indicating that the UT has been latched by the latch circuit 51.
And D from the signal SHOUT2 ′ between the points t and v, and from the signal SHOUT3 between the points s and u, the rising of the signal SHOUT occurs in the period between the points t and u in FIG. In addition to determining that the signal has been made, the signal PT1 indicating the phase timing condition of the sample hold signal is output as indicated by the broken line in FIG.

When the signal PT1 is output, the control circuit 20
Then, as shown in the table of FIG. 4, the signals SH1, SH3 and S
H5 is selected as the sample hold signals SHR, SHG and SHB, respectively, and the sample hold signals SHR, SHG and SHB are output at the timings shown by the broken lines in FIG.

Then, in the sample hold circuit 30,
The video signals R, G, B are sample hold signals SHR, S
Sampling is sequentially performed according to HG and SHB, and the sampled video signals are pixel signals ROUT and GOU.
T and BOUT are synchronized and simultaneously output.

When the rising timing of the signal SHOUT and the rising timing of the horizontal shift clock signal CKH are almost the same timing, the above-mentioned phase detection operation is executed a plurality of times, for example, five consecutive horizontal periods. Accordingly, the shift register circuit 41
It is possible to more accurately detect the operation delay of. For example, when the rising timing of the signal SHOUT is the point t shown in FIG. 2A, the latch circuit 51 also raises the signal SHOUT at the rising edge of the clock signal CLK, and thus the latch operation of latching the signal SHOUT at the rising edge of the signal CLK. The data setup time and the data hold time are zero, and a latch error occurs with the signal SHOUT2 or the signal SHOUT2 'every time the latch operation is performed. Therefore, the first detection circuit 52 detects the detection timing signal TA or TB each time the detection operation is performed.
The signal A or B indicating that the signal SHOUT has been latched is output during the pulse period.

Then, in the discrimination circuit 54, the signal S or the signal D indicating that the signal SHOUT has been latched by the latch circuit 51 in the pulse period of the detection timing signal TA or TB and the signal TD, and the signal S by the signal D.
From HOUT2 between r point and t point, or signal SHOUT
Since it is between t point and v point from 2 ′ and between s point and u point from the signal SHOUT3, it can be determined that the rising edge of the signal SHOUT occurs at about t point in FIG. As described above, when the rising edge of the signal SHOUT and the rising edge of the horizontal shift clock signal CKH are substantially the same, the phase timing condition of the sample hold signal may be the pattern PT6. As a result, with respect to the timing of the sample hold signals SHR, SHG and SHB and the timing of the write signals a, b ... Output from the shift register circuit 41, the video signal as shown in FIG. 6 is surely sampled and held. In this state, there is a phase relationship in which the video signals ROUT, GOUT, and BOUT can be reliably written in the pixels of the panel section 42.

Note that FIG. 4 shows the judgment result and the judgment condition of the timing phase of the sample and hold signal corresponding to the conditions detected by the first and second detection circuits 52 and 53. In the table, for example, the phase detection result is stable,
The signal S in the pulse period of the detection timing signals TB and TD
When the rising edges of HOUT2 and SHOUT3 are detected, the signal SHOUT rises between the points s and t in FIG. 2, so that the sample hold signals SHR, SHG, and SHB.
The optimum timing of the pattern PT1 is as shown in FIG.
It is determined that Further, in the phase detection result, the signal SHOUT is stable during the pulse period of the timing signal TB.
When the rising edge of 2 is detected and the rising edge of the signal SHOUT3 is detected during the pulse period of the detection timing signal TD or TE due to a latch error, the signal SHO is output.
Since the rising edge of UT is approximately at point u, it is determined that the optimum timing of the sample hold signals SHR, SHG, and SHB is the pattern PT2 shown in FIG.

As described above, with respect to one clock of the horizontal shift clock signal CKH from the counter circuit 10, the three-phase detection timing signals TA to TC and the fall of the reference clock signal CLK are synchronized with the rise of the reference clock signal CLK. Synchronized three-phase detection timing signals TD to T
Since the phase difference between the signal SHOUT and the signal CKH is detected by the first and second detection circuits 52 and 53 using the detection timing signals TA to TF having a total of 6 phases with respect to F, the signal SHOUT of the signal SHOUT is detected. The amount of delay can be reliably detected. As a result, the sample hold signals SHR, SHG, and SHB at the optimum timing are output from the control circuit 20, and in the sample hold circuit 30, the pixel signals ROUT, GOUT, and BOUT are output to the pixels of the display unit 42 from the shift register circuit 41. The sample hold output is performed at a timing suitable for the timing of writing by the output write signals a, b, ....

The operation of detecting the detection signals PT1 to PT6 of the phase detection circuit 50 of the present invention by the control circuit is performed during the period outside the image display area after the power supply of the liquid crystal drive circuit is turned on. The image displayed on the display unit 42 is not disturbed by switching the timing of the sample hold signal, and the sample hold signals SHR, SHG, and SH of the optimum sample hold timing are obtained.
The timing of B is selectively output from the control circuit 20.

The horizontal shift clock signal CKH is set to 1
Although the description has been given in the case where the reference clock signal CLK includes 6 clocks in the clock, it is not particularly limited to 6 clocks, and the reference clock signal CLK has a high frequency and is included in 1 clock of the signal CKH. It goes without saying that a more accurate phase difference between the horizontal shift clock signal CKH and the signal SHOUT can be detected by creating detection timing signals of 6 phases or more respectively synchronized with the rising and falling edges of the signal CLK.

[0034]

As described above, according to the present invention, the phase detection circuit 50 is provided, and the phase difference between the output signal SHOUT of the shift register circuit 41 formed by the polysilicon TFT and the shift clock signal CKH is detected, The timing at which the sample-hold circuit 30 performs the optimum sample-hold operation is determined, and the control circuit 20 determines the sample-hold signals SHR, SHG, and SHB according to the determination result.
Is output, a pixel signal corresponding to a display pixel position in the horizontal direction of the LCD panel can be written, and it is possible to reliably prevent a decrease in resolution due to erroneous writing of the pixel signal.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a phase detection circuit of the present invention.

FIG. 2 is a time chart showing a timing example for explaining the operation of the phase detection circuit of FIG.

FIG. 3 is a time chart for explaining the determination result and sample hold timing of the phase detection circuit of FIG.

FIG. 4 is a diagram showing a table for explaining an optimum timing determination of sample hold according to the present invention.

FIG. 5 is a diagram showing a configuration of a conventional sample hold signal generation circuit.

FIG. 6 is a time chart for explaining the timing of sample-holding the image data signals R, G, and B.

[Explanation of symbols]

10 Counter circuit 20 Control circuit 30 sample and hold circuit 40 Polysilicon TFT-LCD module 41 Shift register circuit 50 Phase detection circuit 51 Latch circuit 52 First Detection Circuit 53 Second detection circuit 54 Judgment circuit

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) G09G 3/20 670 G09G 3/20 670D F term (reference) 2H093 NA16 NC09 NC11 NC13 NC15 NC16 NC22 NC23 NC34 NC49 NC62 ND31 5C006 AA01 AA22 AF42 AF46 AF50 AF51 AF52 AF53 AF61 AF71 BB16 BC11 BC16 BC20 BF03 BF04 BF14 BF22 FA16 FA18 5C080 AA10 BB05 CC03 DD05 DD09 EE19 FF11 GG07 GG08 JJ02 JJ04

Claims (6)

[Claims] 1. A sample and hold circuit for sampling and holding a plurality of video signals, a shift circuit for sequentially shifting a first signal and generating a drive signal for each shift operation, and an image sampled and held by a pixel on a liquid crystal screen. In a liquid crystal drive circuit for displaying a signal on a liquid crystal, a phase detection circuit that detects a phase shift generated in the first signal due to a delay characteristic of the shift circuit, and the delay characteristic is removed according to a detection signal of the phase detection circuit. And a control circuit that controls the sample hold timing of the sample hold circuit. 2. The control circuit selects a sample hold suitable for removing the phase shift based on a detection signal of the phase detection circuit from a plurality of sample hold signals, and outputs the sample hold signal to the sample hold circuit. The liquid crystal drive circuit according to claim 1, wherein 3. The phase detection circuit sets a plurality of detection periods, and detects a phase shift depending on which detection period the change of the output signal of the shift circuit enters. 3. The liquid crystal drive circuit according to 1 or 2. 4. The control circuit detects a detection signal of the phase detection circuit a plurality of times and selects a sample hold suitable for removing the phase shift based on the plurality of detection signals detected a plurality of times. 4. The liquid crystal drive circuit according to claim 3, wherein the liquid crystal drive circuit outputs the sample hold circuit. 5. The phase detection circuit detects a phase shift that occurs in the first signal in each horizontal cycle, and the control circuit continuously outputs a plurality of areas in a region other than a video display region after the liquid crystal drive circuit is powered on. A sample hold signal suitable for removing the phase shift is selected from the plurality of sample hold signals based on a plurality of detection signals of a horizontal period, and is output to a sample hold circuit. Item 4. The liquid crystal drive circuit according to item 4. 6. The plurality of detection periods include a plurality of 1-clock-width pulses of the reference clock signal that are respectively synchronized with the rising and falling edges of the reference clock signal that generates the shift clock signal used for the shift operation of the shift circuit. The liquid crystal drive circuit according to claim 3, 4 or 5, wherein the liquid crystal drive circuit comprises a phase.