JP2003229465A - Electrical inspection system and inspection method for semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve efficiency in an inspection and to shorten inspection time by automatically selecting an optimum test program and performing the electrical inspection of a semiconductor device. <P>SOLUTION: Manufacture process information J1 is transmitted from a manufacture process host 11 to a wafer test host 21 and the wafer test host 21 refers to a correspondence chart 212, and decides a wafer specification code J2. The wafer test host 21 transmits the wafer specification code J2 to an electrical inspection device 22, and the electrical inspection device 22 selects a test program and then executes the electrical inspection. Since the test program suitable for the inspection of each semiconductor device is selected on the basis of the manufacture process information J1 and the electrical inspection is executed, the efficiency of the electrical inspection is improved, the inspection time is shortened and the burdens of the correction and alteration, etc., of the test program are reduced. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrical inspection technique that reflects manufacturing process information of a semiconductor device (hereinafter simply referred to as a wafer) in which a plurality of chips are formed on a wafer, and particularly, it is obtained from the wafer manufacturing process information. The present invention relates to an electric inspection system and an inspection method capable of automatically changing an electric inspection item and an inspection judgment standard according to wafer specification information.

[0002]

2. Description of the Related Art In manufacturing a semiconductor device, a semiconductor wafer is subjected to various processes such as formation of a photoresist mask, diffusion of impurities, film formation and etching to form a semiconductor device which becomes a plurality of chips on the wafer. (Hereinafter, referred to as a manufacturing process), a step of electrically inspecting a wafer on which a semiconductor device such as a chip is formed (hereinafter, referred to as an electrical inspection process) is performed.
In the manufacturing technology that performs an electrical inspection process on a wafer on which chips are manufactured by such a manufacturing process, various information obtained in the manufacturing process and past electrical inspections are performed in order to realize an appropriate electrical inspection. It is preferable to create a test program in the electrical inspection step based on the information obtained by the process.

FIG. 7 is a block process diagram for explaining a conventional manufacturing technique based on such requirements. The manufacturing process host 11 includes various devices (hereinafter, referred to as a manufacturing device group) 1 for executing the above manufacturing process.
A lot of manufacturing process information J1 when the wafer is manufactured in 2 is transmitted from the manufacturing device group 12. The semiconductor device manufacturing engineer collects the manufacturing process information J1 transmitted to the manufacturing process host 11 and analyzes the data (S301). Then, based on this data analysis, the contents of the test and the judgment standard performed in the wafer electrical inspection process are optimized (S30).
2) Then, an optimized test program is created (S303). Then, the wafer test host 21 transmits the test program to the electrical inspection apparatus 22 as a test program applied to the inspection of the target wafer, and stores it in the test program storage unit 224 of the electrical inspection apparatus 22. The electrical inspection device 22 uses the stored test program as the test program execution unit 223.
Read in, and the wafer inspection is executed based on this test program. Further, the test result information of the test executed by the electrical inspection device 22 is transmitted to the wafer test host 21, and the technician analyzes the data including the test result information in step S301 to review the test content. I am going to modify and revise the test program,
We are working to improve the manufacturing process capability and test accuracy.

As described above, in the conventional inspection technique, the test program created by the engineer is applied to all the wafers of the product group to which the same test program is applied. This means that the same test is performed regardless of the result of the manufacturing process. Therefore, when a test program is designed to optimize the test of products (wafers) that require high quality, However, the number of test items increases, which causes a problem that the test time is long. In particular,
Even if there are product types that can ensure high quality in the manufacturing process, the test program cannot be modified or revised unless the quality of other product types is ensured. Useless tests will be executed. In addition, in the conventional inspection technology, because the technician reviews the test program based on the test results, it takes time to create an appropriate test program for wafers with different product types, and the manufacturing process Will be delayed.

To solve this problem, Japanese Patent Laid-Open No. 2000-30
Japanese Patent No. 8151 proposes a technique for omitting a wasteful test in an inspection process. That is, information on each process of wafer manufacturing and pattern manufacturing is recorded in the production information table. Also, the test result obtained by the functional test, which is an electrical inspection of the wafer, is recorded in the production information table. Then, in the last repair operation, based on various information recorded in the production information table, by omitting some operations or performing specific operations before other operations, the efficiency of repair operations is improved. To increase the time and reduce the time.

[0006]

SUMMARY OF THE INVENTION In the technique of this publication,
Although a method has been proposed for omitting operations in repair operations by referring to the manufacturing information and test result information recorded in the production information table, no proposal has been made as to what kind of system should be used. . Therefore, when performing an operation omission or the like by referring to the information recorded in the production information table, it is considered that an engineer refers to the information and performs the operation such as omission of the operation in the repair operation. It is difficult to solve the problem in the prior art shown in FIG. Further, since the technology of the publication is a technology of omitting a part of a preset program or changing the order by referring to the information recorded in the production information table, wafers of different product types, that is, different test For each wafer to which the program is applied, it is necessary for the engineer to set an appropriate test program and execute the test in the relevant test program. It is difficult to shorten it.

An object of the present invention is to make it possible to automatically select a test program for wafers of different product types, and to execute an electrical inspection based on the selected test program, thereby making it possible to electrically test a semiconductor device. The present invention provides an electrical inspection system and an inspection method for improving inspection efficiency and shortening the time.

[0008]

An electrical inspection system of the present invention comprises a manufacturing process unit for manufacturing a semiconductor device and an electrical inspection process unit for electrically testing the manufactured semiconductor device. A means for obtaining manufacturing process information of the semiconductor device obtained at the time of manufacturing the semiconductor device, a means for setting a wafer spec code of the semiconductor device based on the manufacturing process information, and a means for setting the wafer spec code And means for selecting a test program in the electrical inspection process section.

For example, the manufacturing process section includes a manufacturing device for manufacturing the semiconductor device, an inspection device for checking characteristics of the manufactured semiconductor device and an appearance inspection, and manufacturing process information from the manufacturing device and the inspection device. And a manufacturing process host that acquires and transmits to the electrical inspection process unit, the electrical inspection process unit sets a wafer spec code of the semiconductor device based on the manufacturing process information transmitted from the manufacturing process information. A wafer test host for transmitting the data, and an electrical inspection device for selecting a test program corresponding to the transmitted wafer spec code and electrically inspecting the semiconductor device based on the selected test program. To do.

Alternatively, the manufacturing process section includes a manufacturing device for manufacturing a semiconductor device, an inspection device for checking the characteristics and appearance of the manufactured semiconductor device, and manufacturing process information from the manufacturing device and the inspection device. A manufacturing process host that acquires and sets the wafer spec code of the semiconductor device based on the manufacturing process information and sends the code to the electrical inspection process unit. A wafer test host that transmits the wafer spec code, and an electrical inspection device that selects a test program corresponding to the transmitted wafer spec code and electrically inspects the semiconductor device based on the selected test program. The configuration is provided.

Here, it is preferable that the electrical inspection apparatus is provided with means for storing a plurality of test programs in advance, and one of the test programs is selected based on the transmitted wafer spec code. Also,
The manufacturing process host or the wafer test host is provided with a correspondence table that defines a wafer spec code based on the manufacturing process information.

In addition, the inspection method of the present invention, the manufacturing process history information of the semiconductor device formed in the manufacturing process section,
Corresponding to a step of acquiring appearance inspection information and characteristic inspection information as manufacturing process information, a step of setting a wafer spec code of the semiconductor device from the manufacturing process information, and a wafer spec code set from a plurality of test programs. It is characterized in that a test program is selected and an electrical inspection of the semiconductor device is executed based on the test program. Here, the wafer spec code is set based on a correspondence table that associates the manufacturing process information with the wafer spec code. Also, in the electrical inspection,
Inspection items using the wafer spec code as a parameter
Select one of multiple test programs with different inspection order and inspection criteria.

According to the present invention, the wafer spec code for the wafer is determined based on the manufacturing process information of the manufactured wafer, and the test program for the electrical inspection is selected based on the wafer spec code. , While preparing multiple test programs in advance,
By setting the correspondence between each test program and the wafer spec code, the test program can be automatically selected without the technician's judgment and work, and the optimum test conditions for the wafer can be set. The test can be executed, and the inspection efficiency and time can be shortened.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION Next, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 shows the first of the present invention.
2 is a block configuration diagram of an electrical inspection system for realizing the electrical inspection method of the embodiment of FIG.
0 and an electrical inspection process unit 20. The manufacturing process unit 10 is a manufacturing facility including one or a plurality of manufacturing facilities such as a diffusion device, an etching device, and an exposure device, which are used in a manufacturing process for forming chips on a wafer not shown in the drawing. A group 12 is provided, and an appearance inspection device 13 for performing an appearance inspection on the wafers manufactured by the manufacturing equipment group 12 and a characteristic checker 14 for checking the characteristics of the manufactured wafers are provided. Then, the manufacturing facility group 12 and the appearance inspection device 1
3. The characteristic checker 14 is connected to the network line 1, and the manufacturing process host 15 is connected to the network line 1.

The appearance inspection apparatus 13 executes the appearance inspection of the manufactured wafer, and reports the inspection result to the manufacturing process host 11 via the network line 1. Also,
The characteristic checker 14 measures the electrical characteristics of the chip on the wafer and reports the measurement result to the manufacturing process host 11 via the network line 1. Further, the manufacturing facility group 12 reports the occurrence of the abnormality to the manufacturing process host 11 via the network line 1 when the abnormality occurs during the manufacturing process work. Manufacturing process host 11
In the manufacturing DB (database) 15 for these inspection results,
Stores manufacturing process information such as measurement results and abnormal conditions.

On the other hand, the electrical inspection process section 20 has the network line 1 connected to the manufacturing process section 10.
And an electrical inspection device 22 connected to the. As the electrical inspection device 22, here, a tester 23 that electrically inspects manufactured chips on a wafer, a prober 24 that is connected to the tester 23 to handle a wafer, and a collective acceleration in a wafer state are performed. It is assumed that a wafer level burn-in device 25 for testing is provided. A wafer test host 21 is connected to the electrical inspection device 22 via the network line 1. The wafer test host 21 notifies the electrical inspection apparatus, that is, the tester 23, the prober 24, and the wafer level burn-in apparatus 25 of the working conditions for performing the electrical inspection, and the tester 2
3. Receive reports of electrical inspection results from the prober 24 and the wafer level burn-in device 25. These electrical inspection results are stored in the wafer test DB (database) 26.

FIG. 2 is a block diagram showing the internal arrangements of the wafer test host and the electrical inspection apparatus, and the portions corresponding to those in FIG. 1 are designated by the same reference numerals. The wafer test host 21 communicates with or transfers files from the manufacturing process host 11 or directly from the wafer test DB 2
Manufacturing process information fetching means 211 for receiving the manufacturing process information J1 written in 6 and manufacturing process information for converting the received manufacturing process information J1 into a wafer spec code J2 as wafer spec information.
A wafer spec code correspondence table 212 (hereinafter referred to as a correspondence table) and a wafer for finally determining the wafer spec code J2 by associating the manufacturing process information J1 with the correspondence table 212 and transmitting the wafer spec code J2 to the electrical inspection apparatus 22. It has a spec code determination unit 213. Correspondence table 212
Are created by engineers registering conditions based on past wafer manufacturing rules of thumb

Further, the electrical inspection apparatus 22 receives the wafer spec code J2 transmitted from the wafer test host 21 and takes in the wafer spec code fetching section 221 for fetching it into the apparatus, and the fetched wafer spec code J2. A wafer spec code transfer unit 222 for delivering to the test program execution unit 223, and a test program selected or set based on the delivered wafer spec code J2, for actually executing the test program based on this test program. The test program execution unit 223 is provided. Further, the electrical inspection device 22 includes a test program storage unit 224, and a plurality of different test programs are stored in advance in the test program storage unit 224, and the test program execution unit 223 stores these test programs. Select the test program to be executed from the stored test programs.

A method of electrically inspecting a wafer by the electrical inspection system having the above configuration will be described with reference to the flowchart of FIG. First, in step S101, the wafer manufacturing process unit 10 uses the manufacturing apparatus group 12 to manufacture chips on the wafer. Here, if an abnormality occurs during the manufacturing process in the manufacturing apparatus group 12, the manufacturing apparatus group 12 reports the abnormality history to the manufacturing process host 11 according to steps S102, S103, and S104, and the manufacturing process host 11 manufactures the abnormality history D
Store in B15. Next, in the manufacturing process unit 10, the characteristic inspection of elements such as transistors is performed on the chips of the wafer manufactured in the characteristic checker 14 (S105), and the characteristic inspection result is the manufacturing process host 1
1 and is stored in the manufacturing DB 15 (S106,
S107). Further, the appearance inspection of the manufactured wafer is performed in the appearance inspection device 13, the inspection result is reported to the manufacturing process host 11, and stored in the manufacturing DB 15 (S
108, S109).

When the manufacturing and the inspection of the wafer are completed as described above, the manufacturing process host 11 sends the above-mentioned information stored in the manufacturing DB 15 via the network line 1, that is, the manufacturing process information J1 to the wafer test host 21. It is transferred to (S111). Communication means, file transfer, or direct writing to a database is used as this transmission means. Next, the wafer test host 21 compares the manufacturing process information J1 received from the manufacturing process host 11 with the correspondence table 212 of the wafer test host 21 to determine the wafer spec code for the product for which the manufacturing process is completed (S111). ).

FIG. 4 is an example of a correspondence table used in this embodiment. In this correspondence table, the manufacturing process information J1
A characteristic check result J11, a defective appearance rate J12, and a process abnormality report count J13 in the manufacturing apparatus are set.
Then, the wafer spec code J2 corresponding to the manufacturing process condition transmitted based on this correspondence table is obtained. For example, when the characteristic check result of the wafer is yield = 97.5%, defective appearance rate = 3%, and process abnormality report count = 0, the wafer spec code J2 of this wafer is “B”.

Referring again to FIG. 3, when the manufactured wafer is transferred to the electrical inspection apparatus and the electrical inspection is performed, the electrical inspection apparatus 22 is applied to the lot of the wafer.
Inquiries are made to the wafer test host 21 about the conditions for starting the inspection work. At this time, the wafer test host 21 recognizes the wafer spec code J2 required for the lot of the wafer, and the wafer spec code J2
Is transmitted to the electrical inspection device 22 (S112).
Upon receiving the wafer spec code J2 in the wafer spec code fetching unit 221, the electrical inspection apparatus 22 transfers the received wafer spec code J2 to the transfer unit 222.
To the test program execution unit 223. Then, in the test program execution unit 223, the test content and the judgment reference value are changed based on the transmitted wafer spec code J2, and the test program corresponding thereto is previously stored in the test program storage unit 224 of the electrical inspection apparatus 22.
Select from a plurality of test programs stored in, or a combination of a plurality of test programs, and further modify a part of the test programs to select as a test program that meets the conditions, and then A test is executed based on the selected test program (S113, S114).

FIG. 5 is a flow chart showing details of the test program selection / execution operation in step S114. As described above, the electrical inspection apparatus 22 inquires of the wafer test host 21 about the wafer spec code (S201), and when the wafer test host 21 sends the wafer spec code J2 (S202). ), This wafer spec code J2
Is selected, a test content corresponding to the recognized wafer spec code J2, a test program for a test result determination criterion is selected, or a combination of a plurality of test programs is selected, and the selected test program is activated (S203). Next, a test is executed, and at that time, the wafer spec code J2 is read as an argument (S
204), determine the branch within the test program.
For example, in the case of testing a wafer with a wafer spec code = “A”, the test contents when the wafer spec code = B is executed in step S205 (S206A), and the judgment criteria for the wafer spec code = “A” in step S207A. Determine the test result with. When testing a wafer having a wafer spec code = “B”, step S
At 205, the test content when the wafer spec code = B is executed (S206B), and at step S207B, the test result is judged by the judgment standard for the wafer spec code = “B”. After the test is completed, the test result of the chip to be measured is set in step S208. For example, if the test result of the chip CH1 of the wafer spec code “A” is non-defective, the chip CH1 = PASS = wafer spec: A
The determination result is added as information, and the electrical inspection apparatus holds this result. Then, steps S209 and S2
After performing the test on all the chips of the wafer in 10, the determination result is transmitted to the wafer test host 21 and the inspection work is completed as shown in FIG. 3 (S11).
5).

As described above, according to this embodiment, the wafer spec code for the wafer is determined based on the manufacturing process information of the manufactured wafer, and the test program for the electrical inspection is determined based on the wafer spec code. Since multiple test programs are prepared in advance and the correspondence between each test program and the wafer spec code is set in advance, the test program is automatically selected without being determined by an engineer or based on work. It is possible to perform the test under optimum test conditions for the wafer, and it is possible to improve the inspection efficiency and shorten the time. In addition, among the wafers manufactured in the manufacturing process, for poor quality products, the test standards can be relaxed by tightening the test standards or conversely lowering the product quality. Can be realized. In addition, this makes it possible to classify semiconductor products to be manufactured at the wafer inspection level before assembling them, and classify them into high-quality products and low-quality products in advance before assembling the semiconductor products. It becomes possible to do it.

FIG. 6 is a block diagram showing the configuration of the second embodiment of the present invention, and particularly showing the configurations of the manufacturing process host 11 and the wafer test host 21. The same parts as those in FIG. 2 are designated by the same reference numerals. In the above-described first embodiment, the correspondence table is provided in the wafer test host 21,
The wafer spec code is set based on the manufacturing process conditions from the manufacturing process host 11. However, in the present embodiment, the correspondence table 212 and the wafer spec code determination unit 213 are provided in the manufacturing process host 11, and the manufacturing device group 12 is provided.
When the manufacturing process information J1 is input from the above, the wafer spec code J2 is set in the manufacturing process host 11.
Is determined and the wafer spec code J2 is transmitted to the wafer test host 21. Therefore, the wafer test host 21 is provided with only the wafer spec code transmission unit 214.

According to the second embodiment, when a plurality of electrical inspection systems for performing a plurality of similar or different inspections are connected to one manufacturing process, a common manufacturing process host is used for each The wafer spec code can be transmitted to each of the electrical inspection system systems, which eliminates the need to provide a means for determining the wafer spec code in each wafer test host of each electrical inspection system, thereby improving the overall system configuration. It is advantageous for simplification.

[0027]

As described above, according to the inspection method using the electrical inspection system of the present invention, the wafer spec code for the wafer is determined based on the manufacturing process information of the manufactured wafer, and the wafer spec code is determined. Since the test program for electrical inspection is selected based on the code, the test program for performing the test under the optimum test conditions for the relevant wafer is automatically selected without the technician's judgment and work. The inspection efficiency can be improved and the time can be shortened.

[Brief description of drawings]

FIG. 1 is a block configuration diagram showing an overall configuration of a first embodiment of an inspection system of the present invention.

FIG. 2 is a block configuration diagram showing an internal configuration of a main part of FIG.

FIG. 3 is a flowchart illustrating an inspection method of the present invention.

FIG. 4 is a diagram showing an example of a correspondence table.

5 is a detailed flowchart of the main steps of the inspection method of FIG.

FIG. 6 is a block configuration diagram of a main part of a second embodiment of the inspection system of the present invention.

FIG. 7 is a diagram for explaining a conventional inspection method.

[Explanation of symbols]

10 Manufacturing Process Unit 11 Manufacturing Process Host 12 Manufacturing Device Group 13 Appearance Inspection Device 14 Characteristic Checker 15 Manufacturing DB (Database) 20 Electrical Inspection Process Unit 21 Wafer Test Host 22 Electrical Inspection Device 23 Tester 24 Prober 25 Wafer Level Burn-in Device 26 Wafer test DB (database) 211 Manufacturing process information fetching means 212 Manufacturing process information-wafer spec code correspondence table 213 Wafer spec code determination section 214 Wafer spec code transmission section 221 Wafer spec code fetch section 223 Test program execution section 224 Test program storage section J1 Manufacturing process information J2 Wafer spec code

Claims (8)

[Claims] 1. A semiconductor manufacturing process unit for manufacturing a semiconductor device, and an electrical inspection process unit for electrically inspecting the manufactured semiconductor device. The semiconductor device obtained at the time of manufacturing the semiconductor device. Means for obtaining manufacturing process information of the device, means for setting a wafer spec code of the semiconductor device based on the manufacturing process information, and a test program in the electrical inspection process unit based on the set wafer spec code. An electrical inspection system for a semiconductor device, comprising: selecting means. 2. The manufacturing process unit includes a manufacturing apparatus for manufacturing the semiconductor device, an inspection apparatus for performing a characteristic check and an appearance inspection of the manufactured semiconductor device, and the manufacturing apparatus and the inspection apparatus. A manufacturing process host for acquiring process information and transmitting the process information to the electrical inspection process unit, wherein the electrical inspection process unit includes a wafer of the semiconductor device based on the manufacturing process information transmitted from the manufacturing process information. Select a wafer test host that sets and sends the spec code, and a test program that corresponds to the sent wafer spec code,
The electrical inspection system for a semiconductor device according to claim 1, further comprising: an electrical inspection device that electrically inspects the semiconductor device based on the selected test program. 3. The manufacturing process unit includes a manufacturing apparatus for manufacturing the semiconductor device, an inspection apparatus for performing a characteristic check and an appearance inspection of the manufactured semiconductor apparatus, and the manufacturing apparatus and the inspection apparatus. A manufacturing process host that acquires process information, sets a wafer spec code of the semiconductor device based on the manufacturing process information, and transmits the wafer spec code to the electrical inspection process unit, wherein the electrical inspection process unit includes: A wafer test host that transmits the wafer spec code transmitted from the manufacturing process information and a test program corresponding to the transmitted wafer spec code are selected, and electrical inspection of the semiconductor device is performed based on the selected test program. The semiconductor device according to claim 1, further comprising: Inspection system. 4. The electrical inspection apparatus comprises means for storing a plurality of test programs in advance, and any one of the test programs is selected based on the transmitted wafer spec code. Item 2 or 3
An electrical inspection system for a semiconductor device according to. 5. The manufacturing process host or the wafer test host is provided with a correspondence table that defines the wafer spec code based on the manufacturing process information. Inspection system for semiconductor devices. 6. A process of obtaining manufacturing process history information, appearance inspection information, and characteristic inspection information of a semiconductor device formed in a manufacturing process section as manufacturing process information, and a wafer spec code of the semiconductor device from the manufacturing process information. A step of setting and a test program corresponding to the set wafer spec code is selected from a plurality of test programs, and an electrical inspection of the semiconductor device is executed based on the test program. Equipment inspection method. 7. The method for inspecting a semiconductor device according to claim 6, wherein the wafer spec code is set based on a correspondence table that associates the manufacturing process information with the wafer spec code. 8. In the electrical inspection, any one of a plurality of test programs having different inspection items, inspection orders, and inspection determination criteria is selected using the wafer spec code as a parameter. A method for inspecting a semiconductor device according to.