JP2003224466A - Current-mode inverter - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a current-mode inverter which consumes less power, does not require a bias voltage generating circuit which generates a special bias voltage, and operates at high speed. <P>SOLUTION: This current-mode inverter is provided with a first PMOS transistor 11 and a first NMOS transistor 12, arranged in series between a source voltage VDD of 1.0 V and a ground GND, and a second NMOS transistor 13 mirror-configured with the NMOS transistor 12. The current-mode inverter 10 inputs a current Iin flowing out from a junction point 14, and outputs a current Iout which flows into the NMOS transistor 13. The gate of the PMOS transistor 11 is kept at a ground level by the control circuit 15, at least when operation is performed. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a current mode inverter adopting a CMOS process.

[0002]

2. Description of the Related Art Conventionally, a current mode logic circuit (Current-Mode Lo) adopting a CMOS process is used.
gic circuit: hereinafter referred to as a CML circuit) is known. One of the CML circuits is a current mode inverter. In addition to the CML circuit, a voltage-mode logic circuit (Voltage-Mode Logic Ci) adopting a CMOS process, which is currently the mainstream, is adopted.
rcuit: hereinafter referred to as VML circuit). C
The ML circuit is different from the VML circuit in the following points. (1) The CML circuit has a configuration in which a constant current is supplied by a current load source. Therefore, a large instantaneous current is not generated during switching in the VML circuit. (2) Mixed mixed digital circuit that handles digital signals and analog circuit that handles analog signals
In the Signal IC, the switching current on the digital circuit side becomes a main noise source flowing into the analog circuit side through the circuit board. Compared to the VML circuit, the CML circuit does not generate an instantaneous current as described above, and thus can greatly contribute to the improvement of accuracy on the analog circuit side in the Mixed-Signal IC and the simplification of design. (3) Since the CML circuit is configured to pass a constant current, the power consumption is constant regardless of the operating frequency. On the other hand, VML
In a circuit, its power consumption is proportional to the operating frequency. Therefore, the power consumption of the CML circuit is lower than that of the VML circuit at a predetermined operating frequency or higher. The VML circuit can be put in a standby state by stopping the clock.

Now, a current mode inverter, which is one of the CML circuits, will be described.

FIG. 5 is a diagram showing the configuration of a conventional current mode inverter.

The current mode inverter 10 shown in FIG.
0 is the first PM arranged in series between the power supply V _DD (2.5 V) and the ground GND, in order from the power supply V _DD side.
An OS transistor 11 (PMOS current source) and a first NMOS transistor 12 are provided.

Further, the current mode inverter 10
0 has one end connected to the ground GND and the gate connected to the first PMOS transistor 11 and the first NM.
The connection point 14 between the OS transistor 12 and the first N
A second NMOS transistor 13 connected to both the gate of the MOS transistor 12 is provided. Here, the first and second NMOS transistors 12 and 13
Is configured as a current mirror, and these first and second
The current ratio (mirror ratio) of the NMOS transistors 12 and 13 is 1: α (1 <α).

Further, the current mode inverter 1
00 includes a bias voltage generation circuit 101 for applying a predetermined bias voltage Vbias (here, 1.5 V) to the gate of the first PMOS transistor 11.

The current mode inverter 100 is
It is formed by a CMOS process of 0.25 μm, the threshold voltage Vtp of the first PMOS transistor 11 is −0.62 V, for example, and the threshold voltage Vtn of the second and third NMOS transistors 12 and 13 is set. Is 0.
It is 43V. Hereinafter, the current mode inverter 100
The operation of will be described.

A power supply voltage V _{DD of} 2.5 V is applied to the current mode inverter 100, and a bias voltage Vbia of 1.5 V from the bias voltage generation circuit 101 is applied to the gate of the first PMOS transistor 11.
s is applied. Then, the first PMOS transistor 11 is turned on and operates in the saturation region, whereby a predetermined current Ib flows through the first PMOS transistor 11. Here, when the predetermined current Ib flows out as the current Iin (logic 0), the current does not flow into the gates of the first and second NMOS transistors 12 and 13, so that the second NMOS transistor 13 is finally supplied. The current Iout flowing in is 0 (logic 1).

On the other hand, when the current Iin is 0 (logic 1),
The predetermined current Ib flows into the gates of the first and second NMOS transistors 12 and 13. Where the first and second
Since the current ratio of the NMOS transistors 12 and 13 is 1: α, the first NMOS transistor 13 has
The current Iout, which is α times the current flowing through the NMOS transistor 12, flows in (logic 0). In this way, the current mode inverter 100 has the connection point 14
The current Iin flowing out from the input is used as an input, and the current Iout flowing into the second NMOS transistor 13 is used as an output to operate as an inverter.

[0011]

As described above, the conventional current mode inverter 100 has the first PMOS.
Since the predetermined current Ib is always supplied to the transistor 11, there is a problem that the power consumption is relatively large. In addition, a special bias voltage V for flowing a predetermined current Ib
A bias voltage generation circuit 101 for generating bias (here, 1.5 V) is also required.

In view of the above circumstances, it is an object of the present invention to provide a current mode inverter which is low in power consumption, does not require a bias voltage generation circuit for generating a special bias voltage, and operates at high speed. To do.

[0013]

A current mode inverter of the present invention that achieves the above object is a first PMO arranged in series between a power source and a ground, in order from the power source side.
An S transistor and a first NMOS transistor,
One end is connected to ground and the gate is connected to the first P
A second NMOS transistor connected to both the connection point between the MOS transistor and the first NMOS transistor and the gate of the first NMOS transistor is provided, and the current flowing out from the connection point is used as an input. In the current mode inverter which outputs the current flowing into the second NMOS transistor, the first P
When the gate of the MOS transistor is at least operating,
It is characterized by being held at the ground level.

In the current mode inverter of the present invention, since the gate of the first PMOS transistor is held at the ground level at least during operation, the first PMOS transistor is operated at the first level. It suffices to apply a relatively low power supply voltage to the PMOS transistor, so that the current flowing through the first PMOS transistor can be relatively small, and low power consumption is achieved. Further, a bias voltage generation circuit for applying a special bias voltage to the gate of the first PMOS transistor is unnecessary. Further, in operating the first PMOS transistor, as described in the embodiments described later, the first PMOS transistor can be operated in the linear region, and therefore, the amplitude of the operating voltage can be suppressed to be small, and high-speed operation can be realized.

Here, the potential at the connection point is Vin,
When the absolute value of the threshold voltage of the first PMOS transistor is set to | Vtp |, it is preferable that the relationship of Vin ≧ | Vtp | be satisfied at at least a part of the timing during operation.

When such a relationship is satisfied, the first PMO
The operating region of the S-transistor can be a linear region as well as a saturation region.

Further, the absolute value of the threshold voltage of the first PMOS transistor is set to | Vtp |, and the threshold voltages of the first and second NMOS transistors are set to Vtn.
Then, it is also a preferable embodiment that the relationship of Vtn <| Vtp | is satisfied.

When such a relationship is satisfied, the first PMO
Both the S transistor and the first and second NMOS transistors configured as a current mirror can be simultaneously operated in the saturation region.

Further, a control circuit for holding the voltage of the gate of the first PMOS transistor at the ground level during operation and holding it at the power supply voltage during standby may be provided.

With such a control circuit, the first PMOS transistor is turned off during standby,
The power consumption can be further reduced. Further, for example, in an IC in which a CML circuit incorporating the current mode inverter of the present invention and a VML circuit are mixed, the clock of the VML circuit is stopped and the first PMOS transistor is turned off by the control circuit during standby. You can Therefore, the affinity with the VML circuit can be increased.

[0021]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below.

FIG. 1 is a circuit diagram showing an embodiment of the current mode inverter of the present invention.

The same components as those of the current mode inverter 100 shown in FIG. 5 will be described with the same reference numerals.

The current mode inverter 10 shown in FIG.
In comparison with the current mode inverter 100 shown in FIG. 5, a relatively low power supply voltage V _DD (1.0 V) is applied instead of the power supply V _DD of 2.5 V.

The current mode inverter 10
Holds the voltage of the gate of the first PMOS transistor 11 at the ground level (0V = GND) during operation, and supplies the power supply voltage V _{DD of} 1.0V during standby.
And a control circuit 15 for holding the same. In this way, during operation, the voltage of the gate of the first PMOS transistor 11 is held at the ground level and the power supply voltage V _DD is suppressed to a low level, whereby low power consumption and high-speed operation described later are achieved. Both are realized. In the standby mode, the voltage of the gate of the first PMOS transistor 11 is held at the power supply voltage V _{DD of} 1.0 V, thereby
The same standby state as when the clock of the MI circuit is stopped is realized. Therefore, further reduction in power consumption can be achieved. Here, the control circuit 15 may be controlled so as to hold the ground level and the power supply voltage V _DD . Therefore, the control circuit 15 has a simple configuration, and the conventional bias voltage generation circuit 101 for generating a special bias voltage (see FIG. 5) is unnecessary and the cost can be reduced.

Here, the first PMOS transistor 11
The following relations are satisfied in order to set the operation region of (1) to the linear region as well as the saturation region. That is, the first PMO
S transistor 11 and first NMOS transistor 12
The potential of the connection point 14 of the above is Vin, and the absolute value of the threshold voltage Vtp of the first PMOS transistor 11 is | Vtp
When |, the relationship of Vin ≧ | Vtp | is satisfied at least at some timings during operation. Here, Vtp is the first P
The threshold voltage of the MOS transistor 11 (for example, −
0.62V).

Further, in the current mode inverter 10 of the present embodiment, the first PMOS transistor 11 and the first and second NMOSs formed by the current mirror structure.
In order to operate both the transistors 12 and 13 in the saturation region at the same time, the absolute value of the threshold voltage of the first PMOS transistor 11 is set to | Vtp | and the first and second NMs are set.
When the threshold voltage of the OS transistors 12 and 13 is Vtn, the relationship of Vtn <| Vtp | is satisfied. Here, Vtn is a threshold value (for example, 0.43 V) of the first and second NMOS transistors 12 and 13.

FIG. 2 is a graph showing the delay time of the current mode inverter shown in FIG. 1 with respect to the change in bias voltage Vbias.

In this graph, the bias voltage Vbias is changed from 1.5V to 0V while the relationship between the power supply voltage _VDD and the bias voltage Vbias is kept constant (power supply voltage _VDD -bias voltage Vbias = 1.0V). The delay time tp in the case of making it is shown. Here, the delay time t
p is represented as tp = 1 / (N × f _N ), where f _N is the oscillation frequency of the ring oscillator including the N-stage current mode inverter 10.

As shown in this graph, the power supply voltage V _DD −
When the bias voltage Vbias is lowered while keeping the bias voltage Vbias = 1.0V, the delay time tp becomes small. That is, the current mode inverter 10 operates at high speed. The reason for this will be described later.

FIG. 3 shows the current I of the current mode inverter shown in FIG. 1 with respect to the change of the bias voltage Vbias.
It is a graph which shows change of b.

In this graph, the bias voltage Vbias is varied from 1.5V to 0V while the relationship between the power supply voltage _VDD and the bias voltage Vbias is kept constant (power supply voltage _VDD -bias voltage Vbias = 1.0V). Average value Iave (solid line A) of current Ib and current Ib
Maximum fluctuation value Ipp of b (Peak-to-Peak value;
The solid line B) is shown.

As is clear from this graph, when the bias voltage Vbias is lowered, the current I as shown by the solid line A is obtained.
The average value Iave (current consumption) of b decreases. On the other hand, the maximum fluctuation value Ipp (noise component) of the current Ib indicated by the solid line B
Will increase. Therefore, in the current mode inverter 10 of the present embodiment to which the bias voltage Vbias of 0V is applied, the noise component increases but the current consumption is suppressed to a small value.

FIG. 4 is a graph showing changes in power consumption and power consumption × delay time of the current mode inverter shown in FIG. 1 with respect to changes in bias voltage Vbias.

In this graph, the bias voltage Vbias is changed from 1.5V to 0V while the relationship between the power supply voltage _VDD and the bias voltage Vbias is kept constant (power supply voltage _VDD -bias voltage Vbias = 1.0V). The power consumption (solid line A) and the power consumption × delay time (power consumption delay time product; solid line B) in the case of being set are shown.

Power supply voltage _VDD -bias voltage Vbias =
If the bias voltage Vbias is lowered while maintaining 1.0V, the average value Iave of the current Ib shown in FIG.
The power consumption (solid line A) decreases as the (current consumption) decreases. Further, the delay time shown by the solid line B also decreases. Since the bias voltage Vbias of 0 V and the power supply voltage V _{DD of} 1.0 V are applied to the current mode inverter 10 of the present embodiment, the effect of reducing the consumption current and the power supply voltage V _{DD are obtained.}
The power consumption is significantly reduced due to both of the effect of reducing the power consumption.

Table 1 shows data in the current mode inverter 10 of this embodiment.

[0038]

[Table 1]

As is clear from Table 1, the power supply voltage V
_{The combination of DD} = 1.0V and bias voltage Vbias = 0V (ground level) enables the current mode inverter 10 to achieve both low power consumption and high speed operation. Here, as compared with the combination of the power supply voltage V _DD = 2.5V and the bias voltage Vbias = 1.5V,
The current Ipp increases about 2.5 times (0.8 μA → 2.
1 μA), the current Ipp of 2.1 μA is
Since it is several tens of times smaller than the current Ipp of the VML circuit, there is no problem in noise characteristics.

In this embodiment, the power supply voltage V _DD = 1.0
In the combination of V and the bias voltage Vbias = 0V, the first PMO is the factor that increases the current Ipp.
This is because the S transistor 11 is operated in the linear region (conventionally, the first PMOS transistor 11 is operated in the saturation region as described with reference to FIG. 5). However, when operated in the linear region, the connection point 14
Since the differential voltage ΔVin (logic voltage amplitude) between logic 1 and 0 at the node is as small as 217 mV, high-speed operation is realized.

[0041]

As described above, according to the present invention,
It is possible to provide a current mode inverter that achieves low power consumption, does not require a bias voltage generation circuit that generates a special bias voltage, and operates at high speed.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a current mode inverter of the present invention.

FIG. 2 is a graph showing a delay time with respect to a change in bias voltage Vbias of the current mode inverter shown in FIG.

3 is a graph showing changes in current Ib with respect to changes in bias voltage Vbias of the current mode inverter shown in FIG. 1. FIG.

4 is a graph showing changes in power consumption and power consumption × delay time with respect to changes in bias voltage Vbias of the current mode inverter shown in FIG. 1. FIG.

FIG. 5 is a diagram showing a configuration of a conventional current mode inverter.

[Explanation of symbols]

10 Current mode inverter 11 First PMOS transistor 12 First NMOS transistor 13 Second NMOS transistor 14 connection points 15 Control circuit

Continued front page    F term (reference) 5F038 DF08 DF17 EZ08 EZ20                 5J055 AX02 AX12 BX17 CX27 DX22                       DX65 DX73 EX07 EY21 EZ00                       EZ04 EZ51 FX20 GX01 GX02                       GX06                 5J056 AA03 BB02 BB17 CC00 CC02                       CC04 DD13 DD28 EE06 FF06                       FF08 GG04 KK03

Claims (4)

[Claims] 1. A first PMOS transistor and a first NMOS transistor, which are arranged in series between a power source and a ground, in order from the power source side, one end of which is connected to the ground, and a gate of which is connected to the first P transistor.
A second NMOS transistor connected to both a connection point between the MOS transistor and the first NMOS transistor and a gate of the first NMOS transistor, and using a current flowing out from the connection point as an input; The second NM
A current mode inverter that outputs a current flowing into an OS transistor, wherein the gate of the first PMOS transistor is held at a ground level at least during operation. 2. The absolute value of the threshold voltage of the first PMOS transistor is |, where Vin is the potential of the connection point.
The current mode inverter according to claim 1, wherein, when Vtp | is set, a relationship of Vin ≧ | Vtp | is satisfied at least at a part of timing during operation. 3. When the absolute value of the threshold voltage of the first PMOS transistor is | Vtp | and the bias voltage of the first and second NMOS transistors is Vtn, the relationship of Vtn <| Vtp | The current mode inverter according to claim 1 or 2, characterized in that: 4. A current control circuit according to claim 1, further comprising a control circuit for holding the voltage of the gate of the first PMOS transistor at the ground level during operation and holding it at the power supply voltage during standby. Mode inverter.