JP2003224216A - Stacked electronic chip - Google Patents

Stacked electronic chip

Info

Publication number
JP2003224216A
JP2003224216A JP2002020117A JP2002020117A JP2003224216A JP 2003224216 A JP2003224216 A JP 2003224216A JP 2002020117 A JP2002020117 A JP 2002020117A JP 2002020117 A JP2002020117 A JP 2002020117A JP 2003224216 A JP2003224216 A JP 2003224216A
Authority
JP
Japan
Prior art keywords
marking
chip
iii
electronic component
type electronic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2002020117A
Other languages
Japanese (ja)
Inventor
Mototsugu Shiga
元次 志賀
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toko Inc
Original Assignee
Toko Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toko Inc filed Critical Toko Inc
Priority to JP2002020117A priority Critical patent/JP2003224216A/en
Publication of JP2003224216A publication Critical patent/JP2003224216A/en
Pending legal-status Critical Current

Links

Abstract

<P>PROBLEM TO BE SOLVED: To provide a stacked electronic chip in which the efficiency of securing the direction of products can be enhanced by preventing detrimental judgment errors in deciding the chip direction. <P>SOLUTION: Upper and lower surfaces [iii] and [iv] of a chip 11 constituting a stacked electronic chip are applied, respectively, with a first marking MK1 and a second marking MK2 of difference shape with a color different definitely from that of the first and second side faces [i] and [ii] of the chip body 11. The first marking MK1 occupies a part of the upper surface [iii] with a smaller area than that of the upper surface [iii] and is applied to a position shifted to the rear surface [vi] side of the upper surface [iii]. On the other hand, the second marking MK2 is applied to cover the entire surface of the lower surface [iv]. <P>COPYRIGHT: (C)2003,JPO

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、積層チップ型電子
部品の向き(方向)の誤判定を防止するための技術に関
し、詳細には積層チップ型電子部品に施すマーキングの
形態に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for preventing an erroneous determination of the orientation (direction) of a laminated chip type electronic component, and more particularly to a form of marking applied to the laminated chip type electronic component.

【0002】[0002]

【従来の技術】近年、電子機器で扱われる信号の周波数
が高周波化し、これに伴って電子部品の小型化が一層進
展した。例えばインダクタやコンデンサ、あるいはそれ
らの応用素子は、積層型電子部品の形態とすることによ
り、極めて小さなチップサイズにて製品化されるように
なった。図3には半製品状態の積層チップ型電子部品の
一例を示した。図3において、21はチップ本体であ
り、所定枚数積層されたグリーンシートより成り、その
内部にはグリーンシート上の導電パターンにより所定の
電気的特性を有する回路素子が等価的に形成されてい
る。
2. Description of the Related Art In recent years, the frequency of signals handled by electronic equipment has become higher, and along with this, the miniaturization of electronic parts has made further progress. For example, inductors, capacitors, and their applied elements have been commercialized with an extremely small chip size by adopting the form of laminated electronic components. FIG. 3 shows an example of a laminated chip type electronic component in a semi-finished product state. In FIG. 3, reference numeral 21 denotes a chip body, which is made up of a predetermined number of laminated green sheets, in which circuit elements having predetermined electric characteristics are equivalently formed by conductive patterns on the green sheets.

【0003】チップ本体21の第1の側面[i]には電
極22〜24がそれぞれ設けられ、第2の側面[ii]
には電極25、26がそれぞれ設けられている。そして
チップ本体21の上面[iii]にはマーキングMKが
施されている。ここでマーキングMKは、上面[ii
i]の前面[v]側を除く上面[iii]の一部を占
め、かつ、上面[iii]の後面[vi]側に偏在した
位置に設けられている。換言すると、上面[iii]の
前面[v]側はシートが露出し、上面[iii]の後面
[vi]側はマーキングMKが施された状態となってい
る。このような形態のマーキングMKでは、面にマーキ
ングMKが存在するか否かによって製品の上下の向きが
認識でき、面上のマーキングMKとシート露出部分との
位置関係により製品の前後あるいは左右の向きが認識で
きることになる。
Electrodes 22 to 24 are provided on the first side surface [i] of the chip body 21 and the second side surface [ii].
Electrodes 25 and 26 are provided in each. A marking MK is provided on the upper surface [iii] of the chip body 21. Here, the marking MK has an upper surface [ii
It occupies a part of the upper surface [iii] of the i] excluding the front surface [v] side and is provided at a position unevenly distributed on the rear surface [vi] side of the upper surface [iii]. In other words, the sheet is exposed on the front surface [v] side of the upper surface [iii], and the marking MK is provided on the rear surface [vi] side of the upper surface [iii]. In the marking MK having such a form, the vertical direction of the product can be recognized depending on whether or not the marking MK is present on the surface, and the front-back or left-right direction of the product is determined depending on the positional relationship between the marking MK on the surface and the exposed portion of the sheet. Can be recognized.

【0004】この図3に示す半製品状態の積層チップ型
電子部品は、この後、幾つかの後工程を経て完成され、
正式に製品化される。この後工程には、例えば、各電極
22〜26の表面に電極金属を接着するための工程や、
完成した製品の電気的特性値を検査する検査工程などが
含まれる。この接着工程や検査工程ではチップ本体21
の側面[i]、[ii]が処理対象になる。各工程で側
面[i]、[ii]に確実に処理を施すためには、チッ
プ本体21の姿勢を整え、更には少なくともチップ本体
21の上下方向あるいは左右方向の向きを揃えるといっ
た措置を講じておく必要がある。
The laminated chip-type electronic component in the semi-finished product state shown in FIG. 3 is completed after several post-processes.
Officially commercialized. In the subsequent step, for example, a step of adhering electrode metal to the surfaces of the electrodes 22 to 26,
An inspection process for inspecting the electrical characteristic value of the completed product is included. In this bonding process and inspection process, the chip body 21
The sides [i] and [ii] of are subject to processing. In order to surely process the side surfaces [i] and [ii] in each process, take measures such as adjusting the attitude of the chip body 21 and at least aligning the chip body 21 vertically or horizontally. I need to put it.

【0005】[0005]

【発明が解決しようとする課題】現在使用されているご
く一般的な積層チップ型電子部品の製造ラインでは、あ
る一定方向からチップ本体21の一面の所定部分(判定
領域と呼ぶ)を撮影し、画像処理により判定領域内の状
態、例えばマーキングMKの有無等、を判定し、判定結
果を基にしてチップ本体21の向きを揃えるようにして
いた。しかし、このように画像処理を利用して各面
[i]〜[iv]が図3のようになっているチップ本体
21の向きを揃える場合、次のような問題点があった。
In a manufacturing line for a general-purpose multilayer chip type electronic component which is currently used, a predetermined portion (referred to as a judgment area) on one surface of the chip body 21 is photographed from a certain direction. The state in the determination area, such as the presence or absence of the marking MK, is determined by image processing, and the orientation of the chip body 21 is aligned based on the determination result. However, when the directions of the chip body 21 in which the respective surfaces [i] to [iv] are as shown in FIG. 3 are aligned by using the image processing as described above, there are the following problems.

【0006】図3に示すようなチップ本体21の第1の
側面[i]、第2の側面[ii]、上面[iii]およ
び下面[iv]を撮影すると、各面における判定領域D
FとマーキングMK、各電極22〜26の関係は図4に
示すようになる。ここで第2の側面[ii]と下面[i
v]を比べると、両面とも判定領域DF内に撮影面が何
面であるかを識別できる特徴部分が無い。このため画像
処理で択一的な判定を行おうとすると、第2の側面[i
i]を下面[iv]に、あるいは下面[iv]を側面
[ii]に誤判定してしまう場合が出てくる。
When the first side surface [i], the second side surface [ii], the upper surface [iii] and the lower surface [iv] of the chip body 21 as shown in FIG. 3 are photographed, the determination area D on each surface is obtained.
The relationship between F, the marking MK, and the electrodes 22 to 26 is as shown in FIG. Here, the second side surface [ii] and the lower surface [i]
Comparing v], there is no characteristic part that can identify the shooting surface in the determination area DF for both surfaces. Therefore, if an alternative decision is made by image processing, the second aspect [i
In some cases, i] may be erroneously determined as the lower surface [iv] or the lower surface [iv] may be the side surface [ii].

【0007】また、第1の側面[i]の判定領域DF内
には撮影面が何面であるかを識別できる特徴部分として
電極23が存在する。しかし、一般に電極23は銀色で
あり、撮影時のチップ本体21の角度や光の加減によっ
ては電極23とその他の部分との間でコントラストに差
が無くなることがある。するとこの場合、画像処理で電
極23の存在を認識できず、判定領域DF内に撮影面が
何面であるかを識別できる特徴部分が無いのと同じ状態
になり、第1の側面[i]を第2の側面[ii]あるい
は下面[iv]に誤判定する恐れが有った。
Further, in the determination area DF of the first side surface [i], the electrode 23 is present as a characteristic portion for identifying what the photographing surface is. However, the electrode 23 is generally silver, and there may be no difference in contrast between the electrode 23 and other portions depending on the angle of the chip body 21 at the time of photographing and the amount of light. Then, in this case, the presence of the electrode 23 cannot be recognized by the image processing, and the state is the same as that where there is no characteristic portion that can identify what the photographing surface is in the determination region DF, and the first side face [i] May be erroneously determined to be the second side surface [ii] or the lower surface [iv].

【0008】これらの誤判定で不都合なのは、互いに対
向する第1の側面[i]と第2の側面[ii]は処理対
象の面であるが、下面[iv]はそれで無いことであ
る。製造装置や検査装置の構成と処理内容にもよるが、
加工治具やプローブ等が処理対象の面に接触するように
なってさえいれば、製品が180度正反対の方向を向い
ていても良いという場合が多い。このような場合、第1
の側面[i]と第2の側面[ii]の間で誤判定があっ
ても実害は無いが、下面[iv]と第1の側面[i]の
間、あるいは下面[iv]と第2の側面[ii]の間で
の誤判定は大いに有害となる。
A disadvantage of these erroneous determinations is that the first side surface [i] and the second side surface [ii] facing each other are the surfaces to be processed, but the lower surface [iv] is not. Depending on the configuration and processing contents of the manufacturing equipment and inspection equipment,
In many cases, the product may face in the opposite direction of 180 degrees as long as the processing jig, the probe, etc. come into contact with the surface to be processed. In such cases, the first
There is no real harm even if there is an erroneous determination between the side surface [i] and the second side surface [ii], but between the lower surface [iv] and the first side surface [i], or the lower surface [iv] and the second side surface [ii]. Misjudgment between aspects [ii] of [1] is extremely harmful.

【0009】このため、画像処理において判定領域DF
内に撮影面が何面であるかを識別できる特徴部分が無か
った場合、その製品は向きを揃える作業を始めからやり
直さなければならず、作業の能率が悪かった。そこで本
発明は、有害となるチップ本体の向きの誤判定を防止
し、これにより製品の向きを揃える作業の能率を向上さ
せることが可能な積層チップ型電子部品を提供すること
を目的とする。
Therefore, in the image processing, the determination area DF
If there was no feature in the product that could identify what the shooting surface was, the product had to be redone from the beginning, and the work was inefficient. Therefore, it is an object of the present invention to provide a laminated chip type electronic component that can prevent harmful misjudgment of the orientation of the chip body, thereby improving the efficiency of the work of aligning the orientation of the products.

【0010】[0010]

【課題を解決するための手段】上記課題を解決するため
の本発明は、内側には所定の電気的特性を発現する素子
が形成され、外側の第1と第2の面にはそれぞれ電極が
設けられ、その電極を介して内部素子が外部回路と電気
的に接続される積層チップ型電子部品において、外側の
対向する第3と第4の面に、それぞれ形状の異なった第
1と第2のマーキングを施しておくことを特徴とする。
According to the present invention for solving the above-mentioned problems, an element that exhibits predetermined electric characteristics is formed on the inner side, and electrodes are formed on the first and second outer surfaces, respectively. In a laminated chip type electronic component, which is provided and whose internal element is electrically connected to an external circuit through its electrode, first and second different shapes are respectively formed on the outer third and fourth surfaces facing each other. It is characterized by giving the marking.

【0011】[0011]

【発明の実施の形態】積層チップ型電子部品を構成する
チップ本体の上下面に、チップ本体の左右の側面とは明
らかに異なる彩色にて、それぞれ形状の異なった第1と
第2のマーキングを施す。具体的には、第1のマーキン
グは、上面より小さな面積で上面の一部を占め、なおか
つ上面の一方向に偏在した位置に存在するように施す。
一方、第2のマーキングは下面の全面を覆うように施
す。
BEST MODE FOR CARRYING OUT THE INVENTION First and second markings of different shapes are provided on the upper and lower surfaces of a chip body which constitutes a laminated chip type electronic component with a coloring which is clearly different from the left and right side surfaces of the chip body. Give. Specifically, the first marking is formed so that it has a smaller area than the upper surface, occupies a part of the upper surface, and is present at a position unevenly distributed in one direction of the upper surface.
On the other hand, the second marking is applied so as to cover the entire lower surface.

【0012】[0012]

【実施例】有害となるチップ本体の向きの誤判定を防止
した、本発明による積層チップ型電子部品(半製品状
態)の実施例を図1に示した。図1において、チップ本
体11の第1の側面[i]には電極12〜14がそれぞ
れ設けられ、第2の側面[ii]には電極15、16が
それぞれ設けられている。そしてチップ本体11の上面
[iii]にはマーキングMK1が、下面[iv]には
マーキングMK1と形状の異なるマーキングMK2が、
それぞれ左右面とは明らかに異なる彩色にて施されてい
る。
EXAMPLE FIG. 1 shows an example of a laminated chip type electronic component (semi-finished product state) according to the present invention, in which misjudgment of the orientation of the chip body, which is harmful, is prevented. In FIG. 1, electrodes 12 to 14 are provided on the first side surface [i] of the chip body 11, and electrodes 15 and 16 are provided on the second side surface [ii]. A marking MK1 is formed on the upper surface [iii] of the chip body 11, and a marking MK2 having a different shape from the marking MK1 is formed on the lower surface [iv].
Each of them has a distinctly different coloring from the left and right sides.

【0013】ここでマーキングMK1は、従来と同様に
上面[iii]の前面[v]側を除く上面[iii]の
一部を占め、かつ、上面[iii]の後面[vi]側に
偏在した位置に設けられている。一方、マーキングMK
2は、マーキングMK1と識別できるように下面[i
v]全面にわたって設けられている。これにより、マー
キングが面の一部にしか施されていないか、あるいは面
の全面に施されてるかにより製品の上下の向きが認識で
きる。また、面上のマーキングMK1とシート露出部分
との位置関係により製品の前後あるいは左右の向きが認
識できるようになっている。
Here, the marking MK1 occupies a part of the upper surface [iii] except the front surface [v] side of the upper surface [iii] and is unevenly distributed on the rear surface [vi] side of the upper surface [iii] as in the conventional case. It is provided in the position. On the other hand, marking MK
2 is a bottom surface [i] so that it can be distinguished from the marking MK1.
v] It is provided over the entire surface. Thereby, the vertical direction of the product can be recognized depending on whether the marking is applied to only a part of the surface or the entire surface. Further, the front-back or left-right direction of the product can be recognized based on the positional relationship between the marking MK1 on the surface and the exposed portion of the sheet.

【0014】図1に示すようなチップ本体11の第1の
側面[i]、第2の側面[ii]、上面[iii]およ
び下面[iv]を撮影すると、各面[i]〜[iv]に
おける判定領域DFとマーキングMK1、MK2、電極
12〜16の関係は図2に示すようになる。図2を見て
分かるように、判定領域DF内に撮影面が何面であるか
を識別できる特徴部分が無いのは第2の側面[ii]だ
けであり、他の三面にはそれぞれ特徴部分が存在するこ
とになる。
When the first side surface [i], the second side surface [ii], the upper surface [iii] and the lower surface [iv] of the chip body 11 as shown in FIG. 1 are photographed, the respective surfaces [i] to [iv]. ], The relationship between the determination region DF, the markings MK1 and MK2, and the electrodes 12 to 16 is as shown in FIG. As can be seen from FIG. 2, it is only the second side face [ii] that there is no characteristic part in the determination area DF that can identify the shooting surface, and the other three surfaces have characteristic parts. Will exist.

【0015】先に、撮影時のチップ本体11の角度や光
の加減によって、第1の側面[i]が第2の側面[i
i]と誤判定される可能性が有ることについては述べ
た。チップ本体11の各面が図1のようになっている積
層チップ型電子部品では、更に、撮影時のチップ本体1
1の位置ズレによって、上面[iii]が下面[iv]
に誤判定される可能性も有る。しかし、側面[i]、
[ii]と上下面[iii]、[iv]との間では誤判
定が起こり得ず、有害となるチップ本体11の向きの誤
判定は防止される。
First, the first side face [i] is changed to the second side face [i] by adjusting the angle of the chip body 11 and the amount of light at the time of photographing.
It has been described that there is a possibility that it will be erroneously determined as i]. In the laminated chip type electronic component in which each surface of the chip body 11 is as shown in FIG.
Due to the position shift of 1, the upper surface [iii] becomes the lower surface [iv]
There is also a possibility of being erroneously determined. But side [i],
Misjudgment cannot occur between [ii] and upper and lower surfaces [iii] and [iv], and harmful misjudgment of the orientation of the chip body 11 is prevented.

【0016】[0016]

【発明の効果】以上に説明したように本発明による積層
チップ型電子部品は、積層チップ型電子部品を構成する
ためのチップ本体の上下面に、チップ本体の両側面とは
明らかに異なる彩色にて、それぞれ形状の異なった第1
と第2のマーキングが施される。具体的には、第1のマ
ーキングは、上面より小さな面積を有し、上面の一方向
に偏在した位置に施され、第2のマーキングは下面の全
面に施されることを特徴としている。このような本発明
によれば、処理対象面(実施例では側面)と非処理対象
面(実施例では上下面)との間では誤判定が起こり得
ず、有害となる積層チップ型電子部品の向きの誤判定を
防止できる。これにより、製品の向きを揃える作業の能
率を向上させることが可能な積層チップ型電子部品を提
供できる。
As described above, the laminated chip type electronic component according to the present invention has a coloring that is distinctly different from both side surfaces of the chip body on the upper and lower surfaces of the chip body for forming the laminated chip type electronic component. The first with different shapes
And a second marking is applied. Specifically, the first marking has an area smaller than that of the upper surface and is provided at a position unevenly distributed in one direction on the upper surface, and the second marking is provided on the entire surface of the lower surface. According to the present invention as described above, erroneous determination cannot occur between the surface to be processed (side surface in the embodiment) and the surface not to be processed (upper and lower surfaces in the embodiment), which is harmful to the multilayer chip electronic component. It is possible to prevent misjudgment of orientation. As a result, it is possible to provide a laminated chip type electronic component capable of improving the efficiency of work for aligning the orientation of products.

【図面の簡単な説明】[Brief description of drawings]

【図1】 本発明による積層チップ型電子部品(半製品
状態)の斜視図。
FIG. 1 is a perspective view of a laminated chip electronic component (semi-finished product state) according to the present invention.

【図2】 図1に示す積層チップ型電子部品の各面の状
態と画像処理用の判定領域を示す図。
FIG. 2 is a diagram showing a state of each surface of the multilayer chip electronic component shown in FIG. 1 and a determination region for image processing.

【図3】 従来の積層チップ型電子部品(半製品状態)
の一例の斜視図。
[FIG. 3] Conventional multilayer chip type electronic component (semi-finished product state)
The perspective view of an example.

【図4】 図3に示す積層チップ型電子部品の各面の状
態と画像処理用の判定領域を示す図。
FIG. 4 is a diagram showing a state of each surface of the multilayer chip electronic component shown in FIG. 3 and a determination region for image processing.

【符号の説明】[Explanation of symbols]

11:チップ本体 12〜16:電極 DF:
判定領域 MK1:第1のマーキング MK
2:第2のマーキング [i]:第1の側面(第1
の面) [ii]:第2の側面(第2の面)
[iii]:上面(第3の面) [iv]:下面
(第4の面)
11: Chip body 12 to 16: Electrode DF:
Judgment area MK1: First marking MK
2: Second marking [i]: First side surface (first
Surface) [ii]: second side surface (second surface)
[Iii]: upper surface (third surface) [iv]: lower surface (fourth surface)

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 内側には所定の電気的特性を発現する素
子が形成され、外側の第1と第2の面にはそれぞれ電極
が設けられ、該電極を介して該内部素子が外部回路と電
気的に接続される積層チップ型電子部品において、 外側の対向する第3と第4の面に、それぞれ形状の異な
った第1と第2のマーキングが施されていることを特徴
とする積層チップ型電子部品。
1. An element that exhibits predetermined electrical characteristics is formed on the inside, electrodes are provided on the outside first and second surfaces, respectively, and the internal element is connected to an external circuit via the electrode. A laminated chip type electronic component electrically connected, characterized in that first and second markings having different shapes are provided on the third and fourth outer facing surfaces, respectively. Mold electronic components.
【請求項2】 前記第1のマーキングは前記第3の面の
一部を占め、かつ該第3の面の一方向に偏在した位置に
施され、前記第2のマーキングは前記第4の面の全面に
施されていることを特徴とする、請求項1に記載した積
層チップ型電子部品。
2. The first marking occupies a part of the third surface and is provided at a position unevenly distributed in one direction of the third surface, and the second marking is provided on the fourth surface. The multilayer chip-type electronic component according to claim 1, wherein the multilayer chip-type electronic component is provided on the entire surface of the.
JP2002020117A 2002-01-29 2002-01-29 Stacked electronic chip Pending JP2003224216A (en)

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Country Link
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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005322743A (en) * 2004-05-07 2005-11-17 Murata Mfg Co Ltd Manufacturing method of laminated coil component
JP2009200168A (en) * 2008-02-20 2009-09-03 Tdk Corp Ceramic electronic component, ceramic electronic component manufacturing method and ceramic electronic component packing method
JP2011014940A (en) * 2010-10-19 2011-01-20 Tdk Corp Ceramic electronic component, method for manufacturing ceramic electronic component, and method for packaging ceramic electronic component
US8879234B2 (en) 2011-07-19 2014-11-04 Murata Manufacturing Co., Ltd. Laminated ceramic electronic component
CN112447356A (en) * 2019-08-29 2021-03-05 株式会社村田制作所 Laminated inductor
CN113764169A (en) * 2020-06-01 2021-12-07 株式会社村田制作所 Inductance component and method for manufacturing inductance component

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005322743A (en) * 2004-05-07 2005-11-17 Murata Mfg Co Ltd Manufacturing method of laminated coil component
JP2009200168A (en) * 2008-02-20 2009-09-03 Tdk Corp Ceramic electronic component, ceramic electronic component manufacturing method and ceramic electronic component packing method
JP2011014940A (en) * 2010-10-19 2011-01-20 Tdk Corp Ceramic electronic component, method for manufacturing ceramic electronic component, and method for packaging ceramic electronic component
US8879234B2 (en) 2011-07-19 2014-11-04 Murata Manufacturing Co., Ltd. Laminated ceramic electronic component
CN112447356A (en) * 2019-08-29 2021-03-05 株式会社村田制作所 Laminated inductor
CN112447356B (en) * 2019-08-29 2023-10-03 株式会社村田制作所 Laminated inductor
CN113764169A (en) * 2020-06-01 2021-12-07 株式会社村田制作所 Inductance component and method for manufacturing inductance component
CN113764169B (en) * 2020-06-01 2024-03-12 株式会社村田制作所 Inductance component and method for manufacturing inductance component

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