JP2011014940A - Ceramic electronic component, method for manufacturing ceramic electronic component, and method for packaging ceramic electronic component - Google Patents

Ceramic electronic component, method for manufacturing ceramic electronic component, and method for packaging ceramic electronic component Download PDF

Info

Publication number
JP2011014940A
JP2011014940A JP2010234837A JP2010234837A JP2011014940A JP 2011014940 A JP2011014940 A JP 2011014940A JP 2010234837 A JP2010234837 A JP 2010234837A JP 2010234837 A JP2010234837 A JP 2010234837A JP 2011014940 A JP2011014940 A JP 2011014940A
Authority
JP
Japan
Prior art keywords
ceramic
layer
chip
electronic component
ceramic electronic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2010234837A
Other languages
Japanese (ja)
Other versions
JP4941585B2 (en
Inventor
Akira Goshima
Kazuyuki Hasebe
Toshihiro Iguchi
Akitoshi Yoshii
亮 五島
俊宏 井口
彰敏 吉井
和幸 長谷部
Original Assignee
Tdk Corp
Tdk株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tdk Corp, Tdk株式会社 filed Critical Tdk Corp
Priority to JP2010234837A priority Critical patent/JP4941585B2/en
Publication of JP2011014940A publication Critical patent/JP2011014940A/en
Application granted granted Critical
Publication of JP4941585B2 publication Critical patent/JP4941585B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01GCAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00Fixed capacitors; Processes of their manufacture
    • H01G4/30Stacked capacitors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01GCAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00Fixed capacitors; Processes of their manufacture
    • H01G4/002Details
    • H01G4/018Dielectrics
    • H01G4/06Solid dielectrics
    • H01G4/08Inorganic dielectrics
    • H01G4/12Ceramic dielectrics
    • H01G4/1209Ceramic dielectrics characterised by the ceramic dielectric material
    • H01G4/1218Ceramic dielectrics characterised by the ceramic dielectric material based on titanium oxides or titanates
    • H01G4/1227Ceramic dielectrics characterised by the ceramic dielectric material based on titanium oxides or titanates based on alkaline earth titanates

Abstract

PROBLEM TO BE SOLVED: To provide a ceramic electronic component in which the lamination direction of internal electrode layers is discriminated.SOLUTION: A chip element 2 of the ceramic electronic component 1 has two end faces 2a, 2b facing each other, a first side face 1c and a second side face 1d perpendicular to both the end faces 2a, 2b and facing each other, and a third side face 2e and a fourth side face 2f perpendicular to both the end faces 2a, 2b and the first side face 2c and the second side face 2d and facing each other, is formed of a first ceramic, and is provided inside with the internal electrodes 7. Identification layers 5, 6 are provided on the first and second side faces 2c, 2d of the chip element 2, respectively, are formed of a second ceramic different from the first ceramic, and have colors different from those of the first to fourth side faces 2c to 2f of the chip element 2. The first ceramic and the second ceramic are composed of BaTiOas a main ingredient, and have different molar ratios of (A) site atoms to (B) site atoms in the BaTiO.

Description

  The present invention relates to a ceramic electronic component, a manufacturing method thereof, and a packaging method.

  A ceramic electronic component comprising a chip body formed in a rectangular parallelepiped shape, a plurality of conductor layers disposed so as to face the inside of the chip body, and external electrodes respectively formed on end surfaces of the chip body. is there. When this ceramic electronic component is manufactured, it is accommodated in a plurality of recesses formed in the packing material (see Patent Document 1 below).

Japanese Patent Laid-Open No. 61-217317

  When mounting the packaged ceramic electronic component, the upper side surface of the ceramic electronic component exposed from the recess of the packing material is sucked by the suction conveyance device, and the ceramic electronic component is taken out of the packing material and mounted on the mounting board. Put. Then, the ceramic electronic component is mounted on the mounting board with the attracted side face up. In this case, the electric capacity between the conductor layer and the external conductor component, the magnetic field by the conductor layer, and the like differ depending on whether the opposing direction of the conductor layer is parallel to or perpendicular to the mounting substrate.

  Therefore, the electrical characteristics differ depending on the facing direction of the conductor layer of the ceramic electronic component with respect to the mounting substrate, and there is a problem because the electrical characteristics vary. In addition, not only when a plurality of conductor layers are arranged opposite to each other inside the chip body, ceramic electronic components having conductors formed inside the chip body have electrical characteristics depending on the arrangement direction of the conductors. There is a problem because it varies. Therefore, in order to mount on the substrate so that the conductors are arranged in the same direction, it is required to package the conductors in the same direction.

  However, in the completed ceramic electronic component, since the conductor disposed inside the chip body is covered with the ceramic and the external electrode, its direction cannot be visually recognized. In particular, when the end surface on which the external electrode is formed is a square, since the side surfaces of the chip body have the same shape, the arrangement direction of the conductors cannot be determined by the shape.

  Accordingly, the present invention relates to a ceramic electronic component capable of determining the arrangement direction of a conductor arranged inside a chip body, a method for manufacturing the same, and a packaging method for a ceramic electronic component capable of packaging with the conductor arrangement direction aligned. The purpose is to provide.

  The ceramic electronic component of the present invention includes two surfaces facing each other, a first side surface and a second side surface that are perpendicular to the two surfaces and facing each other, and perpendicular to the two surfaces and the first and second side surfaces. A chip body having a third side surface and a fourth side surface facing each other and formed of a first ceramic and having a conductor disposed therein, and an exterior formed on each of two surfaces of the chip body body The electrode is provided on at least one of the first side surface and the second side surface of the chip body, and is formed of a second ceramic different from the first ceramic, and is formed of the first ceramic. And an identification layer having a color different from that of the third and fourth side surfaces.

  In the ceramic electronic component of the present invention, the chip body is formed of a first ceramic, and is formed of a second ceramic different from the first ceramic on at least one side of the first side and the second side. A discriminating layer is provided. The discriminating layer formed of the second ceramic is different in color from the third and fourth side surfaces of the chip body formed of the first ceramic. Therefore, if it is determined whether the identification layer is provided on one of the side surface parallel to the conductor arrangement direction and the side surface perpendicular to the conductor arrangement direction, the conductor arrangement direction can be easily determined by the identification layer.

  In the ceramic electronic component of the present invention, preferably, the identification layer is formed so as to cover the entire surface of at least one side surface. In this case, it becomes easier to confirm the color of the identification layer.

  In the ceramic electronic component of the present invention, preferably, the first ceramic and the second ceramic have different colors due to different degrees of firing. In this case, a second ceramic identification layer having a different color from the first ceramic can be easily provided on the side surface of the chip body.

  In the ceramic electronic component of the present invention, preferably, the first ceramic and the second ceramic have different particle sizes of contained particles. In this case, a second ceramic identification layer having a different color from the first ceramic can be easily provided on the side surface of the chip body.

  In the ceramic electronic component of the present invention, preferably, the first ceramic and the second ceramic have different additives. In this case, a second ceramic identification layer having a different color from the first ceramic can be easily provided on the side surface of the chip body.

  In the ceramic electronic component of the present invention, the first ceramic and the second ceramic have different composition ratios of materials contained therein. In this case, a second ceramic identification layer having a different color from the first ceramic can be easily provided on the side surface of the chip body.

  A method of manufacturing a ceramic electronic component according to the present invention includes: a laminate forming step of forming a laminate in which a plurality of first ceramic green layers are laminated and an electrode pattern is provided therein; A second ceramic green layer is formed on at least one of the opposing surfaces using a material that is different from the first ceramic green layer and has a different color after firing from the color after firing of the first ceramic green layer. The identification layer forming step to be formed, the laminated body on which the second ceramic green layer is formed are cut, and the two surfaces facing each other, the first side surface perpendicular to the two surfaces and facing each other, and the second surface A first side surface, a third side surface and a fourth side surface that are perpendicular to the two surfaces and the first and second side surfaces and are opposed to each other, and are formed of a first ceramic green layer; A chip forming step of forming a laminate chip in which the second ceramic green layer formed in the identification layer forming step is provided on at least one of the side surface and the second side surface; and firing the laminate chip; A chip body formed of a first ceramic, a firing process for forming a chip body having an identification layer formed of a second ceramic on at least one side surface, and two chip bodies: And an external electrode forming step of forming an external electrode on the surface.

  In the method for manufacturing a ceramic electronic component according to the present invention, in the identification layer forming step, a second ceramic green layer that serves as an identification layer is formed on at least one of the mutually opposing surfaces of the multilayer body that serves as the base of the chip body. Then, it is cut into chips and fired. Thereby, it is possible to easily form a chip body in which an identification layer formed of the second ceramic is provided on at least one of the first side surface and the second side surface. The discriminating layer formed of the second ceramic is different in color from the third and fourth side surfaces of the chip body formed of the first ceramic. Further, it is provided on either one of the side surface perpendicular to the direction of arrangement of the conductors provided in the chip element body and the side surface parallel to the side surface. Therefore, the arrangement direction of the conductor can be easily determined by the identification layer.

  In the ceramic electronic component of the present invention, the first ceramic green layer and the second ceramic green layer have different particle sizes of contained particles. In this case, a second ceramic identification layer having a different color from the first ceramic can be easily provided on the side surface of the chip body.

  In the ceramic electronic component of the present invention, the first ceramic green layer and the second ceramic green layer have different additives. In this case, a second ceramic identification layer having a different color from the first ceramic can be easily provided on the side surface of the chip body.

  In the ceramic electronic component of the present invention, the first ceramic green layer and the second ceramic green layer have different composition ratios of the contained materials. In this case, a second ceramic identification layer having a different color from the first ceramic can be easily provided on the side surface of the chip body.

  The method for packing ceramic electronic components according to the present invention includes an internal electrode in a ceramic electronic component based on a preparation step for preparing a plurality of the ceramic electronic components described above, and a color difference between the third or fourth side surface and the identification layer. A discriminating step for discriminating the stacking direction of the layers, and a packing step for arranging and packing a plurality of ceramic electronic components so that the stacking directions discriminated in the discriminating step face the same direction.

  In the ceramic electronic component packaging method of the present invention, if it is determined whether an identification layer is provided on any one of the side surface parallel to the conductor arrangement direction and the side surface perpendicular to the conductor arrangement direction, in the determination step, the conductor layer The arrangement direction can be determined. Subsequently, in the packaging process, a plurality of ceramic electronic components can be arranged and packaged so that the arrangement directions of the conductors face the same direction.

  In the method for packing ceramic electronic components according to the present invention, preferably, in the determining step, the color difference between the third side surface and the identification layer is determined by measuring the difference in brightness. In this case, since the color difference can be determined with high accuracy, the stacking direction of the internal electrode layers can be determined with high accuracy.

  ADVANTAGE OF THE INVENTION According to this invention, the ceramic electronic component which can discriminate | determine the arrangement direction of a conductor, its manufacturing method, and the packaging method of the ceramic electronic component which can arrange and arrange the arrangement direction of a conductor can be provided.

It is a perspective view of the ceramic electronic component which concerns on this embodiment. It is sectional drawing of the ceramic electronic component which concerns on this embodiment. It is a flowchart which shows the procedure of the manufacturing method and packing method of the ceramic electronic component which concern on this embodiment. It is sectional drawing of the laminated body formed in the manufacturing method of the ceramic electronic component which concerns on this embodiment. It is a perspective view of the laminated body chip | tip formed in the manufacturing method of the ceramic electronic component which concerns on this embodiment. It is sectional drawing which shows the packing state of the ceramic electronic component which concerns on this embodiment. It is a figure which shows the Example of the ceramic electronic component which concerns on this embodiment.

  The best mode for carrying out the present invention will be described below in detail with reference to the accompanying drawings. In the description of the drawings, the same reference numerals are assigned to the same elements, and duplicate descriptions are omitted.

  FIG. 1 is a perspective view of a ceramic electronic component according to this embodiment. The ceramic electronic component C1 according to this embodiment is a multilayer chip capacitor. The ceramic electronic component C1 has a substantially rectangular parallelepiped shape, a height of about 2.5 mm, a width of about 2.5 mm, and a depth of about 3.2 mm, and the height direction dimension and the width direction dimension are substantially the same. The end surface on which the external electrode is formed is square.

  The ceramic electronic component C1 includes a substantially rectangular parallelepiped chip element 2, first and second external electrodes 3 and 4 formed on both end faces 2a and 2b of the chip element 2, and a chip element 2, respectively. Discriminating layers 5 and 6 provided respectively on the first side surface 2c and the second side surface 2d facing each other.

  In the chip body 2, both end surfaces 2 a and 2 b face each other, and the first side surface 2 c and the second side surface 2 d face each other and are perpendicular to the both end surfaces 2 a and 2 b. The chip body 2 includes a third side face 2e and a fourth side face 2f that are perpendicular to both end faces 2a and 2b and the first and second side faces 2c and 2d and face each other. The identification layers 5 and 6 cover the entire surfaces of the first side surface 2c and the second side surface 2d of the chip body 1, respectively.

  The first external electrode 3 is formed on the end surface 2a of the chip body 2, covers the entire surface of the end surface 2a, and covers the identification layers 5 and 6 and part of the third and fourth side surfaces 2e and 2f. The second external electrode 4 is formed on the end face 2b of the chip body 2, covers the entire end face 2b, and covers the identification layers 5, 6 and part of the third and fourth side faces 2e, 2f.

  The chip body 2 and the identification layers 5 and 6 will be described with reference to FIG. FIG. 2 is a cross-sectional view of the ceramic electronic component according to the present embodiment. The cross-sectional view shown in FIG. 2 is a cross section parallel to both end faces 2a and 2b of the ceramic electronic component C1. This cross section has a square shape in the present embodiment.

The chip body 2 is formed of ceramic (first ceramic), and a plurality of internal electrode layers 7 are formed therein. The first ceramic forming the chip body 2 is composed of, for example, BaTiO 3 as a main component and added with additives such as MgO, Y 2 O 3 , MnO, V 2 O 5 and BaSiO 3 or CaSiO 3. Is done.

  A plurality of internal electrode layers 7 are stacked with a first ceramic layer formed of a first ceramic interposed therebetween. The plurality of internal electrode layers 7 are shifted to the end face 2a side so that the end face of the internal electrode layer 7 is exposed at the end face 2a, and shifted to the end face 2b side to be shifted to the end face 2b. The internal electrode layers 7 arranged so as to expose the end faces are alternately laminated. The end face of the internal electrode layer 7 shifted to the end face 2a side is electrically and mechanically connected to the first external electrode 3, and the end face of the internal electrode layer 7 shifted to the end face 2b side is connected to the second external electrode 4. Are electrically and mechanically connected.

  Of the plurality of internal electrode layers 7, the dimension between the internal electrode layer 7 located closest to the first side surface 2c and the first side surface 2c is about 300 μm. Of the plurality of internal electrode layers 7, the dimension between the internal electrode layer 7 located closest to the second side surface 2d and the second side surface 2d is about 300 μm.

  The end surfaces on the third side surface 2e side of the plurality of internal electrode layers 7 are arranged together, and the dimension between the end surface and the third side surface 2e is about 200 μm. The end surfaces on the fourth side surface 2f side of the plurality of internal electrode layers 7 are arranged together, and the dimension between the end surfaces and the fourth side surface 2f is about 200 μm. That is, in the chip body 2, the first to fourth side surfaces 2c to 2f are made of the first ceramic.

  The thickness dimension of the identification layers 5 and 6 is about 30 μm. The identification layers 5 and 6 are made of a second ceramic different from the first ceramic. Thereby, the identification layers 5 and 6 are different in color from the first to fourth side surfaces 2 c to 2 f of the chip body 2.

  For example, the first ceramic and the second ceramic have different particle sizes of contained particles. By making the average particle size and BET diameter of the ceramic particles as the second ceramic material smaller than the average particle size and BET diameter of the ceramic particles as the first ceramic material, and increasing the degree of sintering, The color of the second ceramic is darker than that of the ceramic. In this case, the average particle size of the ceramic particles sintered in the second ceramic is smaller than the average particle size of the ceramic particles sintered in the second ceramic, and the density of the second ceramic is higher than the density of the first ceramic. high. Further, the average particle diameter and BET diameter of the ceramic particles as the second ceramic material are made larger than the average particle diameter and BET diameter of the ceramic particles as the first ceramic material, and the second ceramic is more than the first ceramic. You may lighten the color.

  Further, the first ceramic and the second ceramic may be configured such that the additives contained therein are different. For example, an additive that is not contained in one of the first and second ceramics and that changes the energy level in the band gap to change the color, or the degree of sintering Additives and the like having different colors may be added due to the difference.

  Further, the first ceramic and the second ceramic may be configured so that the composition ratios of the contained materials are different. For example, one of the first and second ceramics may be added with an additive having a different color or an additive having a different degree of sintering than the other.

  In the ceramic electronic component C <b> 1, the plurality of internal electrode layers 7 are conductors arranged inside the chip body 1. The plurality of internal electrode layers 7 are arranged symmetrically with respect to three surfaces passing through the center of the chip body 1 and parallel to the end surface 2a, the first side surface 2c, and the second side surface 2e. The arrangement direction of the conductor can be indicated by the stacking direction of the internal electrode layers 7. In the present embodiment, the stacking direction of the internal electrode layers 7 is a direction perpendicular to the identification layers 5 and 6.

  In the ceramic electronic component C1 according to the present embodiment described above, the chip body 2 is formed of the first ceramic, and the first side face 2c and the second side face 2d are different from the first ceramic. Discrimination layers 5 and 6 made of ceramic are provided. The discriminating layers 5 and 6 made of the second ceramic are different in color from the first to fourth side faces 2c to 2f of the chip body 2 made of the first ceramic. Since the identification layers 5 and 6 are provided on the first and second side surfaces 2c and 2d perpendicular to the stacking direction of the plurality of internal electrode layers 7, the stacking direction of the internal electrode layers 7 is determined by the identification layers 5 and 6. Can be determined. That is, the arrangement direction of the conductors provided inside the chip element body 2 can be determined.

  In addition, since the identification layers 5 and 6 are formed so as to cover the entire surfaces of the first and second side surfaces 2c and 2d, the colors of the identification layers 5 and 6 and the third and fourth side surfaces 2e and 2f are different. It is easy to confirm the difference.

  Further, the first ceramic and the second ceramic have different particle sizes of the main component particles contained therein. Thereby, the identification layers 5 and 6 of the second ceramic having a different color from the first ceramic can be easily provided on the side surface of the chip body 1. In addition, since the first and second ceramics have the same components and the same composition ratio, the separation between the first and second side surfaces 2c and 2d of the chip body 2 and the identification layers 5 and 6 is suppressed. Can do.

  Further, the first ceramic and the second ceramic may be configured such that the additives contained therein are different. Further, the first ceramic and the second ceramic may be configured so that the composition ratios of the contained materials are different. As a result, as in the case described above, the identification layers 5 and 6 of the second ceramic having a color different from that of the first ceramic can be easily provided on the side surface of the chip body 1. Further, since the first and second ceramics have the same main component, peeling between the first and second side surfaces 2c and 2d of the chip body 2 and the identification layers 5 and 6 can be suppressed. In addition, the first ceramic and the second ceramic are different in color due to part of the material being different or part of the addition amount being different. Therefore, the identification layers 5 and 6 can be easily formed.

  Then, the manufacturing method and packing method of the ceramic electronic component C1 which concern on this embodiment are demonstrated. FIG. 3 is a flowchart showing the steps of the method for manufacturing and packing the ceramic electronic component according to the present embodiment. The method for manufacturing a ceramic electronic component according to the present embodiment includes a multilayer body forming step S1, an identification layer forming step S2, a cutting step S3, a firing step S4, and an external electrode forming step S5. A plurality of the ceramic electronic components C1 described above are formed by these steps S1 to S5 (preparation step). Each step will be described.

In the laminated body forming step S1, as shown in FIG. 4, a laminated body in which a plurality of first ceramic green layers 21 are laminated and a plurality of electrode patterns 17 are provided therein is formed. First, the first ceramic green layer 21 is formed on the PET film. The first ceramic green layer 21 is a green layer serving as a first ceramic. The first ceramic green layer 21 is obtained by adding a ceramic slurry obtained by adding an additive to a main component and further adding and mixing a binder resin (for example, an organic binder resin), a solvent, a plasticizer, and the like on a PET film. After coating, it is formed by drying. For example, the main component of the first ceramic green layer 21 is BaTiO 3 , and the additive is MgO, Y 2 O 3 , MnO, V 2 O 5 , BaSiO 3 , CaSiO 3 and the like.

  Next, a plurality of electrode patterns 17 are formed on the upper surface of the first ceramic green layer 21. The electrode pattern 17 is formed by printing an electrode paste on the upper surface of the first ceramic green layer 21 and then drying it. The electrode paste is a paste-like composition obtained by mixing a binder resin, a solvent, or the like with a metal powder such as Ni, Ag, or Pd. For example, screen printing or the like is used as the printing means.

  A plurality of first ceramic green layers 21 on which the electrode patterns 17 are formed are stacked. A plurality of first ceramic green layers 21 on which the electrode pattern 17 is not formed are stacked on the upper and lower sides with a plurality of first ceramic green layers 21 on which the electrode pattern 17 is formed interposed therebetween. Thereby, a laminated body is formed.

  Subsequently, in the identification layer forming step S2, second ceramic green layers 15 and 16 to be the identification layers 5 and 6 are formed. The second ceramic green layers 15 and 16 are respectively formed on the surfaces 12c and 12d facing each other in the stacking direction of the stacked body.

The second ceramic green layers 15 and 16 are green layers serving as second ceramics. The second ceramic green layers 15 and 16 are mainly composed of BaTiO 3 , added with additives such as MgO, Y 2 O 3 , MnO, V 2 O 5 and BaSiO 3 or CaSiO 3 , and further a binder resin. A ceramic slurry obtained by adding (for example, an organic binder resin), a solvent, a plasticizer, and the like and mixing and dispersing is applied onto the surfaces 15 and 16 and then dried. In addition, after applying a ceramic slurry on a PET film, it may be dried and formed into a sheet to be laminated on a laminate.

  However, the second ceramic green layers 15 and 16 are ceramic green layers different from the first ceramic green layer 21. The colors of the second ceramic green layers 15 and 16 after firing are different from the colors after firing of the first ceramic green layer 21. In order to make the colors different, for example, the first ceramic green layer 21 and the second ceramic green layers 15 and 16 are made to have different particle sizes. Moreover, you may comprise the 1st ceramic green layer 21 and the 2nd ceramic green layers 15 and 16 so that the additive contained may each differ. Moreover, you may comprise the 1st ceramic green layer 21 and the 2nd ceramic green layers 15 and 16 so that the composition ratio of the material contained may differ, respectively.

  Next, in the cutting step S3, the laminated body 10 on which the second ceramic green layers 15 and 16 are formed is cut to form the laminated body chip 11 as shown in FIG. The multilayer chip 11 includes two end faces 12a and 12b that face each other, a first side face 12c and a second side face 12d that are perpendicular to the two end faces 12a and 12b, and face each other, two end faces 12a and 12b, and a first end face 12a. The third side surface 12e and the fourth side surface 12f are perpendicular to the first and second side surfaces 12c and 12d and face each other.

  The ends of the electrode pattern are exposed at the two end faces 12a and 12b. Further, the first side surface 12c and the second side surface 12d are constituted by the second ceramic green layers 15 and 16 formed by the identification layer forming step S2.

  Next, in the firing step S4, the binder contained in the first ceramic green layer 21 and the second ceramic green layers 15 and 16 is removed and fired. By firing, the first ceramic green layer 21 of the multilayer chip 11 becomes the first ceramic, and the second ceramic green layers 15 and 16 become the identification layers 5 and 6 made of the second ceramic, The electrode pattern 17 becomes the internal electrode layer 7.

  That is, the chip body 2 provided with the identification layers 5 and 6 is formed by firing. The first to fourth side surfaces 2 c to 2 d of the chip body 2 are different in color from the identification layers 5 and 6. For example, in the first ceramic, one of the BET diameters of the ceramic particles of the second ceramic is made larger or smaller than the other. Since the smaller ceramic particles are sintered at a lower temperature than the larger ceramic particles, the color can be darkened.

Further, for example, in the first ceramic, one ceramic can be made darker than the other ceramic by adding a SiO 2 compound or TiO 2 to any one of the second ceramic materials. Alternatively, by adding a large amount of SiO 2 compound or TiO 2 to one ceramic, one ceramic can be made darker than the other ceramic. That is, since the ceramic is easily burned by the additive such as SiO 2 compound and TiO 2 , the firing is further advanced and the lightness L is lowered.

Further, for example, by adding BaO, MgO, or Re 2 O 3 (rare earth oxide) to one of the materials of the first ceramic and the second ceramic, one of the ceramics can be made more than the other ceramic. Can be brightened. Alternatively, by adding a large amount of BaO, MgO, or RE 2 O 3 (rare earth oxide) to one ceramic, it is possible to make one ceramic brighter than the other ceramic. That is, additives such as BaO, MgO, Re 2 O 3 and the like make the ceramic difficult to burn, so that it becomes brighter and the brightness L is increased.

Further, for example, by adding V 2 O 5 to one of the materials of the first ceramic and the second ceramic, one ceramic can be made darker than the other ceramic. Alternatively, by adding a large amount of V 2 O 5 to one ceramic, one ceramic can be made darker than the other ceramic. This is because the band structure of BaTiO3 is changed by adding V.

  Next, in the external electrode forming step S5, the first external electrode 3 and the second external electrode 4 are formed on both end faces 2a and 2b of the chip body 2, respectively. As a result, the internal electrode layer 7 is electrically connected to the first external electrode 3 or the second external electrode 4. Through the steps described above, a plurality of ceramic electronic components C1 are completed.

  Subsequently, a method for packing ceramic electronic components according to the present embodiment will be described. The ceramic electronic component packaging method according to the present embodiment includes a preparation process, a determination process S6, and a packaging process S7. First, as a preparation step, the above-described steps S1 to S5 are performed to prepare a plurality of ceramic electronic components C1.

  Next, in the determination step S6, the stacking direction of the internal electrode layer 7 in the ceramic electronic component C1 is determined based on the color difference between the third or fourth side surface 2e, 2f and the identification layers 5, 6. Among the side surfaces of the ceramic electronic component C1 excluding the end surfaces on which the external electrodes 3 and 4 are formed, the color of two adjacent side surfaces is measured using a color measuring device. Based on the difference in the lightness L, it is discriminated whether the measured side surface is the identification layer 5, 6 or the third or fourth side surface 2e, 2f.

  For example, a spectral color difference meter can be used as the color measuring device. The lightness L of the L * a * b * color system (JIS Z8729) is measured with this spectral color difference meter. Based on the difference in the lightness L, it is discriminated whether the measured side surface is the identification layer 5, 6 or the third or fourth side surface 2e, 2f. If the measured side surface is the identification layers 5 and 6, the measured surface is a surface perpendicular to the stacking direction of the internal electrode layers. If the measured side surface is the third or fourth side surface 2e, 2f, the measured surface is a surface parallel to the stacking direction of the internal electrode layers.

  Next, in the packing step S7, as shown in FIG. 6, a plurality of ceramic electronic components C1 are arranged and packed so that the determined stacking directions of the internal electrode layers face the same direction. The packing material includes a packing material 31 and a packing material 32. The packing material 31 is formed with a plurality of concave portions 31a having a quadrangular cross section in a two-dimensional array. Ceramic electronic components C1 are accommodated in the recesses 31, respectively.

  The ceramic electronic component C <b> 1 is accommodated in the recess 31 so that the identification layers 5 and 6 are perpendicular to the depth direction of the recess 31. That is, the ceramic electronic component C <b> 1 is accommodated in the recess 31 so that the stacking direction of the internal electrode layers 7 is parallel to the depth direction of the recess 31. Thereafter, the opening of the recess 31a is covered with the packing material 32, and the packing is completed.

  In the method for manufacturing a ceramic electronic component according to the present embodiment described above, in the identification layer forming step S1, the first and second identification layers 5 and 6 are formed on the mutually facing surfaces 12c and 12d of the stacked body that is the base body of the chip body 1. Two ceramic green layers 15 and 16 are formed, then cut into chips and fired. Thereby, the chip body 2 in which the identification layers 5 and 6 formed of the second ceramic are provided on the first side surface 2c and the second side surface 2d can be easily formed. The identification layers 5 and 6 formed of the second ceramic are different in color from the third and fourth side surfaces 2e and 2f of the chip body 2 formed of the first ceramic. The identification layers 5 and 6 are perpendicular to the stacking direction of the internal electrode layers 7. Therefore, the stacking direction of the internal electrode layer 7 can be easily determined by the identification layers 5 and 6.

  In the ceramic electronic component packaging method according to the present embodiment, first, a ceramic electronic component C1 is prepared. Since the identification layers 5 and 7 are provided on the side surfaces perpendicular to the stacking direction of the internal electrode layers 7, the stacking direction of the internal electrode layers 6 can be determined by the identification layers 5 and 6 in the determination step S6. Subsequently, in the packaging step S7, a plurality of ceramic electronic components C1 can be arranged and packaged so that the stacking direction of the internal electrode layers 7 faces the same direction.

  Thereby, since it can mount in the board | substrate by aligning the lamination direction of the internal electrode layer 7 at the time of mounting, the dispersion | variation in the electrical property in the ceramic electronic component C1 and the electronic component on a board | substrate can be suppressed.

  In the packaging method of the ceramic electronic component according to the present embodiment, the color difference between the third or fourth side surface 2e, 2f and the identification layers 5, 6 in the discrimination step S6 is L * a * b * color specification. The determination is made by measuring the difference in lightness L of the system. Thereby, since the difference in color can be determined with high accuracy, the stacking direction of the internal electrode layers can be determined with high accuracy.

  Further, the first ceramic green layer and the second ceramic green layer that become the first ceramic and the second ceramic after firing have different BET diameters of the main component particles contained therein. Thereby, the identification layers 5 and 6 of the second ceramic having a different color from the first ceramic can be easily provided on the side surface of the chip body 1. In addition, since the first and second ceramics have the same components and the same composition ratio, the separation between the first and second side surfaces 2c and 2d of the chip body 2 and the identification layers 5 and 6 is suppressed. Can do.

  Further, the first ceramic green layer and the second ceramic green layer, which are the first ceramic and the second ceramic, may be configured such that the additives contained therein are different. Further, the first ceramic green layer and the second ceramic green layer, which are the first ceramic and the second ceramic, may be configured such that the composition ratios of the contained materials are different. As a result, as in the case described above, the identification layers 5 and 6 of the second ceramic having a color different from that of the first ceramic can be easily provided on the side surface of the chip body 1. Further, since the first and second ceramics have the same main component, peeling between the first and second side surfaces 2c and 2d of the chip body 2 and the identification layers 5 and 6 can be suppressed.

  In general, the chip body of the ceramic electronic component has first and second side surfaces that are perpendicular to the stacking direction of the internal electrode layers, and third and fourth side surfaces that are parallel to the stacking direction. It becomes concave. Therefore, the installation state of the ceramic electronic component is different between the case where the first or second side surface is mounted on the mounting substrate side and the case where the third or fourth side surface is mounted on the mounting substrate side. If the case where the side surface on the mounting substrate side is the first or second side surface and the case where the side surface is the third or fourth side surface coexists, the installation accuracy varies, which is a problem.

  On the other hand, according to the method for packing ceramic electronic components according to the present embodiment, the stacking directions of the internal electrode layers 7 are aligned and packed. Thus, by mounting the ceramic electronic component C1 taken out from the packing material without changing the stacking direction of the internal electrode layers 7, it is possible to suppress variations in the installation accuracy of the ceramic electronic component C1.

  Further, when the ceramic electronic component C1 is taken out from the packing material, the ceramic electronic component C1 is sucked out by using a negative pressure. At this time, since the side surface on the opening side of the packing material is adsorbed and taken out, the convex side surface is easier to adsorb than the concave shape. In the ceramic electronic component packaging method of the present embodiment, the first or second side surface 2c, 2d is positioned on the opening side of the packaging material, and thus the convex first or second side surface 2c, 2d will be adsorbed. Therefore, suction conveyance can be performed easily.

  The present invention is not limited to the above embodiment, and various modifications can be made. For example, the ceramic electronic component C1 according to the present embodiment is a chip capacitor. However, the ceramic electronic component C1 is not limited thereto, and may be a multilayer piezoelectric body, a varistor, an inductor, or the like. In the ceramic electronic component C1 according to the above embodiment, a plurality of conductors (internal electrode layer 7) are stacked. However, the number of conductors may be one.

  Further, for example, in the ceramic electronic component C1 according to the present embodiment, the identification layers 5 and 6 are provided on the first side surface 2c and the second side surface 2d of the chip body 2, respectively. . You may provide in either one of the 1st side surface 2c and the 2nd side surface 2d. Further, the identification layers 5 and 6 may be provided on the side surfaces of the chip body 2 facing each other in parallel with the stacking direction. The identification layer may be provided on any part of the first to fourth side surfaces.

(Example)
Subsequently, examples will be described. The ceramic electronic components manufactured by the above-described ceramic electronic component manufacturing method according to this embodiment are referred to as Examples 1 to 12, and the identification layer forming step is omitted in the above-described ceramic electronic component manufacturing method according to this embodiment. A ceramic electronic component having no surface is designated as Comparative Example 1.

  In FIG. 7, the material which comprises the ceramic green layer of the comparative example 1 and Examples 1-12, and the measurement result by a spectral color difference meter are shown with a L * a * b * color system. The spectral color difference meter used is a fine surface spectral color difference meter VSS 400 manufactured by Nippon Denshoku Industries Co., Ltd.

  In FIG. 7, about the comparative example 1, the material of the 1st ceramic green layer is shown. In FIG. 7, Examples 1 to 12 show the material of the second ceramic green layer, that is, the material of the identification layer. The material of the first ceramic green layer constituting the third and fourth side surfaces of Examples 1 to 12 is the same as the material of the first ceramic of Comparative Example 1.

  In Comparative Example 1, the difference between the brightness L80.9 of the identification layer and the brightness L80.2 of the third or fourth side surface was 0.7. This is a difference in error level, and the discrimination layer could not be determined based on the brightness.

In Example 1, the BET of BaTiO 3 was made larger than that of Comparative Example 1, and in Example 2, the BET of BaTiO 3 was made smaller than that of Comparative Example 1. In Example 1, the difference between the lightness L75.3 of the discrimination layer and the lightness L80.9 of the third or fourth side surface was −5.6. In this case, the discrimination layer based on the brightness could be determined. In Example 2, the difference between the lightness L88.9 of the identification layer and the lightness L80.7 of the third or fourth side surface was 8.2. In this case, the discrimination layer based on the brightness could be determined.

Example 3 is to reduce the molar ratio of A site atoms to B site atoms BaTiO 3 than Comparative Example 1, Example 4, increasing the molar ratio of A site atoms to B site atoms BaTiO 3 than Comparative Example 1 did. In Example 3, the difference between the lightness L73.7 of the identification layer and the lightness L80.6 of the third or fourth side surface was −6.9. In this case, the discrimination layer based on the brightness could be determined. In Example 4, the difference between the lightness L89.0 of the identification layer and the lightness L80.4 of the third or fourth side surface was 8.7. In this case, the discrimination layer based on the brightness could be determined.

  In Example 5, the amount of MgO added was larger than that in Comparative Example 1, and in Example 6, the amount of MgO added was smaller than that in Comparative Example 1. In Example 6, the difference between the lightness L73.2 of the identification layer and the lightness L81.2 of the third or fourth side surface was −8.0. In this case, the discrimination layer based on the brightness could be determined. In Example 6, the difference between the lightness L89.0 of the identification layer and the lightness L80.2 of the third or fourth side surface was 8.8. In this case, the discrimination layer based on the brightness could be determined.

Example 7, by increasing the amount of Y 2 O 3 than Comparative Example 1, Example 8 was reduced amount of Y 2 O 3 than Comparative Example 1. In Example 7, the difference between the lightness L71.9 of the identification layer and the lightness L80.3 of the third or fourth side surface was −8.3. In this case, the discrimination layer based on the brightness could be determined. In Example 8, the difference between the lightness L87.9 of the identification layer and the lightness L80.7 of the third or fourth side surface was 7.2. In this case, the discrimination layer based on the brightness could be determined.

Example 9 by increasing the addition amount of V 2 O 5 from Comparative Example 1, Example 10, was reduced amount of V 2 O 5 from Comparative Example 1. In Example 9, the difference between the lightness L65.3 of the identification layer and the lightness L80.6 of the third or fourth side surface was −15.3. In this case, the discrimination layer based on the brightness could be determined. In Example 10, the difference between the brightness L90.3 of the identification layer and the brightness L80.6 of the third or fourth side surface was 9.7. In this case, the discrimination layer based on the brightness could be determined.

Example 11 to increase the amount of Comparative Example 1 (Ba, Ca) SiO 3 , Example 12, Comparative Example 1 (Ba, Ca) was reduced amount of SiO 3. In Example 11, the difference between the lightness L73.7 of the identification layer and the lightness L80.2 of the third or fourth side surface was −6.6. In this case, the discrimination layer based on the brightness could be determined. In Example 12, the difference between the lightness L89.0 of the identification layer and the lightness L80.2 of the third or fourth side surface was 8.8. In this case, the discrimination layer based on the brightness could be determined.

  As described above, if the difference between the brightness of the discrimination layer and the brightness of the third or fourth side is 1 or more, the discrimination layer can be determined relatively accurately.

  C1 ... ceramic electronic component, 2 ... chip body, 2a, 2b ... end surface, 2c ... first side surface, 2d ... second side surface, 2e ... third side surface, 2f ... fourth side surface, 3 ... first External electrodes, 4 ... second external electrodes, 5, 6 ... identification layer, 7 ... internal electrode layer (conductor), 11 ... laminated chip, 15, 16 ... second ceramic green layer, 17 ... electrode pattern, 21: First ceramic green layer.

Claims (8)

  1. Two surfaces facing each other, a first side surface and a second side surface facing each other perpendicular to the two surfaces, and a first surface facing each other perpendicular to the two surfaces and the first and second side surfaces A chip body having three side surfaces and a fourth side surface and formed of a first ceramic and having a conductor disposed therein;
    External electrodes respectively formed on the two surfaces of the chip body;
    The chip body is provided on at least one side surface of the first side surface and the second side surface, is formed of a second ceramic different from the first ceramic, and is formed of the first ceramic. And an identification layer having a color different from that of the third and fourth side surfaces,
    With
    The identification layer is provided so as to cover the entire surface of the at least one side surface,
    The ceramic electronic component according to claim 1, wherein the first ceramic and the second ceramic are mainly composed of BaTiO 3 and have different molar ratios of A site atoms to B site atoms in BaTiO 3 .
  2. 2. The ceramic electronic component according to claim 1, wherein the second ceramic has a larger molar ratio of A site atoms to B site atoms in BaTiO 3 than the first ceramic. 3 .
  3. 2. The ceramic electronic component according to claim 1, wherein the second ceramic has a smaller molar ratio of A site atoms to B site atoms in BaTiO 3 than the first ceramic. 3 .
  4. A laminate forming step of forming a laminate in which a plurality of first ceramic green layers are laminated and an electrode pattern is provided inside;
    A material that is different from the first ceramic green layer and has a color after firing different from that after firing of the first ceramic green layer on at least one of surfaces facing each other in the stacking direction in the laminate. A discriminating layer forming step of forming a second ceramic green layer using
    The laminated body on which the second ceramic green layer is formed is cut, and two surfaces facing each other, a first side surface and a second side surface facing each other perpendicular to the two surfaces, and the 2 A first side and a third side and a fourth side which are perpendicular to the first side and the first side and the second side and are formed of the first ceramic green layer. A chip forming step of forming a laminate chip provided with the second ceramic green layer formed in the identification layer forming step on at least one side surface of the second side surface;
    The laminated chip is fired to form a chip body formed of a first ceramic, the chip body having an identification layer formed of a second ceramic on at least one side surface. A firing step;
    An external electrode forming step of forming external electrodes on the two surfaces of the chip body;
    With
    The first ceramic green layer and the second ceramic green layer are mainly composed of BaTiO 3 , and the molar ratio of A site atoms to B site atoms in BaTiO 3 is different. A manufacturing method for parts.
  5. 5. The manufacturing of a ceramic electronic component according to claim 4, wherein the second ceramic green layer has a molar ratio of A site atoms to B site atoms in BaTiO 3 larger than that of the first ceramic green layer. Method.
  6. 5. The ceramic electronic component according to claim 4, wherein the second ceramic green layer has a smaller molar ratio of A site atoms to B site atoms in BaTiO 3 than the first ceramic green layer. Method.
  7. A preparation step of preparing a plurality of ceramic electronic components according to any one of claims 1 to 3,
    A determination step of determining a stacking direction of the internal electrode layer in the ceramic electronic component based on a difference in color between the third or fourth side surface and the identification layer;
    A packing step of arranging and packing the plurality of ceramic electronic components so that the stacking direction determined in the determination step faces the same direction;
    A method for packing ceramic electronic components.
  8.   The method for packing ceramic electronic components according to claim 7, wherein in the determination step, the difference in color between the third side surface and the identification layer is determined by measuring a difference in brightness.
JP2010234837A 2010-10-19 2010-10-19 Ceramic electronic component, method for manufacturing ceramic electronic component, and method for packing ceramic electronic component Active JP4941585B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2010234837A JP4941585B2 (en) 2010-10-19 2010-10-19 Ceramic electronic component, method for manufacturing ceramic electronic component, and method for packing ceramic electronic component

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2010234837A JP4941585B2 (en) 2010-10-19 2010-10-19 Ceramic electronic component, method for manufacturing ceramic electronic component, and method for packing ceramic electronic component

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2008039111 Division 2008-02-20

Publications (2)

Publication Number Publication Date
JP2011014940A true JP2011014940A (en) 2011-01-20
JP4941585B2 JP4941585B2 (en) 2012-05-30

Family

ID=43593457

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2010234837A Active JP4941585B2 (en) 2010-10-19 2010-10-19 Ceramic electronic component, method for manufacturing ceramic electronic component, and method for packing ceramic electronic component

Country Status (1)

Country Link
JP (1) JP4941585B2 (en)

Cited By (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2426644A1 (en) 2010-09-03 2012-03-07 Sony Corporation Image processing apparatus and image processing method
JP2014022722A (en) * 2012-07-20 2014-02-03 Samsung Electro-Mechanics Co Ltd Laminated chip electronic component, board for mounting the same, and packing unit of the same
JP2014072507A (en) * 2012-10-02 2014-04-21 Murata Mfg Co Ltd Laminated electronic component
JP2014072515A (en) * 2012-09-27 2014-04-21 Samsung Electro-Mechanics Co Ltd Laminated chip electronic component, board for mounting the same, and packing unit thereof
JP2014127504A (en) * 2012-12-25 2014-07-07 Murata Mfg Co Ltd Multilayer ceramic electronic component
WO2014148133A1 (en) * 2013-03-19 2014-09-25 株式会社村田製作所 Multilayer ceramic capacitor
JP2014183188A (en) * 2013-03-19 2014-09-29 Murata Mfg Co Ltd Multilayer ceramic capacitor
JP2015035571A (en) * 2013-08-08 2015-02-19 サムソン エレクトロ−メカニックス カンパニーリミテッド. Multilayer ceramic capacitor and board for mounting multilayer ceramic capacitor thereon
JP2015061074A (en) * 2013-09-17 2015-03-30 サムソン エレクトロ−メカニックス カンパニーリミテッド. Multilayer ceramic electronic component and board having multilayer ceramic electronic component mounted thereon
JP5696821B2 (en) * 2013-03-19 2015-04-08 株式会社村田製作所 Multilayer ceramic capacitor
KR20150114798A (en) 2014-04-02 2015-10-13 삼성전기주식회사 Multilayered electronic component and manufacturing method thereof
KR20160098780A (en) 2015-02-11 2016-08-19 삼성전기주식회사 Chip electronic component, and circuit board for mounting the same
KR101670184B1 (en) 2015-08-24 2016-10-27 삼성전기주식회사 Multilayered electronic component and manufacturing method thereof
JP2017022407A (en) * 2011-08-22 2017-01-26 サムソン エレクトロ−メカニックス カンパニーリミテッド. Mounting structure of circuit board for multi-layered ceramic capacitor
KR20170032057A (en) 2015-09-14 2017-03-22 삼성전기주식회사 Multilayered electronic component
KR20170032056A (en) 2015-09-14 2017-03-22 삼성전기주식회사 Multilayered electronic component and manufacturing method thereof
KR20170045629A (en) 2015-10-19 2017-04-27 삼성전기주식회사 Multilayered electronic component and manufacturing method thereof
JP2018088534A (en) * 2012-07-20 2018-06-07 サムソン エレクトロ−メカニックス カンパニーリミテッド. Laminated chip electronic component, board for mounting the same, and packing unit thereof

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06120094A (en) * 1992-09-30 1994-04-28 Tdk Corp Micro electronic part assembly and checking method thereof
JPH06132182A (en) * 1992-10-19 1994-05-13 Tdk Corp Manufacture of small electronic parts
JPH06204075A (en) * 1992-12-25 1994-07-22 Taiyo Yuden Co Ltd Stacked ceramic electronic component for high frequency and its manufacture
JPH09148134A (en) * 1995-11-28 1997-06-06 Taiyo Yuden Co Ltd Multilayer inductor and manufacture thereof
JPH10241987A (en) * 1997-02-25 1998-09-11 Tokin Corp Manufacture of laminated ceramics capacitor
JP2002270428A (en) * 2001-03-09 2002-09-20 Fdk Corp Laminated chip inductor
JP2003224216A (en) * 2002-01-29 2003-08-08 Toko Inc Stacked electronic chip
JP2004356305A (en) * 2003-05-28 2004-12-16 Kyocera Corp Stacked type ceramic capacitor and manufacturing method therefor
JP2006278557A (en) * 2005-03-28 2006-10-12 Tdk Corp Multilayer ceramic electronic component
JP2009123897A (en) * 2007-11-14 2009-06-04 Tdk Corp Ceramic electronic part, its manufacturing method and its packaging method

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06120094A (en) * 1992-09-30 1994-04-28 Tdk Corp Micro electronic part assembly and checking method thereof
JPH06132182A (en) * 1992-10-19 1994-05-13 Tdk Corp Manufacture of small electronic parts
JPH06204075A (en) * 1992-12-25 1994-07-22 Taiyo Yuden Co Ltd Stacked ceramic electronic component for high frequency and its manufacture
JPH09148134A (en) * 1995-11-28 1997-06-06 Taiyo Yuden Co Ltd Multilayer inductor and manufacture thereof
JPH10241987A (en) * 1997-02-25 1998-09-11 Tokin Corp Manufacture of laminated ceramics capacitor
JP2002270428A (en) * 2001-03-09 2002-09-20 Fdk Corp Laminated chip inductor
JP2003224216A (en) * 2002-01-29 2003-08-08 Toko Inc Stacked electronic chip
JP2004356305A (en) * 2003-05-28 2004-12-16 Kyocera Corp Stacked type ceramic capacitor and manufacturing method therefor
JP2006278557A (en) * 2005-03-28 2006-10-12 Tdk Corp Multilayer ceramic electronic component
JP2009123897A (en) * 2007-11-14 2009-06-04 Tdk Corp Ceramic electronic part, its manufacturing method and its packaging method

Cited By (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2426644A1 (en) 2010-09-03 2012-03-07 Sony Corporation Image processing apparatus and image processing method
JP2017022407A (en) * 2011-08-22 2017-01-26 サムソン エレクトロ−メカニックス カンパニーリミテッド. Mounting structure of circuit board for multi-layered ceramic capacitor
JP2014022722A (en) * 2012-07-20 2014-02-03 Samsung Electro-Mechanics Co Ltd Laminated chip electronic component, board for mounting the same, and packing unit of the same
JP2018088534A (en) * 2012-07-20 2018-06-07 サムソン エレクトロ−メカニックス カンパニーリミテッド. Laminated chip electronic component, board for mounting the same, and packing unit thereof
CN108155011A (en) * 2012-07-20 2018-06-12 三星电机株式会社 Laminated chip electronic component, for installing the plate of the element and its encapsulation unit
CN103578758A (en) * 2012-07-20 2014-02-12 三星电机株式会社 Laminated chip electronic component, board for mounting the same, and packing unit thereof
JP2014072515A (en) * 2012-09-27 2014-04-21 Samsung Electro-Mechanics Co Ltd Laminated chip electronic component, board for mounting the same, and packing unit thereof
JP2014072507A (en) * 2012-10-02 2014-04-21 Murata Mfg Co Ltd Laminated electronic component
JP2014127504A (en) * 2012-12-25 2014-07-07 Murata Mfg Co Ltd Multilayer ceramic electronic component
US9336948B2 (en) 2012-12-25 2016-05-10 Murata Manufacturing Co., Ltd. Laminated ceramic electronic component
US9589729B2 (en) 2013-03-19 2017-03-07 Murata Manufacturing Co., Ltd. Multilayer ceramic capacitor
JP5696821B2 (en) * 2013-03-19 2015-04-08 株式会社村田製作所 Multilayer ceramic capacitor
US9460852B2 (en) 2013-03-19 2016-10-04 Murata Manufacturing Co., Ltd. Laminated ceramic capacitor
JP2014183188A (en) * 2013-03-19 2014-09-29 Murata Mfg Co Ltd Multilayer ceramic capacitor
WO2014148133A1 (en) * 2013-03-19 2014-09-25 株式会社村田製作所 Multilayer ceramic capacitor
KR20150017966A (en) * 2013-08-08 2015-02-23 삼성전기주식회사 Multi-layered ceramic capacitor and board for mounting the same
JP2015035571A (en) * 2013-08-08 2015-02-19 サムソン エレクトロ−メカニックス カンパニーリミテッド. Multilayer ceramic capacitor and board for mounting multilayer ceramic capacitor thereon
KR102122932B1 (en) * 2013-08-08 2020-06-15 삼성전기주식회사 Multi-layered ceramic capacitor and board for mounting the same
US9595386B2 (en) 2013-09-17 2017-03-14 Samsung Electro-Mechanics Co., Ltd. Multilayer ceramic electronic component and board having the same mounted thereon
US9875850B2 (en) 2013-09-17 2018-01-23 Samsung Electro-Mechanics Co., Ltd. Multilayer ceramic electronic component and board having the same mounted thereon
JP2015061074A (en) * 2013-09-17 2015-03-30 サムソン エレクトロ−メカニックス カンパニーリミテッド. Multilayer ceramic electronic component and board having multilayer ceramic electronic component mounted thereon
KR20150114798A (en) 2014-04-02 2015-10-13 삼성전기주식회사 Multilayered electronic component and manufacturing method thereof
US10186367B2 (en) 2015-02-11 2019-01-22 Samsung Electro-Mechanics Co., Ltd. Electronic component and board having the same
KR20160098780A (en) 2015-02-11 2016-08-19 삼성전기주식회사 Chip electronic component, and circuit board for mounting the same
KR101670184B1 (en) 2015-08-24 2016-10-27 삼성전기주식회사 Multilayered electronic component and manufacturing method thereof
KR20170032057A (en) 2015-09-14 2017-03-22 삼성전기주식회사 Multilayered electronic component
KR20170032056A (en) 2015-09-14 2017-03-22 삼성전기주식회사 Multilayered electronic component and manufacturing method thereof
US10170241B2 (en) 2015-10-19 2019-01-01 Samsung Electro-Mechanics Co., Ltd. Multilayer electronic component and method of manufacturing the same
KR20170045629A (en) 2015-10-19 2017-04-27 삼성전기주식회사 Multilayered electronic component and manufacturing method thereof

Also Published As

Publication number Publication date
JP4941585B2 (en) 2012-05-30

Similar Documents

Publication Publication Date Title
US9812260B2 (en) Multilayer ceramic capacitor
US10431379B2 (en) Method of manufacturing a multilayer ceramic capacitor
JP6593424B2 (en) Multilayer chip electronic component, its mounting substrate and package
TWI453777B (en) Laminated chip electronic component, board for mounting the same, and packing unit thereof
US20180190432A1 (en) Method for manufacturing multilayer ceramic capacitor
JP6275377B2 (en) Multilayer chip electronic component, its mounting substrate and package
KR102018307B1 (en) Multi-layered ceramic capacitor and board for mounting the same
JP5512625B2 (en) Multilayer ceramic capacitor and manufacturing method thereof
KR101548797B1 (en) A multilayer ceramic capacitor and a method for manufactuaring the same
EP2187411B1 (en) Ceramic electronic component terminals
JP2015226053A (en) Multilayer ceramic capacitor, method of manufacturing multilayer ceramic capacitor, and board with multilayer ceramic capacitor mounted thereon
JP4905498B2 (en) Multilayer ceramic electronic components
KR20140040547A (en) Multilayer ceramic capacitor and a method for manufactuaring the same
KR101681358B1 (en) A multilayer ceramic capacitor and a method for manufactuaring the same
KR101570204B1 (en) Laminated ceramic electronic component
JP5206440B2 (en) Ceramic electronic components
JP5196038B2 (en) Coil built-in board
JP5420619B2 (en) Multilayer ceramic capacitor and manufacturing method thereof
US7662430B2 (en) Ceramic electronic component and method for manufacturing the same
US9251957B2 (en) Multilayer ceramic condenser and method of manufacturing the same
JP6370744B2 (en) Multilayer ceramic capacitor and manufacturing method thereof
CN102810399B (en) Multilayer ceramic capacitor
JP5293379B2 (en) Multilayer ceramic electronic components
US10515764B2 (en) Multilayer ceramic capacitor having a tuned effective volume
US9190213B2 (en) Method of manufacturing multilayer ceramic capacitor and multilayer ceramic capacitor

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20101019

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20120131

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20120213

R150 Certificate of patent or registration of utility model

Ref document number: 4941585

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20150309

Year of fee payment: 3