JP2003223339A - In-circuit emulator - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To easily observe the operating states of a plurality of CPUs in targeting a microprocessor system having the plurality of CPUs. <P>SOLUTION: Registers (30, 31) are used for each of CPUs 27 and 28 prepared corresponding to CPU 12 and 13 of a microprocessor system 10 respectively, and when one CPU 27 is turned to an observation point based on the instruction of an external device, the CPU 27 inverts the data of the register 30 corresponding to the other CPU 28 from the observation non-execution to execution, and the transition of the corresponding CPU 28 to the observation execution state is executed in response to the inverting operation of the data. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an in-circuit emulator.

[0002]

2. Description of the Related Art In-circuit emulator (ICE)
Is a device that observes the microprocessor system, that is, confirms the operation of hardware and software. The transition to the observation state in this in-circuit emulator is performed as follows. In the observation point comparator, it is judged whether or not the access to the specific address is made in the target microprocessor system, and if it is established, the NMI is compared with the CPU prepared corresponding to the CPU in the target microprocessor system. This is performed by outputting a signal (top priority interrupt signal). Then, the CPU causes the interrupt to stop at the location where the specific address is accessed. This will make observations. The transition to the observation execution state will be referred to as "break" hereinafter.

Here, as shown in FIG. 4, the target microprocessor system has a plurality of CPUs (two CPUs 101, 10 in FIG. 4) that operate in a related manner.
2), in the in-circuit emulator, an observation point comparator for each CPU (two comparators 203 and 204 in FIG. 4) is prepared and each comparator (203, 203,
It is necessary to send the NMI signal from 204) to the CPU (201, 202).

In this case, when a state observation is performed by a program operating in relation to each other in a plurality of CPUs, there is a state in which one CPU breaks but another CPU does not break. There is a CPU that is not, and the observability is poor.

As described above, when there is a state where one CPU breaks but another CPU does not break, and there is a CPU that is in the observation state and a CPU that is not in the observation state, the observation points are set for each CPU. There was a problem that it was necessary to set each comparison condition of.

[0006]

The present invention has been made under such a background, and its purpose is to provide a plurality of Cs.
When a microprocessor system having a PU is targeted, it is possible to easily observe the operating states of a plurality of CPUs.

[0007]

According to the in-circuit emulator of claim 1, a register is prepared for each CPU prepared corresponding to each CPU of the targeted microprocessor system, and an external device is provided. When one CPU becomes an observation point based on the command of
The CPU inverts the data in the register corresponding to the other CPU from observation non-execution to execution until then, and the corresponding CPU shifts to the observation execution state in response to this data inversion operation. Therefore, one CPU shifts to the observation execution state based on the command from the external device, and the other CPU shifts to the observation execution state via the register. As a result, when targeting a microprocessor system having a plurality of CPUs, it becomes possible to easily observe the operating states of the plurality of CPUs.

[0008]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a circuit configuration of the in-circuit emulator 20 in this embodiment. The microprocessor system 10 as a target includes a mold IC (QFP) 11,
The mold IC (QFP) 11 has two CPUs 12, 1
3 and the input / output interface memory 14 are packaged. Both CPUs 12 and 13 are connected to an input / output interface memory 14. CPU12,
13 operate in relation to each other. The in-circuit emulator 20 is for observing the microprocessor system 10 having such two CPUs 12 and 13.

The in-circuit emulator 20 is composed of a target probe 21 and an in-circuit emulator main body 22. The in-circuit emulator main body 22 can be connected to the microprocessor system 10 via the target probe 21.

The main body 22 of the in-circuit emulator is
A ceramic package (PGA) 23, a host processor 24, an emulation bus analyzer 25, and an emulation controller 26 are provided. The ceramic package (PGA) 23 has a CP of the target 10.
Two CPUs 27 and 28 corresponding to U12 and U13, and an input / output interface memory 29 are packaged. Both CPUs 27 and 28 are input / output interfaces
It is connected to the memory 29.

The above-mentioned host processor 24 is for controlling the entire in-circuit emulator. The emulation bus analyzer 25 has both CPUs 27 and 2.
8 is connected to perform analysis. The emulation controller 26 performs control for emulation. Host processor 24 and emulation bus analyzer 2
5 and the emulation controller 26 are connected to each other. In addition, the host processor 24 is an external device 40.
Connected with. Each CPU 2 is controlled by this external device 40.
Target breakpoints for 7, 28, or target address numbers, can be specified.

Further, the in-circuit emulator main body 2
2 is provided with observation point comparators 32 and 33. A target breakpoint (target address number) for the CPU 27 by the external device 40 is input to one input terminal of the observation point comparator 32 via the emulation controller 26. The actual address number in the CPU 27 is input to the other input terminal of the observation point comparator 32. The output terminal of the observation point comparator 32 is connected to the CPU 27. Then, the observation point comparator 32 outputs an NMI signal (highest priority interrupt signal) for observation when the target address number and the actual address number match.

Similarly, a target breakpoint (target address number) for the CPU 28 by the external device 40 is input to one input terminal of the observation point comparator 33 via the emulation controller 26. The other input terminal of the observation point comparator 33 has C
The actual address number in PU28 is input. The output terminal of the observation point comparator 33 is connected to the CPU 28. Then, when the target address number and the actual address number match, the observation point comparator 33 outputs an NMI signal (highest priority interrupt signal) for observation.

Further, in the in-circuit emulator main body 22, a register 31 corresponding to the CPU 27, and
A register 30 corresponding to the CPU 28 is prepared.
Each CPU 27, 28 inputs the data of the corresponding register 31, 30. Further, the CPU 27 can rewrite the data in the register 30, and at the same time, the CPU 28
The data of the register 31 can be rewritten.

FIG. 2 shows the characteristic components (main parts) of FIG.
It is the one that takes out and shows only. Register 31 is C
It corresponds to the PU 27, and the register 30 is a CPU
It corresponds to 28.

Next, the operation of the in-circuit emulator will be described. The observation point comparators 32 and 33 shown in FIG. 2 determine whether or not the target microprocessor system 10 has accessed a specific address. When this is established, the NMI signal (highest priority interrupt signal) is output to the CPUs 27 and 28 prepared corresponding to the CPUs 12 and 13 in the target microprocessor system 10. CPU27 or C
The PU 28 stops at the location where the particular address is accessed by this interrupt. This will make observations. In other words, the observation point comparators 32 and 33 are for determining whether or not one CPU has become an observation point, and are breakpoints for stopping when the CPU accesses a specific address. As the highest priority interrupt signal (N
MI) is output.

In the following description, the case where the observation point comparator 32 shown in FIG. 2 accesses a specific address will be described. FIG. 3 is a timing chart for explaining the operation. In FIG. 3, the signal A from the observation point comparator 32 in FIG.
, A signal B from the CPU 27 to the register 30, a signal C from the register 30 to the CPU 28, a signal D from the CPU 28 to the register 31, and a register 31 to the CPU 27.
Signal E to.

In FIG. 3, CP at the timing of t1
When the address numbers on the U27 side match, the level of the signal A from the observation point comparator 32 to the CPU 27 is inverted. That is, the NMI signal (highest priority interrupt signal) is output to the CPU 27. Based on this, the level of the signal B from the CPU 27 to the register 30 is inverted at the timing of t2, and the data of the register 30 is inverted (rewritten) from the observation non-execution to the execution up to that point. Specifically, for example, what has been a logic “0” until then is changed to a logic “1”. As a result, the level of the signal C from the register 30 to the CPU 28 is inverted at the timing of t3. That is, the register 30 outputs a signal indicating that it is an NMI (highest priority interrupt).

Further, at the timing of t4, the level of the signal D from the CPU 28 to the register 31 is inverted, and the data of the register 31 is inverted (rewritten) from observation non-execution to execution. Specifically, for example, what has been a logic “0” until then is changed to a logic “1”. As a result, from the register 31 to the CPU 27 at the timing of t5.
The level of the signal E to is inverted.

By inverting the level of this signal E (inversion from observation non-execution to execution), the CPU 27 shifts to the observation execution state. Further, in the CPU 28, the level of the signal C is inverted (NM
By inputting the I signal), the highest priority interrupt is applied. That is, although the condition of the observation point in the observation point comparator 33 is not satisfied (although it is not the target address number), the CPU 28 shifts to the observation execution state (highest priority interrupt) by the register 30.

As a result, the CPU 27 and the CPU 28 stop at the location where the specific address is accessed by this transition (interrupt). This will make observations.

That is, as a standard configuration of the in-circuit emulator, a function of outputting its NMI state to another CPU (register data rewriting function), and
It has a configuration in which the function of the highest priority interrupt (transition to the observation execution state) is added by the data of the register rewritten by another CPU. And a CPU
(Here CPU27) is N
If the MI state is reached, register (here register 3
0) causes the other CPU (here, CPU 28) to enter the NMI state even if the observation point is not established. That is, in the conventional configuration shown in FIG. 4, even if one CPU enters the NMI state due to the establishment of an observation point, another CPU
Since U operates irrelevantly, the observability regarding the operation of a plurality of CPUs was poor. However, by adopting the configuration of FIG. The operating state can be easily observed.

When the observation is completed, t10 in FIG.
Although it is released (reset) at the timing of 0, the following operation is performed at this time. At the timing t98, which is a predetermined time Δt before the release timing t100, the signal C
And the level of the signal E is inverted. Further, the levels of the signal A and the signal D are inverted at the timing of t99. Then, at the release timing t100, the level of the signal B is inverted.

As described above, in the present in-circuit emulator, the CP prepared corresponding to each CPU 12 and 13 of the microprocessor system 10.
Registers (30, 31) are prepared for each U 27, 28, and one CPU 2 based on a command from the external device 40.
When 7 becomes the observation point, the CPU 27 causes another CP
The data in the register 30 corresponding to U28 is inverted from the previous observation non-execution to execution, and the corresponding CPU 28 shifts to the observation execution state in response to this data inversion operation. In other words, the function of outputting the NMI state from the CPU (outputting the signals B and D in FIG. 2) and the function of inputting the NMI state from the other CPU (inputting the signals E and C) are added. By doing so, a break of one CPU can break another CPU.
That is, one CPU shifts to the observation execution state based on a command from the external device, and the other CPU shifts to the observation execution state via the register. As a result, multiple CPUs
It is possible to easily observe the operating state in.

In FIGS. 1 and 2, the two CPUs 12,
Although the in-circuit emulator targeting the microprocessor system 10 having 13 CPUs has been described, it goes without saying that it may be applied to an in-circuit emulator targeting a microprocessor system having 3 or more CPUs. Absent.

Further, regarding the observation point comparators 32 and 33, in the above description of the embodiments, the highest priority interrupt signal (NMI) is regarded as the breakpoint to be stopped when the CPU accesses the specific address. However, this is merely an example, and when the CPU accesses a specific data or a specific access method, it is regarded as a break point to stop there, and the highest priority interrupt signal ( It goes without saying that it may output NMI).

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram of an in-circuit emulator according to an embodiment.

FIG. 2 is a circuit configuration diagram showing only a main part of the in-circuit emulator.

FIG. 3 is a timing chart for explaining the operation.

FIG. 4 is a circuit configuration diagram for explaining a conventional technique.

[Explanation of symbols]

10 ... Target, 12 ... CPU, 13 ... CPU, 20
... In-circuit emulator, 22 ... In-circuit emulator main body, 27 ... CPU, 28 ... CPU, 30
... register, 31 ... register, 32 ... observation point comparator, 33 ... observation point comparator.

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Claims (2)

[Claims] 1. An in-circuit emulator targeting a microprocessor system (10) having a plurality of CPUs (12, 13), each CPU (12, 1) of the microprocessor system (10).
Registers (30, 31) are prepared for each CPU (27, 28) prepared corresponding to 3), and when one CPU (27) becomes an observation point based on a command from the external device (40), The CPU (27) is another CPU
The data of the register (30) corresponding to (28) is inverted from observation non-execution to execution until then, and the corresponding CPU (28) shifts to the observation execution state in response to the data inversion operation. An in-circuit emulator characterized by that. 2. Whether or not one of the CPUs has become an observation point is determined when the CPU has made access to a specific address, access to specific data, or a specific access method. To the observation point comparator (32, 3) that outputs the highest priority interrupt signal (NMI) as the breakpoint to be stopped there.
The in-circuit emulator according to claim 1, which is performed by 3).