JP2003218844A - Data link device, method for skew detection, and method for skew detection and correction - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To speed up the decision of skew values, downsize a skew detection/ correction circuit, and respond simultaneously to parallel links with the different skew values. <P>SOLUTION: A method for generating a data pattern for the skew detection/ correction is improved. The data pattern used for the skew correction in the range up to 15 characters is disclosed. In this invention, two data PING and PONG are communicated between two nodes constructing a bi-directional link to confirm the skew detection/correction. (The node sends the PING pattern when it does not finish the skew detection/correction, while the node sends the PONG pattern when it finishes the skew detection/correction). Likely, special data is communicated to execute the skew detection/correction. The time required for determining the skew value is reduced, and the scale of the circuit is downsized. The pattern generation method of this invention is applicable to both the small and the large skews. The larger the skew value to be corrected is, the higher the effect of saving in the decision time and the circuit scale is, compared with the prior arts. This invention is also applicable to a variable skew. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for detecting and correcting a propagation delay time difference (skew), and more particularly to detecting a propagation delay time difference between parallel data signals in a device for transmitting a synchronization signal using a parallel signal line. -It relates to an electronic circuit device for correction.

[0002]

2. Description of the Related Art In a computer system, transmission / exchange equipment, data connection between equipment, and long-distance data communication system, in order to increase transmission capacity, a plurality of data transmission paths are used in parallel. The method of transmitting synchronous data is commonly used. Above all, flat cables are used for data connection inside the device, which has a very short distance. And
For data transmission up to several hundred meters between devices,
An optical link technology is used in which an optical signal transmission system including a light emitting element, a light receiving element, and an optical fiber is driven in parallel to perform signal transmission. The wavelength division multiplexing (WDM) communication technology is generally used for long-distance data transmission. "Parallel multiplex transmission technology", which collectively refers to these, uses a plurality of low-speed signal lines to enable large-capacity data transmission at low cost compared to serial data transmission in which data is put on one high-speed modulated signal. realizable.

A problem in transmitting synchronous data using this parallel data transmission system is a difference in propagation delay time between signals due to a difference in data propagation speed between a plurality of signal lines due to variations in characteristics of the signal lines. (Skew). As a result of the presence of the skew, the parallel synchronization data transmitted at the same timing on the transmitting side are received on the receiving side at mutually different timings. Therefore, it is absolutely necessary to have a method of correcting the skew and enabling the synchronization processing on the receiving side. Two techniques are mainly used for skew detection / correction of parallel signals in a conventional data communication system. One is a technology to detect and correct skew using a gate latch, and the other is to detect and correct skew in the data signal.
This is a technique of inserting a correction data pattern and performing skew detection / correction in a logic circuit.

A method of skew correction using a gate latch is disclosed in Atsushi Takai et al., IEEE Journal of Lightwave Techn.
ology, Volume 12, pages 260-270. In this report, gate latch circuits are arranged inside the laser drive circuit of the optical transmission interconnection module and the photodiode drive circuit of the optical reception interconnection module, and the skew between 11 data channels driven in parallel is 1 channel. A configuration is used in which retiming is performed using the clock signal of Also,
The clock skew correction circuit of Japanese Patent Laid-Open No. 5-234266 also realizes a circuit for correcting the clock signal of data by using the flip-flop circuit. Further, in the data identification circuit, the optical parallel receiver, the optical parallel transmitter, and the terminal structure of the optical transmission fiber used in the optical parallel receiver, the circuit for detecting the data edge using the multiphase clock is realized. is doing. All of the above three methods are methods of detecting the edge of the data signal with respect to the clock signal, and the skew amount of the signal that can be corrected is as small as within one cycle of the clock signal.

The following three methods have been proposed as techniques for correcting a larger skew of one cycle or more in a logic circuit. The first method is proposed in the inter-channel skew compensating device of Japanese Patent No. 3193352 and Japanese Patent Laid-Open No. 11-341102. In the present invention, in order to compensate for the skew between the parallel signal paths of the m channels, a redundant signal line of the m'channel is provided, and the encoded signal is placed on the parallel signal paths of a total of m + m '. It realizes skew compensation. The second method is a method proposed in Japanese Patent Laid-Open No. 11-298457 parallel optical transmission / reception module, in which an independent skew correction logic circuit dedicated for skew detection / correction is provided in the receiving section. The third method is a method generally used in Ethernet (registered trademark) multi-channel communication. Skew detection / composition consisting of special characters of 8B10B code.
Skew is corrected on the receiving side by communicating a dedicated correction pattern. In the third method, the skew detection / correction is not always performed, but only in the initial state of communication (immediately after the reset is released) and when the skew changes, the skew detection / correction is required.
Data pattern "I + I +" for skew detection / correction below
II-I + I-I + I-I + I-I + I-I + I-I + I- "or" II-I + I + I-
I + I-I + I-I + I-I + I-I + I-I + "(I + is 8B10B code special character K28.5 +, I- is the same K28.5-) is sent for each channel. And I + I + II- or I on the receiving side
-Detects and corrects the skew amount between parallel channels by searching the position of -I-I + I +. According to the third method in FIG.
A data pattern used in a multi-link of Gigabit Ethernet and a skew determination example of 3 channels using the data pattern assuming a skew amount of 12 characters will be shown.

[0006]

The problem to be solved by the present invention is to reduce the circuit scale and the judgment time necessary for correcting a large skew amount of several clocks or more. In the method using the gate latch circuit in the prior art, the maximum skew that can be corrected is as small as about ± 0.5 clock because the setup hold time of the gate latch must be satisfied. Data transmission in which the skew is within 1 clock is a short distance or an area where the data modulation speed is very slow. The present invention is directed to areas that are faster and have a larger amount of skew.

On the other hand, the first method using the frame synchronization method
The method can correct the skew of several clocks at any time during data communication by increasing the number of m'redundant channels for skew adjustment. It is necessary to expand and install the redundant channel of the channel, and the expansion of the device scale becomes a problem. The second method is also a method in which the circuit scale is doubled by arranging an independent receiving system circuit provided for skew detection / correction.

The third method requires expansion of the signal line as in the first method, and the second method requires a receiving circuit dedicated to skew detection / correction on the receiving side. Although it does not require a large expansion of the structure, it has the disadvantage that data communication cannot be realized during the skew determination time (I + I + ... pattern is communicating).

Since the purpose of the present invention is to correct the skew amount that cannot be corrected by the gate latch circuit, it is premised on the use of frame synchronous skew detection / correction, and the first and second methods are used. The initial state of data communication (immediately after reset is released) as in the third method, without drastically expanding the device configuration (increasing the number of channels or providing an optical receiver independently)
And a method of communicating a dedicated data pattern only when the skew changes. However, since the third method is a method in which data communication is temporarily disabled during the skew detection / correction operation, it is necessary to perform the skew detection and correction operation in a short time. An object of the present invention is to reduce the time required for processing and the circuit scale in an apparatus that communicates this dedicated data pattern to realize skew detection / correction.

[0010]

In order to solve the above problems, the present invention proposes to utilize a special pattern for detecting a skew. And from the sending side,
The special pattern for detecting the skew is transmitted to the receiving side, the receiving side detects a predetermined number of character arrays in the special pattern, and based on the detected character array,
Measure the amount of skew.

Now, let X be the maximum value of the skew to be guaranteed. In other words, there are X kinds of skew amounts to be detected. However, skew 0 is not included in the X types. The skew unit is, for example, a carrier clock period (unit is bit). A unique character array is determined for each of these skews. For example, to guarantee a skew of 15 bits,
A character array that can express 16 kinds of deviations of 0 to 15 bits is used by adding 1 bit of skew 0 (no deviation) to 15 bits. The minimum character arrangement that can realize this is an arrangement in which four A and B are used as character units and four of them are combined. When A is associated with 1 (or 0) or B is associated with 0 (or 1), there are four digits from "0000" to "1111". Of course, if it is four digits or more, the same effect can be obtained. As will be described in detail later, in order to detect the round-trip skews respectively, it is sufficient to use the doubled five digits from “00000” to “11111”. That is, the maximum value of the skew that can be specified by the arrangement of the two types of characters (Y + 1) is the value obtained by subtracting 1 from the power of 2 X (= 2 ^Y-
1). As a result, the specific character arrangement corresponds to the skew amount in a one-to-one manner, and thus the skew amount can be immediately determined by the determination of the character arrangement.

Next, a method for forming the above character array will be described. Here, the shortest character array is used. In this case, the predetermined number of character arrays are Y + 1 characters arranged,
The special pattern is defined according to the following rules (1) to (7). (1) Define two characters A and B. These characters A and B may be formed of one bit such as "1" or "0", or may be formed of a plurality of bits such as "0000" to "1111". Next, a character array consisting of Y + 1 characters is generated by combining at least X sets and A and B. At least one of A and B should be a character dedicated to skew detection in order to easily discriminate it from normal data. The rules for forming X patterns are (2)-
It is as in (7).

(2) Only the character B is arranged in Y + 1 number, and a predetermined number of character arrays are defined. (3) The top character of the character array defined immediately before is deleted. (4) The top character is selected in (3) above. If (a) A is added to the position of the least significant character in the deleted character array, it must match the already defined character array.
Add A and (b) Add A to define a predetermined number of character arrays by adding B if they match the already defined character array.

(5) Returning to (3) above, the character array is defined in order by (4). When a character array in which the highest character is A and all others are B appears, the process ends (6) Character B Only Y + 1 pieces, then
The character added in (a) or (b) of (4) is added in order, and the leading character B is connected after the last character to define a character loop. That is, as described with reference to FIG. 3, when such a pattern generation rule is used, the generated pattern array finally circulates in a constant cycle.

(7) At least Z from the defined loop
A number of consecutive characters are extracted and defined as a special pattern (where Z = X + Y + 1). It should be noted that one feature of the present invention lies in the arrangement of the special pattern itself, and therefore the arrangement forming procedure itself is not necessarily limited to the above (1) to (7). In short, the formed special pattern may eventually satisfy the conditions (1) to (7). Next, any continuous Y + 1 character string in the special pattern is defined in correspondence with skew 0 (no skew), and Y + 1 character strings sequentially shifted by one character are generated from 1 bit each. Supports skew up to X bits.

As described above, the Y + 1 character strings corresponding to the skews all have different arrangements. When detecting the skew, the above skew detection pattern is transmitted prior to data transmission (even during transmission), and the receiving side forms an observation window of window width Y + 1 at a predetermined reference point for observation. To do. The skew amount can be detected from the observed character string.

The case where the present invention is applied to a parallel bidirectional link will be described below. The skew of each communication path of the bidirectional link connecting the two communication nodes is communicated with a pattern satisfying the following rule to detect and correct the skew. (1) Let us assume that the maximum skew expected between parallel channels is the W bit width with the carrier clock period as the unit of deviation, and the skew of this W bit is judged in units of characters consisting of Q bits (the maximum value of the skew is
Represented as the X character). However, X is an integer that can be represented by 2 ^Y -1, and Y is a positive integer that satisfies Q × (2 ^Y -1) ≥ W> Q × (2 ^(Y-1) -1). (2) At this time, skew detection / correction is performed by communicating the data pattern PING and the data pattern PONG of two different Z characters (Z = X + Y + 1) as the data pattern for skew detection / correction. .

(3) Both the PING and PONG patterns have the following characteristics. In the Y + 1 continuous character pattern that starts with the Fth character from the beginning (F is an arbitrary integer from 2 to X + 1), the Y consecutive patterns from the beginning are the F-1th from the beginning. Start with character, Y +
The Y-th consecutive pattern in the Y + 1 consecutive character pattern that is equal to the last Y consecutive patterns in one consecutive character pattern and that has the Fth character from the beginning is the beginning To F
Y + the 1st character as the head Y + Y continuous patterns that are equal to the Y continuous patterns from the beginning of the data pattern, and Y + that starts the Fth character from the beginning
The pattern of one continuous data is the continuous pattern of Y + 1 data starting with the F + 1 character and the PING
PONGs differ from each other in the case where F is an arbitrary integer from 2 to X + 1 (the same Y + 1 continuous pattern does not appear between PING and PONG).

(4) The data pattern PING is transmitted when the skew detection / correction of the own node is not completed at the nodes at both ends connected by the bidirectional link. In the data pattern PONG, the skew detection / correction of the own node is completed in each of the nodes at both ends connected by the bidirectional link,
Sent when the PING pattern is received from the opposite node. On the receiving side, when the PING or PONG pattern is received, it is possible to determine the skew value between the mutual data channels by observing the data pattern for Y + 1 characters at the same time for all the parallel channels. Further, by communicating with two data patterns of PING and PONG, both end nodes forming the bidirectional link can mutually monitor the skew detection / correction state of the oppositely connected nodes.

[0020]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below. In the following examples, specific numerical values are used to facilitate understanding, but these numerical values are merely examples, and the present invention is not meant to be limited to these numerical values. (Embodiment 1) FIG. 1 is a conceptual diagram of a PING / PONG data pattern used in the present invention and a 3-channel skew determination example using the same, assuming a maximum skew amount of 15 characters. In this embodiment, a maximum skew of 150 ns is corrected in three parallel channels with a modulation rate of 1 Gbit / sec. That is, the deviation of one character is 1
Corresponds to 0 ns. For example, in Figure 1, CH1 and CH2 are 40
It has a gap of ns.

First, the data pattern (PING and
PONG) is prepared. The method of generating PING and PONG is shown below. (1) The maximum skew expected between parallel channels is W bit width with carrier clock period as a unit,
It is assumed that the W bit width skew is determined in units of a character having a Q bit width. Here, the maximum value of the skew is expressed as an X character. That is, W = Q × X.
However, X is a positive integer that can be represented by 2 ^Y −1, and Y is a positive integer that satisfies Q × (2 ^Y −1) ≧ W> Q × (2 ^(Y−1) −1) Expression 1. In the example of FIG. 1, the maximum skew value is 15 characters, and characters A and B are composed of 10 bits, so X = 15, Q = 10, W = 150, Y = 4.
Is.

(2) At this time, two different characters (A,
B) Z data pattern PING and data pattern
PONG is communicated to detect and correct skew. Here, Z = X + Y + 1. Skew detection is Y + 1 as described below.
It is realized by observing individual characters. The maximum value of skew that can be detected by Y + 1 characters is 2 to the power of Y
It is the value X (= 2 ^Y -1) minus 1. It is necessary to make X a minimum value that exceeds the maximum value of the assumed skew in order to optimize (minimize) the data pattern width for observation. In the example of FIG. 1, Z = 15 + 4 + 1 = 20.

(3) The PING pattern is generated according to the following rules. (A) First, assume two characters consisting of Q bits (hereinafter A and B). (B) Y + 1 character string is generated by combining X sets and A and B. However, in the character string, the total number of A is B
The condition is less than the total number of. Here, at least one of A and B is a character dedicated to skew detection / correction. (C) The X sets of patterns are made to correspond to the skews from 0 to X characters (total of X + 1 pieces) in the following order (the skews from 0 ns to 150 ns in time conversion are made to correspond at intervals of 10 ns). (D) The pattern corresponding to the 0 ns skew has a configuration in which only Bs are arranged. (E) For the pattern corresponding to the skew of 1 character (10 ns), the uppermost character of the pattern corresponding to 0 ns is erased, the character is shifted up one by one, and A is added to the position of the lowermost character. , If it does not match the pattern already mentioned
Add A. When A is added and it matches the existing pattern B
Add. (F) Return to the following (O) and X from 2 characters (20ns)
The patterns corresponding to the skew up to +1 (150 ns) are generated in order. (G) The patterns in which A is the maximum number (A is less than B) are rearranged so as to be associated again with the skew of 0 ns, and then added to the bottom in the steps (e) to (f). The characters A and B are connected in order to form a PING pattern.

(5) The PONG pattern is generated according to the following rules. (A) First, assume two characters consisting of Q bits (hereinafter A and B). (B) Y + 1 character string is generated by using X sets and a combination of A and B. However, in the character string, the total number of B is less than the total number of A. Where A
At least one of B and B is a character dedicated to skew detection and correction. (C) The X sets of patterns are made to correspond to the skew from 0 to the X character (total X + 1 pieces). (D) The pattern corresponding to the 0 ns skew has a configuration in which only A is arranged. (E) For the pattern corresponding to the skew of 1 character (10 ns), erase the highest character of the pattern corresponding to 0 ns, shift 1 character to the upper position, and add A to the position of the lowest character, If it does not match the pattern already mentioned
Add A. When A is added and it matches the existing pattern B
Add. (F) Return to the following (O) and X from 2 characters (20ns)
The patterns corresponding to the skew up to +1 (150 ns) are generated in order. (K) A is arranged from the top (maximum number -1), followed by B, and rearranges the pattern with A at the end to correspond again to the skew of 0 ns, and then from (E) The characters A and B added to the lowest in the process of (f) are connected in order to form a PONG pattern.

Actually, this generation rule is applied to the skew correction of 150 ns. (1) First, 10-bit characters K28.5 and K28.1 are prepared as characters for skew detection / correction. K28.5 and K28.1 are special characters in the 8B10B code. In this skew detection / correction circuit, K28.1 is a character code dedicated to skew detection / correction, and upon detection of K28.1, the skew detection / correction mode is entered. In addition, K28.5 and K28.1 disparities communicate according to the rules of the 8B10B code.

(2) A skew of 150 ns corresponds to 150 bits at a modulation rate of 1 Gbit / sec (cycle 1 ns), and a 10-bit character (K28.5 or K28.
When 1) is used as a unit, it corresponds to 15 characters. (3) Assuming a skew of 15 characters, X, Y, Z in the generation rule are calculated as 15, 4, 20. Substituting into Expression 1, 10 × (2 ⁴ −1) ≧ 150> 10 × (2 ³ −1) Expression 2 that satisfies the conditional expression (Expression 1) is obtained as follows.

(4) A PING pattern is generated as follows. (A) First, Y + 1 (5) A (K28.1), B (K28.5)
16 for the combination data pattern of BBBBB as the initial value
Generate individually. 1) BBBBB 2) BBBBA (A addition) 3) BBBAA (A addition) 4) BBAAB (A requires 2 or less, B added) 5) BAABB (A requires 2 or less, B added) 6) AABBB (A requires 2 or less, B added) 7) ABBBA (A added) 8) BBBAB (BBBAA already mentioned, B added) 9) BBABA (A added) 10) BABAB (A requires 2 or less, B 11) ABABB (A is 2 or less, B is added) 12) BABBA (A is added 13) ABBAB (A is 2 or less is required, B is added) 14) BBABB (BBABA is already mentioned, B is added,) 15) BABBB (BABBA has already appeared, B added,) 16) ABBBB (ABBBA has already appeared, B added,) (b) The sixth AABBB is sorted to the top (AA is the maximum number)
Two at the beginning). Make AABBB correspond to skew value 0. 1) AABBB 2) ABBBA 3) BBBAB 4) BBABA 5) BABAB 6) ABABB 7) BABBA 8) ABBAB 9) BBABB 10) BABBB 11) ABBBB 12) BBBBB 13) BBBBA 14) BBBAA 15) BBAAB 16) BAABB ) AABBB at the beginning, underlined symbols, and PING
Use as a pattern. AABBBABABBABBBBBAABB

According to the above rules, the PING pattern shown in FIG. 1 is formed. In this pattern, arbitrary consecutive 5 characters are all arranged differently. Note that the zero skew value corresponds to AABBB, but this is relative. (5) Generate a PONG pattern as follows. (A) First, Y + 1 (5) A (K28.1), B (K28.5)
The combination data pattern of 16 with AAAAA as the initial value
Generate individually. 1) AAAAA 2) AAAAB 3) AAABB 4) AABBA 5) ABBAA 6) BBAAA 7) BAAAB 8) AAABA 9) AABAB 10) ABABA 11) BABAA 12) ABAAB 13) BAABA 14) AABAA 15) ABAAA 16) BAAAA (A) ) Rearrange the 4th AABBA to the top (two AA that are 1 less than the maximum number, aligned at the top). AABBA is skew value 0
Correspond to. 1) AABBA 2) ABBAA 3) BBAAA 4) BAAAB 5) AAABA 6) AABAB 7) ABABA 8) BABAA 9) ABAAB 10) BAABA 11) AABAA 12) ABAAA 13) BAAAA 14) AAAAA 15) AAAAAB 16) AAABB (c) ) Starting from AABBA, arrange the underlined symbols to make a PONG pattern. AABBAAABABAABAAAAABB

According to the above rules, the PING pattern shown in FIG. 1 is formed. In this pattern, arbitrary consecutive 5 characters are all arranged differently. Note that the zero skew value corresponds to AABBA, but this is relative. Here, as shown in FIG. 1, A (8B1) dedicated to skew detection / correction for all three channels is used.
After observing the pattern of the special character K28.1) in the 0B code, the skew of each channel can be determined by observing 5 characters for 3 channels simultaneously (corresponding to the window position in FIG. 1). According to the example of FIG. 1, channel 3 (CH3) is used as a reference (skew 0 (AABB
B)), the skew of channel 1 (CH1) is 4 characters (BABAB) and the skew of channel 2 is 8 characters.
It turns out that it can be judged as (BBABB). After the skew is detected, channel 2 is delayed by a buffer for 8 characters and channel 1 is delayed by a buffer for 4 characters, so that channels 1, 2, and 3 are synchronized (skew is aligned) and passed to a subsequent circuit. I can do things.

FIG. 3 shows the skew amount and the corresponding data pattern (5 characters) of the data pattern in the example of FIG.
Shows the relationship. The data pattern group of 5 characters in the present invention has the relationship shown in FIG. 3, and the pattern of the lowest BAABB of PING is shifted by 1 character to the highest pattern AABBB of PING and the highest pattern AABBA of PONG, respectively. In addition to the relationship of adding B and A respectively, the relationship of adding 1 character shift and B and A respectively from the lowest AAABB pattern of PONG to the highest pattern AABBB of PING and the highest pattern AABBA of PONG. The pattern of PING and PONG can be switched smoothly by shifting one character.

FIG. 4 is a state transition diagram showing a handshake for skew detection / correction used in the present data transmission system. In this system, a pair of two skew detection / correction circuit reception side (DS / RX) and skew detection / correction circuit transmission side (DS / TX) are connected face-to-face, and handshaking is performed between them. It has a structure to establish a heavy data communication system. Figure 8 shows such skew detection
FIG. 6 shows a structural block diagram of a bidirectional parallel optical link using a correction circuit. The state transition is composed of four states. D
4 with 3 state variables of SREADY, PNGRDY, PIGPOG
Defines two states. The initial state is defined as INIT. INIT
Starts to extract the clock signal from the data signal, waits for the clock signal to stabilize, and then the two state variables RDY signal and PIG
Change the POG signal from L to H, and transit to the PING state.

In the PING state, the PING data pattern is DS / T
Send from X to DS / RX to perform skew detection / correction operation. The DS / TX side has a structure for transmitting PING sequence data (PING side in FIG. 1) while the state variable PNGRDY signal is L, and transmitting PONG sequence data when the PNGRDY signal is H.
When the DS / RX side receives the PING sequence signal from the DS / TX side in the PING state and the skew detection / correction operation by the PING sequence is completed, the PNGRDY signal transits from L to H and PO
Move to NG state. On the other hand, when the DS / RX side is in the PING state, D
When the PONG sequence data (PONG side in Fig. 1) is received from S / TX and the skew detection / correction operation in the PONG sequence is completed after that, the status variable PNGRDY signal and DSREADY signal
The signal simultaneously transits from L to H and transits to OPERATION mode. Furthermore, when the DS / RX side is in the PONG state, the PONG sequence data (PONG) from the DS / TX or the data signal Dx.x (8B1
Receive any valid data in 0B code) and send PONG
When the skew detection / correction operation in the sequence is completed, the DSREADY signal transits from L to H and transits to OPERATION mode.

In the OPERATION mode, the PING / PONG synchronization sequence is completed, and data communication between full-duplex systems becomes possible. By providing two states of PING / PONG for the handshake operation, two nodes in the full-duplex system can monitor each other's skew detection / correction operation status, and wait for the completion of both skew detection / correction operations to communicate data between nodes. The handshake function to start is realized.

(Embodiment 2) An embodiment of the present invention will be described below. In the following examples, specific numerical values are used to facilitate understanding, but these numerical values are merely examples, and the present invention is not meant to be limited to these numerical values. FIG. 5 shows a PING / PONG data pattern used in the present invention, assuming a maximum skew amount of 63 characters. The data generation method used in the first embodiment is applied when the maximum skew is 64 characters. In this case, the skew of each channel can be detected by communicating the PING and PONG data patterns shown in FIG. 5 and observing the data pattern of 7 characters. Then, by referring to the observed signal sequence,
The skew value between each signal channel is detected, and the detected delay value is delayed by the buffer and corrected, so that the receiving side can process as a synchronization signal without skew (skew detection / correction is completed. ).

When the skew position is determined using the conventional Gigabit Ethernet system, a clock number of 68 characters at the maximum is necessary for the skew determination (I + I +
II-I + I -... 29 repeats I + I-). On the other hand, the method of the present invention enables skew determination by observing 7 characters. As described above, according to the present invention, as the amount of skew requiring correction increases, the speed of skew determination can be increased as compared with the conventional example.

(Embodiment 3) An embodiment of the present invention will be described below. In the following examples, specific numerical values are used to facilitate understanding, but these numerical values are merely examples, and the present invention is not meant to be limited to these numerical values. The present invention is an example in which the skew detection / correction circuit of the first embodiment is applied to a parallel optical link device. The skew detection / correction LSI according to the present invention comprises two circuit blocks, a reception side skew detection / correction circuit (DS / RX) and a transmission side skew detection / correction circuit (DS / TX). Skew detection / correction is performed on the transmitting side DS / TX and the receiving side DS / RX.
It is carried out between parallel signals of 10 channels connecting between the two.

FIG. 6 shows the case of communicating the carrier clock.
FIG. 6 is an internal block diagram of a receiver side (DS / RX) of a parallel link device equipped with a skew detection / correction circuit. FIG. 7 is an internal block diagram of the transmitter side (DS / TX) of a parallel link device equipped with a skew detection / correction circuit when communicating a carrier clock. This link device constitutes a data system having 10 bidirectional parallel channels. The data rate of the signal is 1.25 gigabits per second per signal. When realizing long-distance transmission with parallel optical signals as in this device, the dispersion of transmission delay in the fiber ribbon used as the transmission medium (50 ps / m for multimode fiber) is large, and the fiber length is longer than about 16 meters. Skew between signal channels is 1 for distance transmission
The clock (800 ps) or more and the retiming process of the gate latch method, which can correct only the skew within one clock, cannot be applied. Therefore, in the present invention,
By sending the skew detection / correction data pattern (Fig. 1) from the transmission side and analyzing the timing of the data pattern at the reception side, retiming up to 150 clocks (1.25 gigabits per second clock) is possible. Was adopted.

In the data transmission device shown in FIG.
A function to connect a laser transmitter to the output end of the transmission side encoder to convert the signal to optical and transmit it, and to connect a laser receiver to the input end of the reception side decoder to reconvert the signal from optical to electrical signal By installing the, the high-speed and long-distance data transmission of signals became possible. In this equipment, the laser transmitter used was a parallel optical transmitter equipped with an array type laser element, and the laser receiver used in the equipment was an optical parallel receiver equipped with an array photodiode. Large-capacity optical data communication is realized by using parallel ribbon fibers to connect the transmitter and laser receiver. The signal flow in the device is described below.

As shown in FIG. 8, first, a parallel optical signal of 10 channels × 1.25 gigabits / sec of data signal is converted into a parallel electrical signal of 10 channels × 1.25 gigabits / sec by an optical receiver (Optical RX). . The DS / RX block corrects the delay time difference (skew) between this 10-channel electrical signal and the base clock, and after 8B10B decoding, it is used as a parallel synchronization signal of 8 channels x 1.25 gigabits per second as a clock signal / frame. Output together with the sync signal. The data signal of 8 channels is subjected to data processing at the node, and then 8 channels × 1.
It outputs as a 25 Gbit / s data signal together with two signals of clock and frame synchronization. The signal from the node is 8B10B encoded by the DS / TX block and output in the form of 10 channels × 1.25 gigabits per second. Then, the 10-channel electrical signal is converted into an optical signal by the 10-channel parallel optical transmitter (Optical RX), and long-distance data transmission up to 1 km is realized by the multimode fiber ribbon. When a signal with a modulation rate of 1.25 gigabits per second is transmitted by an electric cable, the limit of the distance is about 20 m due to the propagation loss, and the system is configured to take advantage of the optical data transmission.

In the present skew detection / correction device, a multiplexer is further connected to the output side of the decoder on the receiving side, and a demultiplexer is mounted on the input side of the encoder on the transmitting side, so that the decoding on the receiving side is performed. By reducing the number of signal pins for input / output data between the encoder and the transmitter encoder, and by separately mounting the decoder and encoder in a chip package separate from the signal processing circuit, they can be used independently as skew detection / correction circuits. In addition to making it possible, the number of external input / output signal pins at the time of separate mounting can be reduced.

The internal block configuration on the DS / RX side is shown in FIG. The 10-channel electrical signal output from the optical receiver is input to the DS / RX 10-channel input port INRXD-0P / N, ...,
INRXD-9P / N (here, skew adjustment LSI port 0
Alternatively, one of the ports 1, P and N respectively represent a positive phase signal and a negative phase signal of the differential signal). At the input end of DS / RX, the clock signal INRXC-P / N is input to the clock recovery circuit circuit (CG1) and distributed to each block in DS / RX as the clock signal RXC.

Input signal INRXD- [0..9] to the DS / RX circuit
Has a phase different from that of the high-speed clock signal RXDC reproduced from INRXC and has a maximum skew of ± 80 clocks (clock speed of 1.25 Gbit / sec) when a 1 km fiber is used. The 10-channel input data signal is first input to the clock signal RX by the deskew circuit (Deskew) at the input stage.
The phase difference between DC and each data bit INRXD- [0..9] is corrected with a delay line, and the clock and data signals are resynchronized independently for each channel, and the 10 The data signal is converted into RXS- [0..9] (at this stage, the data signal is synchronized with the clock, but the skew between the data is deviated in units of one clock).

In the next stage, 10: 1 demultiplexer processing is performed for each data channel, and 10 bits (total 1
00 bit) Expand to RM- [0..9]-[0..9] (1.2
Convert 5 Gbit / s x 1 bit signal to 1.25 Mbits / s x 10 bits). At this time, the first bit of the 8B10B encoded signal is set in the demultiplexer.
Output signals are aligned in 10-bit character units by arranging them in the LSB (character synchronization). The 10-bit signal of each channel output from the demultiplexer is 8
Decoded by B10B decoder, 8-bit signal RS- [0 ..
9]-[0..7]. Then, the word synchronization circuit (Wsync Buffer) in the next stage performs synchronization processing between words,
80-bit data signal synchronized with one clock signal
Converted to RE- [0..79].

This 80-bit data signal is resynchronized with the internal clock signal in the elastic buffer and R-
As [0..79], the signal is output as OUTRXD- [9..0] -P / N from the DS / RX block as a high-speed signal of 1.25 Gbit / s × 8 channels after being subjected to 10: 1 multiplexer processing again. . At this time, the frame synchronization signal OUTRXF-P / N and the clock signal OUTRXC-P / N indicating the first bit of the 10: 1 multiplexer processing are output in parallel to the 8-channel data signal. Re-synchronization by the elastic buffer is an essential process for handling signals synchronized with different clock sources during transmission and reception of data. OUTRXF-P / N
The DELAY circuit attached to each stage of the clock signal OUTRXC-P / N is a circuit for adjusting the phase difference between the data OUTRXD- [9..0] -P / N and outputting it as a synchronization signal. is there. The output synchronization signal is the phase locked loop circuit PLL1.
At the same time, it is generated from BASECLK and CRCLK (1
25 MHz) and CLK1250 (1250 MHz).

FIG. 7 shows the internal block structure on the DS / TX side. DS / TX block is 8 channels from node x 1.2
5 Gbit / sec parallel synchronous electrical signal INTXD- [0..7] P /
N is 80 bits × 1. With a 10: 1 demultiplexer.
Convert to signal TR- [0..79] of 25 Mbit / s.
The operation of the demultiplexer is the clock signal INTXC-P / N synchronized with the data signal and the frame synchronization signal INTXF-P for each port.
Execute based on / N. Electric signal TR- [0 ... 79] of 80 bits x 1.25 megabits per second is 8B10 every 8 bits.
Encoding processing is performed with the B encoder. Then, the electric signal TE- [0 ...
9]-[0..9] is 1 every 10 bits after resynchronizing with the carrier clock CLK1250 in the elastic buffer.
Multiplexed by 0: 1 multiplexer, total 10 channels x 1.25 Gbit / sec electric signal OUTTXD-
[0.7.] Converted to P / N and output to the optical transmission module.
Then, OUTTXC-P / N is transmitted as a carrier clock signal synchronized with the output data. Input signal from node INTXC-
The P / N is converted into 125 MHz clock signals TXDC and TXC by the clock reproduction circuit CD2 and output. In addition, the output synchronization signal is BASECLK in the phase locked loop circuit PLL1.
Generated from, and CRCLK (125MHz) and each circuit block
It is distributed as CLK1250 (1250MHz). The handshake for skew detection / correction used in the entire system has a configuration according to FIG.

FIG. 9 shows the detailed operation of the skew detection / correction function used in the PONG routine and the PING routine of the handshake routine shown in FIG. In the skew detection / correction operation, the skew detection / correction operation is completed through two synchronization stages of bit / character synchronization and word synchronization. When bit / character synchronization is completed normally for each channel, BSYNC [ch] ([ch] is 0 for each port and each channel)
1 to 10 channels out of 9 channels are shown. ) Becomes 1 and WSYNC becomes 1 when the word synchronization operation ends normally. W when all skew adjustments are completed
When SYNC becomes 1, the PING or PONG skew adjustment routine is completed.

In the bit / character synchronization stage, a bit synchronization operation is first performed. In bit synchronization, the receiving side receives and analyzes the dedicated bit pattern (Fig. 1) output from the transmitting side,
The delay time of the clock signal is corrected in units of 100 ps independently for each 10-bit data channel in the port, and the optimum value of the timing between the clock signal and the data signal is searched.

FIG. 10 shows the relationship between the eye pattern of the data signal and the clock read timing. When the value of DVALUECH is changed in 8 steps from 0 to 7 and the setting is such that the clock trigger point for the data signal is delayed by 100 ps units, in the phase relationship of FIG. 10, four DVALUECH values of 0, 1, 6, 7 are set. When the value is, the H / L of the data signal is not stable at the trigger point, so the comma pattern is not detected in the data determination, and conversely when the DVALUECH has four values of 2, 3, 4, and 5, Since the H / L of the data signal is stable at the trigger point, the comma pattern can be detected correctly in data discrimination. In this case, DVAL
The UECH of 3 or 4 is the optimum point among the eight delay amounts.

In the present invention, the minimum value with which the delay line can be accurately manufactured is considered to be 100 ps, and eight observations are performed every 100 ps so that the data can be observed eight times at a clock cycle of 800 ps of 1.25 Gbit / s signal. , Adopted the method of searching for the optimum point. Further, the delay amount is not changed at the timing of the carrier clock (1.25 gigabits per second), but is changed in synchronization with the timing of the internal clock (1.25 megabits per second), which facilitates implementation. Immediately after the delay amount changes, the delay time becomes unstable, so
The observation of the comma pattern is performed for 3 clocks at a timing of 1.25 megabits per second, 1 clock immediately after the change is not observed, and the truth pattern of the comma pattern detection in the 2 or 3 clocks thereafter is determined. . The delay pattern table was determined so as to cover the time width of one clock at equal intervals as much as possible in eight measurements. The determination table is determined so that the delay value can be set as close to the center of the eye opening diameter as possible.

By controlling DVALUECH- [CH], the delay amount of the clock signal with respect to the data signal is changed by 8 values in one synchronous operation, and the input terminal RX-D of the 10: 1 demultiplexer is changed.
8B1 called a comma with EMUX input as shown in Fig. 10.
10-bit specific data pattern defined on the 0B code (K28.1 and K28.5 are also a kind of comma with 10 kinds)
The optimum point of the delay value is searched depending on whether or not can be observed (in FIG. 10, the case where the comma is correctly received is represented by a circle, and the trigger point position is not appropriate and the comma cannot be received correctly. When the pattern matches, it is expressed as x).

Bit-character synchronization shifts to character synchronization. In character synchronization, the reading order of the registers in the demultiplexer is adjusted so that the first bit of the 8B10B encoded signal consisting of 10 bits is set to the LSB of the 10: 1 demultiplexer. This is 8B
This is the same method as the comma alignment generally used in Ethernet circuits using 10B codes.

FIG. 11 shows the structure of character synchronization in bit character synchronization. The character synchronization mechanism means that the leading bit of 10-bit data and the low-speed clock are not synchronized at the input terminal of the 1:10 demultiplexer,
When the 10-bit character signal cannot be output correctly from the demultiplexer, the read timing in the demultiplexer is corrected so that the 10-bit character signal and the clock TRXC synchronized with the character signal are correctly synchronized on the output side of the demultiplexer. It means the operation to correct the state. For example, in FIG. 11, the input signal RXS of the demultiplexer and the internal clock signal (1.25 MHz) are synchronized with the 7th bit of the character signal (10 bits), and the output side RM correctly starts from 0 bit. The data is read out as a character signal (10 bits) of 1.25 megabits per second with 9 bits aligned. In the present invention, bit synchronization and character synchronization are performed at the same time, and when both ends normally, BSYN for each channel
C [ch] transits from 0 to 1. And all BSYNCH [c
When [h] becomes 1, the operation shifts to the next word synchronization operation (FIG. 9). On the contrary, if even one bit of all BSYNCH [ch] cannot be confirmed to transition to 1, the initial state is returned to START, and the signal after bit character synchronization is 8 bit data for every 10 channels through 8B10B decoder. Converted to a pattern. Next, a word synchronization operation is performed so that a signal whose phase is aligned in 10-bit character units for each channel is adjusted in character units and output as a 1-word (80-bit) signal. In word synchronization, the skew between the data signals of 10 channels that have been character-synchronized is determined from the deviation of the embedded pattern in the data pattern,
Skew detection / correction is performed by adjusting the read / write timing of the read / write buffer among 10 channels.
By the above operation, maximum 1 of 10 channels in each port
Correct skew for up to 5 characters. In the present invention, by transmitting / receiving the data pattern shown in FIG. 1 and observing data for 7 characters on the receiving side at the time of word synchronization transition,
The skew is determined by the same method as in the second embodiment.

(Fourth Embodiment) In the third embodiment, one of the data signals is input to the clock data recovery circuit (CDR) mounted on the receiving side without transmitting the carrier clock,
The receiving side generates a clock signal (the data signal input to the CDR and the clock have a synchronous relationship). The adjustment of the phase relationship between the generated clock signal and the other reception side data signal not used for clock extraction and the clock signal uses the same method as the bit / character synchronization of the third embodiment.
Figure 12 shows the structure of the DS / RX block. FIG. 13 shows the block structure of DS / TX. Compared to the drawing of the third embodiment, it has a structure in which the carrier clock signal line is eliminated.

(Embodiment 5) FIG. 14 is a structural block diagram of a bidirectional parallel optical link in which a skew detection / correction circuit is integrated inside a module. The parallel optical transmission module and the parallel optical reception module were each equipped with the function of any one of Examples 1 to 4 (FIG. 14). By installing a skew detection / correction circuit that synchronizes words and a bit / character synchronization circuit inside the module, the overall size of the device can be reduced.

(Embodiment 6) FIG. 15 is a structural block diagram of a bidirectional wavelength division multiplexing optical link using a skew detection / correction circuit. The function according to any one of Embodiments 1 to 5 is installed in a wavelength division multiplexing optical transmitter and a wavelength division multiplexing optical receiver, respectively (see FIG. 1).
5). The skew detection / correction method described in the first embodiment is
Although there is a difference in arrival time at the receiving side due to dispersion in the fiber, by resynchronizing at the receiving side by this method,
Parallel synchronous transmission using a plurality of wavelength-multiplexed signals can be easily realized.

(Embodiment 7) FIG. 16 is a structural block diagram of a bidirectional parallel optical link using a skew detection / correction circuit having an external control line for skew amount. In any one of Embodiments 1 and 3 to 6, in the data pattern generation circuit for skew detection / correction for word synchronization, the maximum skew detection / correction amount to be set is input by the external circuit of the device, and the input skew detection / correction amount is input. Depending on the correction amount,
Skew detection according to the generation method shown in the first embodiment
A data pattern for correction is generated and communicated (FIG. 16).
This method can provide optimal and highly efficient skew detection and correction functions according to the set skew detection / correction amount.

[0057]

According to the present invention, skew detection / correction is performed prior to parallel link data transmission, as a method for widening the skew detection / correction range and for avoiding an increase in circuit scale such as by providing redundant data lines. The method of communicating the data pattern of the above is transmitted and received. At this time, K28.5, which was conventionally used in Ethernet etc., was replaced by K28.5 +, K28.5 +,
In the method of detecting the positions where K28.5- and K28.5- appear, for example, it took a maximum of 20 characters to measure the skew position in the range of 15 characters, whereas the present invention It is possible to detect and correct skew by observing 4 characters.
The correction circuit can be simplified. The effect of saving the detection time, the time required for the correction, and the circuit size is greater when the skew is larger than that in the conventional technique. further,
By controlling the skew range to be corrected by the external circuit, it is possible to easily determine and correct the skew of any width. This method can be extended to the detection and correction of skew of any size as long as the size of the buffer memory that can be mounted on the receiving side that constitutes the data link system allows.

[Brief description of drawings]

FIG. 1 is a conceptual diagram of a PING / PONG data pattern used in the present invention and a 3-channel skew determination example using the same when a maximum skew amount of 15 characters is assumed.

FIG. 2 is a conceptual diagram of a data pattern used in a multi-link of Gigabit Ethernet and a skew determination example of 3 channels using the data pattern when a maximum skew amount of 15 characters is assumed.

FIG. 3 is a diagram showing a relationship between a skew amount and a corresponding data pattern (5 characters) of the data pattern in the example of FIG.

FIG. 4 is a PING / PONG state transition diagram.

FIG. 5 is a table of a PING / PONG data pattern used in the present invention, assuming a maximum skew amount of 63 characters.

FIG. 6 is an internal block diagram of a receiver side (DS / RX) of a skew detection / correction circuit when a carrier clock is communicated.

FIG. 7 is an internal block diagram of a transmitter side (DS / TX) of a skew detection / correction circuit when a carrier clock is communicated.

FIG. 8 is a structural block diagram of a bidirectional parallel optical link using a skew detection / correction circuit.

FIG. 9: Bits inside both PING / PONG states
FIG. 9 is a state transition diagram of a skew determination / correction operation that combines character synchronization and word synchronization.

FIG. 10 is an explanatory diagram of bit synchronization.

FIG. 11 is an explanatory diagram of character synchronization.

[Fig. 12] Receiver side of the skew detection / correction circuit (DS / R when the clock data recovery circuit (CG1) is used.
It is an internal block diagram of (X).

FIG. 13 is an internal block diagram of the receiver side (DS / TX) of the skew detection / correction circuit when the clock data recovery circuit is used.

FIG. 14 is a structural block diagram of a bidirectional parallel optical link in which a skew detection / correction circuit is integrated inside a module.

FIG. 15 is a structural block diagram of a bidirectional wavelength division multiplexing optical link using a skew detection / correction circuit.

FIG. 16 is a structural block diagram of a bidirectional parallel optical link using a skew detection / correction circuit having an external control line for skew amount.

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Hiroaki Nishi             2-5-12 Higashi-Kanda, Chiyoda-ku, Tokyo             New Information Processing Development Organization (72) Inventor Junji Yamamoto             2-5-12 Higashi-Kanda, Chiyoda-ku, Tokyo             New Information Processing Development Organization F-term (reference) 5K029 AA01 AA18 CC04 DD23 JJ01                 5K047 AA08 AA16 BB02 BB04 GG11                       GG16 HH01 HH12 HH43

Claims (14)

[Claims] 1. A data link device for transmitting a synchronization signal by using P-channel (P is a positive integer of 2 or more) signal lines in parallel, wherein Q ′ × P bits are set to 1 at both transmitting and receiving nodes.
Synchronous signal processing is performed as a word, and in data transmission, Q'bits are encoded into Q bits in each channel on the transmitting side and data is transmitted, and decoding processing is performed from Q bits to Q'bits on each channel on the receiving side. In a device that transmits data by using the following method (Q and Q'are equal when not encoded),
Prior to data transmission, a data pattern for skew (transmission delay time difference) detection / correction, which is transmitted at each parallel signal line at the transmission end, is generated according to the following rules (1) to (3), (1) The maximum skew expected between parallel channels is assumed to be W bit width in units of carrier clock period, and the skew of W bit is assumed to be determined in units of Q bit characters. Here, X is an integer that can be represented by 2 ^Y −1, and the bit width Y is a positive integer that satisfies Q × (2 ^Y −1) ≧ W. (2) At this time, the data patterns for skew detection / correction are set to two different characters A and B (both Q bit width).
Is defined as a data pattern of Z characters (Z = X + Y + 1) represented by the array, and at this time, at least one of the two characters A and B does not appear during normal data communication. It is a correction-only character. (3) The skew detection / correction data pattern has an array configuration that satisfies the following conditions (1) to (3). In the Y + 1 continuous character pattern that starts with the Fth character from the beginning (F is an arbitrary integer from 2 to X + 1), the Y continuous patterns from the beginning are F-1 from the beginning.
The first character is the same as the last Y continuous patterns in the Y + 1 consecutive character pattern, and the Fth character from the beginning is Y,
The Y continuous patterns from the end of the +1 continuous character pattern are from the beginning of the Y + 1 continuous data pattern that starts with the F + 1 character from the beginning.
Y + 1 which is equal to Y consecutive patterns, and whose beginning is the Fth character from the beginning
The pattern of the continuous data is different from the continuous pattern of the Y + 1 data starting with the F + 1 character and the case where F is an arbitrary integer from 2 to X + 1. Further, in some or all of the parallel signal lines in the data link device, the receiving side simultaneously observes Y + 1 continuous data patterns of the data pattern, thereby making it possible to reduce skew between observed parallel signals. According to the detected data, the skew between the observed parallel signal paths is corrected word by word (Q ′ × P bits are defined as one word. Nodes at both ends perform data synchronous processing in word units), and the receiving circuit A data link device characterized by synchronizing parallel signals with each other. 2. In a bidirectional data link device for transmitting a synchronization signal by using P-channel (P is a positive integer of 2 or more) signal lines in parallel, Q ′ × P bits are set as one word at both transmitting and receiving nodes. Synchronous signal processing, and in data transmission, each channel on the transmitting side encodes Q'bits into Q bits and sends out the data, and on each channel on the receiving side, decodes from Q bits to Q'bits to perform data processing. In a transmitting device (Q and Q ′ are equal when not encoded), a skew (transmission delay time difference) detection / correction dedicated data pattern transmitted from the transmission end for each parallel signal line is transmitted before data transmission. Assuming that the following rules (1) to (3) are satisfied, (1) the maximum skew expected between parallel channels is assumed to be W bit width in units of carrier clock period. Assume the skew determining character consisting of Q bits as the unit of (the maximum value of the skew expressed as X characters). However, X is an integer that can be represented by 2 ^Y -1, and Y is a positive integer that satisfies Q × (2 ^Y -1) ≥ W. (2) At this time, a data pattern of Z characters (Z = X + Y + 1) defined as an array of two different characters A and B (both Q bit width) as a data pattern for skew detection / correction. 2 types are defined as PING and PONG data patterns. At this time, at least one of the characters A and B is a character for skew detection / correction that does not appear during normal data communication. (3) And, both PING and PONG patterns are common,
It has the following structures. In the Y + 1 continuous character pattern that starts with the Fth character from the beginning (F is an arbitrary integer from 2 to X + 1), the Y consecutive patterns from the beginning are F from the beginning.
-Equal to the last Y consecutive patterns in the Y + 1 consecutive character pattern, starting with the first character, and starting with the Fth character from the beginning, Y
The Y continuous patterns from the end of the +1 continuous character pattern are from the beginning of the Y + 1 continuous data pattern that starts with the F + 1 character from the beginning.
Y + 1 which is equal to Y consecutive patterns, and whose beginning is the Fth character from the beginning
The pattern of this continuous data is the continuous pattern of Y + 1 data starting with the F + 1st character, and PING and PO.
NG differs from each other when F is an arbitrary integer from 2 to X + 1 (the same Y + 1 continuous pattern does not appear between PING and PONG). And the data pattern PI
NG is transmitted when the skew detection / correction of the own node is not completed at the nodes at both ends connected by the bidirectional link, and the data pattern PONG is transmitted by the nodes at both ends connected by the bidirectional link. When the skew detection / correction is completed and the PING pattern is received from the opposite node, the PING pattern is transmitted, and further, in one or a plurality of parallel signal lines in the data link device, the data pattern of the data pattern is simultaneously received on the receiving side. By observing Y + 1 characters inside, the skew between the observed parallel signals is detected,
In accordance with the detected data, the skew between the observed parallel signal paths is corrected word by word (Q ′ × P bits are defined as one word. Nodes at both ends perform synchronous processing of data in word units), and parallel correction is performed in the receiving circuit. A data link device characterized by synchronizing signals. 3. A bit synchronization function for phase-correcting a data signal and a clock signal within a range of one clock cycle for each parallel channel, and detecting the first bit of a character signal composed of Q bits for each parallel channel. The data link device according to claim 1 or 2, further comprising a character synchronization function for performing synchronous output. 4. A carrier clock signal synchronized with the data signal is transmitted from the transmission side of the skew detection / correction circuit separately from the parallel data signal, and the carrier clock signal is transmitted at the reception side of the skew detection / correction circuit. The data link device according to any one of claims 1 to 3, wherein the signal is used as a synchronous clock signal to detect and correct skew between each parallel data and the clock signal. 5. A clock data recovery circuit for extracting a synchronous clock from a fluctuation edge of a data signal is mounted on some or all channels on the receiving side of the skew detection / correction circuit, and a part or all branched from the receiving side are provided. The clock component is extracted from all the data signals by the clock data recovery circuit, and the skew between each parallel data and the clock signal is detected and corrected by using the clock signal as a synchronous clock signal. The data link device according to any one of items 1 to 7. 6. The data generation circuit unit used for skew detection and correction is mounted inside a parallel optical transmission module having a laser array mounted thereon.
The data link device according to any one of items 1 to 7. 7. The structure according to claim 1, wherein the skew detection / correction circuit unit used for skew detection / correction is mounted inside a parallel optical receiver module having a photodiode array. The data link device according to item. 8. A parallel synchronization using a plurality of wavelength-multiplexed channels by having a structure in which a parallel signal is multiplexed and carried by optical signals of different wavelengths and the multiplexed signal is transmitted by one serial fiber. The data link device according to any one of claims 1 to 7, which realizes transmission. 9. The maximum value of the skew required to be detected and corrected is input by an external signal, and the value of Y is a positive integer satisfying the following expression and a determination condition according to the magnitude of the external signal. And Q × (2 ^Y −1) ≧ W ＞ Q × (2 ^Y −1 -1) Based on the calculated value of Y, the minimum skew detection / correction data pattern is required. 9. By generating and communicating the above, a minimum necessary skew detection / correction function according to the skew is provided for a skew of any size, and any one of claims 1 to 8 is provided. The data link device according to item 1. 10. The transmission side transmits a special pattern for detecting a skew to the reception side, and the reception side detects a predetermined number of character arrays in the special pattern, and based on the detected character array. Then, in the skew detection method for measuring the skew amount, there are X kinds of skew amounts to be detected (however, skew 0 is not included), and the predetermined number of character arrays are Y + 1 characters arranged. The skew detection method is characterized in that the special pattern is defined according to the following rules (1) to (7). (1) Define two characters A and B (2) Arrange only Y + 1 number of characters B and define a predetermined number of character arrays (3) Delete the highest character of the character array defined immediately before (4) If (a) A is added to the position of the lowest character of the character array from which the highest character has been deleted in (3) above, it must match the previously defined character array.
Add A, (b) Add A when A matches the already defined character array, and add B to define a predetermined number of character arrays. (5) Return to (3) above, and (4) Define the character arrays in order, and end when the character array in which the highest character is A and all others are B appears (6) Only the character B is arranged in Y + 1 number, and then,
The character added in (a) or (b) of (4) is added in order, and the leading character B is connected after the last character to define a character loop (7) The defined loop At least Z consecutive characters are extracted from the table and defined as the special pattern (where Z = X + Y + 1). 11. The skew detection method according to claim 10, wherein X is a value obtained by subtracting 1 from 2 to the power of Y. 12. The character according to claim 10, wherein the characters A and B are characters formed by a combination pattern of “1” and “0”, and at least one of them is a pattern that does not appear in the data. Skew detection method. 13. P channel (P is a positive integer of 2 or more)
In a data link device for transmitting a synchronization signal by using the signal lines in parallel, the transmitting and receiving nodes process the synchronization signal with Q '× P bits as one word, and in data transmission, Q'bits are used in each transmission side channel. In a device that encodes data into Q bits and sends out the data, and performs decoding processing from Q bits to Q'bits in each channel on the receiving side for data transmission (when not coded, Q and Q'are equal) Side transmits a special pattern for detecting the skew to the receiving side, the receiving side detects a predetermined number of character arrays in the special pattern, and measures the skew amount based on the detected character array. The skew amount to be detected is X, and the skew amount to be detected is X.
Type (but does not include skew 0), X is 2
It is assumed that the value is obtained by subtracting 1 from the power of Y of the above, and the predetermined number of character arrays are arranged by Y + 1 characters, and the special pattern is defined according to the following rules (1) to (7). Characteristically, (1) define two characters A and B (2) arrange only Y + 1 number of characters B and define a predetermined number of character arrays (3) delete the highest character of the character array defined immediately before (4) If (a) A is added to the position of the lowest character of the character array from which the highest character has been deleted in (3) above, it must match the already defined character array.
Add A, (b) Add A when A matches the already defined character array, and add B to define a predetermined number of character arrays. (5) Return to (3) above, and (4) Define the character arrays in order, and end when the character array in which the highest character is A and all others are B appears (6) Only the character B is arranged in Y + 1 number, and then,
The character added in (a) or (b) of (4) is added in order, and the leading character B is connected after the last character to define a character loop (7) The defined loop At least Z consecutive characters are extracted from the above, and defined as the special pattern (where Z = X + Y + 1). Further, in some or all of the parallel signal lines in the data link device, the data pattern of the data pattern is simultaneously received on the receiving side. The skew between the observed parallel signals is detected by observing the Y + 1 continuous data pattern in the above, and the word (Q ′ × P bit is defined as one word according to the detected data. (Synchronize data in units) Synchronize parallel signals in the receiving circuit by correcting skew between observed parallel signal paths in units. View detection / correction method. 14. A data pattern for detecting data skew (transmission delay time difference) on the transmission side during data transmission, or prior to this, or during and before data transfer, is defined by the following (1) to (3). ), The data skew is detected by observing Y + 1 continuous data patterns in the data pattern on the receiving side. (1) It is assumed that the maximum expected skew is the W bit width with the carrier clock cycle as the unit, and the skew of this W bit is determined with the character consisting of Q bits as the unit, and the maximum skew value is the X character. Where X is an integer that can be represented by 2 ^Y -1, and the bit width Y is
A positive integer that satisfies Q × (2 ^Y −1) ≧ W (2) Data patterns for skew detection and correction are both
Defined as a data pattern of Z characters (Z = X + Y + 1) represented by an array of two different characters A and B of Q bit width, and at least one of the two characters A and B at that time Is a skew detection / correction-dedicated character that does not appear during normal data communication (3) The skew detection / correction data pattern has an array configuration that satisfies the following conditions (1) to (3). In the Y + 1 continuous character pattern that starts with the Fth character from the beginning (F is an arbitrary integer from 2 to X + 1), the Y consecutive patterns from the beginning are F from the beginning.
-Equal to the last Y consecutive patterns in the Y + 1 consecutive character pattern, starting with the first character, and starting with the Fth character from the beginning, Y
The Y continuous patterns from the end of the +1 continuous character pattern are from the beginning of the Y + 1 continuous data pattern that starts with the F + 1 character from the beginning.
Y + 1 which is equal to Y consecutive patterns, and whose beginning is the Fth character from the beginning
The pattern of the continuous data is different from the continuous pattern of the Y + 1 data starting with the F + 1 character and the case where F is an arbitrary integer from 2 to X + 1.