KR100401062B1 - Apparatus for transmiting/receiving high speed data of an infiniband system - Google Patents

Abstract

The high-speed data transmission and reception apparatus of the Infiniband system according to the present invention is to enable fast and efficient transmission and reception of high-capacity data, and is provided among symbols for controlling a transmission request in a link layer and symbols for a physical layer. Transmission means for multiplexing according to the selection control signal and converting the output packet byte stream into a bit stream; Training sequence generating means for generating a training sequence for initializing the physical layer and providing a selection control signal to the transmitting means; Lane recognition means for converting the received data by changing the lane according to the corresponding lane; Word alignment means for aligning words by eliminating skew generated between signals output when the training sequence is received through four lanes; Conversion means for converting the byte stream outputted from the transmission means into a serial bit stream and transmitting it externally through a connector, and converting the serial bit stream received from the outside into a parallel byte stream and outputting the same; Receiving means for decoding the serial byte stream provided by the conversion means, extracting only the necessary data from the decoded stream to provide to the link layer.

Description

Apparatus for transmiting / receiving high speed data of an infiniband system

The present invention relates to a high speed data transmission apparatus of an InfiniBand system, and to a high speed data transmission and reception apparatus of an InfiniBand system capable of transmitting and receiving high capacity data quickly and efficiently.

The demand for complex computer calculations is increasing with the development of the multimedia Internet.

Therefore, the demand for a high performance computer that can perform a large amount of calculations in a short time is rapidly changing from traditionally used single system form to clustering form.

A cluster computer builds a single system by combining unit computing nodes equipped with general purpose processors into a high-speed connection network. This structure is widely used as an internet server because of its scalability, price performance ratio, and fault monitoring.

Recently, Infiniband has emerged as the next generation cluster network. International standardization work has already been done.

InfiniBand Architecture (hereinafter referred to as IBA) is a System Area Network (SAN) that interconnects independent processor platforms, I / O platforms, and I / O devices.

IBA systems range from small servers with one processor and its peripherals to large parallel supercomputers with hundreds of processors and thousands of peripherals.

IBA has several hierarchies like traditional networks. Protocols at each layer are independent of protocols at other layers. It provides services to the upper layers depending on the services of the layers below each layer. The upper layer of the physical layer is a link layer, and direct communication between two terminal nodes is performed through high speed serial data transmission between both physical layers.

High speed serial data transmission has recently been widely used to solve the problem of shared bus type transmission.

High-speed serial data transmission is a method of dividing data between two points through a serial line into a transmission medium. There are two types of cable transmission and optical fiber transmission.

A high speed serial data transmission method using RS-422 is well shown in Korean Patent Application No. 1989-9329 (name of the invention: high speed serial data transmission circuit). In other words, this technology is a circuit for transmitting data at high speed through a serial line using RS-422, and it is possible to transmit and receive data by connecting to a RS-422 interface through a serial line between systems installed at a long distance. The data is converted into serial data and transmitted, and the received serial data is converted in parallel. To this end, a monostable multivibrator is built in.

In addition, in order to increase the data rate in high-speed serial data transmission, a patent application has been filed for a device capable of sending transmission data on the rising edge and the falling edge of a clock. ). In other words, the present invention relates to a method of synchronous serial communication in order to transmit data at high speed in a high speed synchronous serial communication system. It is a method of dividing the odd clock and even clocks and transmitting them, and latching them at the receiving end to synchronize them.

However, the IBA physical layer protocol is defined to support 2.5Gbps data transfer, which is much faster than RS-422. Therefore, since it has a sufficient data rate, it is necessary to use a data transmission method at both edges.

Although multiple channels in parallel with high-speed serial lines are used to transmit large amounts of data at the same time, data skew between channels becomes a serious problem. Accordingly, a solution has been proposed in Korean Patent Application No. 1998-708973 (name of the invention: a system and method for high speed multi-channel data transmission that is not sensitive to skew) to solve the skew problem between channels. That is, by performing a high-speed serial data transmission through a multi-serial channel, a method and apparatus for receiving a multi-channel digital serial coded signal and convert it to a synchronized binary character set. The charge pump phase locked loop receives the transmitted reference clock and derives a multi-phase clock from the reference clock. In particular, it is a method for receiving multi-channel serial signals, correcting skew in sampling of each serial signal, and synchronizing binary characters in one channel with corresponding binary characters in another channel.

In addition, the high-speed data transmission method using serial lines connected in parallel is also applied through optical channels. In this case, skew between data transmitted in parallel channels remains a serious problem. "Nobuhiro Fujimoto, Atsuo Ishzuka, Skew-Free Parallel Optical Transmission Systems, Journal Of Lightwave Technology, Vol, 16. No. 10. Oct. 1998." It was also published in the paper.

Many optical channels are used for high-speed serial lines, and there are still skew problems in the Wavelength Division Multiplexing (WDM) scheme, which is widely used in such optical channels, and has been filed in US Pat. No. 4,677,618 to eliminate them. Briefly, this technique is a method of simultaneously transmitting digital data through a single line using frequency or WDM technology. This method divides one byte into independent bits and transmits them simultaneously with different time delays. I used it. In case of transmitting data on several channels at the same time, channel delay calculation and control circuit is placed in the center to reduce the skew between channels. This is still a skew problem.

However, the standard specification for InfiniBand (InfiniBand Trade Association, InfiniBand Architecture Specification Volume 1,2,3 Oct 24. 2000) has already been provided standardized, and this standard specification is a layer for data transmission between computers through InfiniBand. The star protocols are defined and the protocols of the Infiniband physical layer are also defined. Here, the IBA physical layer protocol defines a skew problem solving method, which is intended to be solved in the prior art, and suggests a solution for solving the skew problem.

Accordingly, an object of the present invention is to provide a high-speed data transmission / reception apparatus of an Infiniband system capable of transmitting and receiving high-capacity data quickly and efficiently. In providing.

1 is a view showing the overall configuration of a typical Infiniband system.

FIG. 2 is a diagram showing the configuration of an Infiniband channel adapter in the processor node shown in FIG.

Figure 3 is a block diagram of a high-speed data transmission and reception apparatus of the Infiniband system according to the present invention.

4 is a block diagram of the training state machine shown in FIG.

5 is a block diagram illustrating an internal block configuration of the transmitter shown in FIG. 3;

6 is a diagram illustrating a connection configuration of a receiver, a lane recognizer, and a word aligner illustrated in FIG. 3.

FIG. 7 is a diagram showing the configuration of the serial converter shown in FIG. 3; FIG.

* Description of the symbols for the main parts of the drawings *

100: Infiniband physical layer 120: Transmission unit

130 receiver 140 serial converter

150: word sorter 160: lane recognition controller

170: training state machine 180: error handler

The high-speed data transmission and reception apparatus of the Infiniband system according to the present invention for achieving the above object, the link training to perform a physical layer initialization operation to determine the data transmission width between the ports of both ends, the number of data transmission lanes It also includes a serial transmission function for sending word data through a differential serial line, and a serial reception function for converting serial data received through a differential serial line into word data. An 8b / 10b encoder that converts transmitted 8-bit symbols into 10-bit symbols to reduce, a 10b / 8b decoder that converts received 10-bit into original 8-bit data, and extracts the clock from the symbols received through the serial line Clock error compensator to reduce errors and lane deskew circuit to correct synchronization between lanes And there is a characteristic that as the InfiniBand physical layer protocol compatibility to the implement to facilitate the InfiniBand physical layer and data transmission and reception are designed differently so.

According to an aspect of the present invention, in the high-speed data transmission apparatus of the Infiniband system, after multiplexing according to a selection control signal provided among symbols for controlling a transmission request and symbols for the physical layer in the link layer, and then select output Transmitting means for converting the packet byte stream to a bit stream; Training sequence generating means for generating a training sequence for initializing the physical layer and providing a selection control signal to the transmitting means; Lane recognition means for converting the received data by changing the lane according to the corresponding lane; Word alignment means for aligning words by eliminating skew generated between signals output when the training sequence is received through four lanes; Conversion means for converting the byte stream outputted from the transmission means into a serial bit stream and transmitting it externally through a connector, and converting the serial bit stream received from the outside into a parallel byte stream and outputting the same; Receiving means for decoding the serial byte stream provided by the conversion means, extracting only the necessary data from the decoded stream to provide to the link layer.

In addition, if an error occurs in the data received by the receiving means, further comprising error recovery means for recovering the generated error, the transmission means, the sequence generating unit for generating a plurality of sequences; And an encoder for converting the packet byte stream received from the link layer into a 10-bit stream according to an 8b / 10b coding scheme and providing the converted stream to the converting means.

The sequence generator may include: a training sequence generator for generating a training sequence; A skip sequence generator for generating a skip sequence; And an idle sequence generator for generating an idle sequence, wherein each sequence generator includes a counter for specifying an order for generating each sequence at an accurate time.

The training sequence generating means may include: a disable state machine, wherein the infiniband port maintains an output signal at a stop level and generates no response to received data; The InfiniBand port includes a sleep state machine that maintains the output signal at a stop level and generates a response only to the received training sequence; A polling state machine that starts when power is applied and sends a training sequence at the output and generates a response to the received training sequence; A configuration state machine for generating a temporary state signal for the transmitting means and the receiving means to go into an active state; A linkup state machine capable of transmitting packets over an InfiniBand port while maintaining normal link operational status; The recovery state machine may be configured to perform physical layer resynchronization, return the link to a normal state, and return the link when link synchronization fails, an error occurs, or a retry request signal is received from the link layer.

The converting means includes: a parallel / serial converter converting the parallel byte stream output from the transmitting means into a serial bit stream; A serial / parallel converter for converting a serial bit stream received from the outside into parallel byte data according to a provided clock signal; A clock regenerator for reproducing a clock from a serial bit stream input from an external source and providing the clock signal used for data conversion to a serial / parallel converter; A clock synchronizer for synchronizing a driving clock of the parallel / serial converter according to an externally provided clock; And a comma detector for detecting a comma signal that is a control symbol from the parallel byte data converted by the serial / parallel converter and then providing the converted parallel byte data to the receiving means.

On the other hand, the receiving means includes a decoder for converting the received 10-bit stream into an 8-bit stream; A word aligner that aligns words by removing skew generated between signals input through a plurality of lanes when a training sequence is received; A function control symbol remover which removes received symbols for physical layer control from the symbols transmitted after word alignment is completed and extracts only pure data to provide to the link layer; The lane recognizer 132 includes a lane recognizer that converts data received by changing lanes according to the corresponding lane. Here, the symbols for controlling the physical layer are COM, IDLE, TS, SKIP symbols, and the control symbol remover transmits data to the link layer when the physical link is normally in an up state.

The word aligner receives a training sequence sent to four TBIDE outputs, checks the order of COMs in each lane, corrects a difference between a COM input first and a COM input later, thereby performing synchronization between lanes.

Hereinafter, a preferred embodiment of a high speed data transmission apparatus of an Infiniband system according to the present invention will be described in detail with reference to the accompanying drawings.

1 is a view showing the overall configuration of a typical Infiniband system.

In the IBA system shown in FIG. 1, several computer systems, storage systems, and I / O modules are connected through an InfiniBand network.

Computer systems and storage systems can be connected via InfiniBand switches and InfiniBand routers to exchange information. Each terminal node can be a process node, a RAID system that is a storage device, or an I / O chassis that can connect multiple Infiniband channel adapters.

The part connecting Infini band network and nodes is composed of HCA and TCA. HCA is mainly a device that connects the processor node and Infiniband, and TCA is a device that connects the I / O node and Infiniband.

The present invention may exist in all parts to which the infiniband of FIG. 1 is connected. All InfiniBand connection parts such as HCA, TCA, switches, routers, etc. need a physical layer device, and the present invention can be used for this purpose.

FIG. 2 is a diagram illustrating a configuration of an InfiniBand channel adapter in the processor node illustrated in FIG. 1, wherein the process node 10 connects a bus 20 to which the processors 50 exchange data, a memory, an input / output device, and the like. It is connected to the north bridge 60. Most Infiniband channel adapters 30 are connected to the north bridge 60 or the HCA 30 is directly connected to the processor bus 20. This can vary depending on which host interface you are using. The present invention is applicable regardless of which host interface the HCA has.

The present invention exists within the HCA 30, which is divided into a transport layer 40, a network layer 40, and a physical layer 40 therein. Each layer exchanges protocols with the same layer of the other party.

The upper layer depends on the services of the lower layer, and the lower layer provides services to the upper layer. This type of hierarchy is widely used in most communication systems because these layers can be defined independently regardless of how the lower layers are formed and how they are implemented.

The InfiniBand Physical Layer (IBPHY) 100 is connected to the link layer 70 at the top and 80 to the physical differential serial cable or the optical channel at the bottom.

The Infiniband physical layer 100 is a physical connection unit that is the most basic in the Infiniband connection network. The links of the Infiniband physical layer 100 are physically terminated at the ports, and the interconnection method between each port performs point-to-point full bidirectional signal transmission. That is, data is transmitted only in one direction, but there are separate transmission and reception channels, so that data is transmitted in both directions at the same time. The data rate of the encoded Infiniband physical layer 100 on the media is 2.5 Gbps in one direction. This results in a data rate of 500 MByte / sec in both directions.

In addition, the Infiniband physical layer 100 can extend up to four 2.5 Gbps lanes 100 as shown in FIG. 2, thus, the net data rate of the physical layer having four lanes is 2 GByte / sec.

Infiniband physical layer 100 is a training state machine (TSM) having a state machine for generating a training sequence for the initialization operation of the physical layer, as shown in Figure 2, the lane is changed Lane Identifier Controller (LIC), which converts received data into the corresponding lane, eliminates skew generated between signals output when training sequence (TS) is received through four lanes. Word Aligner (WA) for aligning words.

Such an Infiniband physical layer 100 will be described in detail with reference to FIG. 3.

3 is a block diagram illustrating a high speed data transmission apparatus of the Infiniband system according to the present invention.

As shown in FIG. 3, the Infiniband physical layer 100 converts the byte stream 71 input from the link layer 400 into a bitstream through 8b / 10b encoding, and the converted bitstream is parallel / A serial converter (differential serial transceiver) is sent to the Infiniband connection network 81.

In addition, the bitstream 80 received by the serial / parallel converter in the InfiniBand connection network 82 is converted into a byte stream through 10b / 8b decoding, and then transferred to the link layer 400 through the connection network 72. do. In addition, the Infiniband physical layer 100 mediates the speed arbitration of the physical link and the width of the link to initialize the link to an active state and monitor the state of the activated link.

As shown in FIG. 3, the Infiniband physical layer 100 may be composed of a transmitter 120, a receiver 130, a training state machine 170, and a serial converter 140.

The transmitter 120 has a function of multiplexing a symbol requested for transmission in the link layer 400 and a symbol for physical layer control, and a function of converting an 8-bit stream into a 10-bit stream according to an 8b / 10b coding scheme. .

Training state machine 170 is a state controller for training sequence control performed at the physical layer.

The receiver 130 includes a control symbol remover that selects only pure data, a word aligner 150 that adjusts skew between lanes, a lane recognition controller 160 which automatically recognizes lanes, and holds inverted lanes, and 10 bits. It may consist of a 10b / 8b decoder that converts the stream into 8 bits.

The serial converter 140 converts a word transmitted from the transmitter 120 into a bitstream and transmits it to a cable through a differential serial transceiver, or converts a bitstream received by the differential serial transceiver into a byte stream. .

In addition, the Infiniband physical layer 100 may include an error handler 180 that may process an error in the received data.

The error controller 180 provides an error occurrence monitoring signal to the link layer 400 when an abnormally generated bitstream is received, an order of training sequences is changed, or an error occurs when adjusting lane skew.

In addition, it has a built-in performance counter to store the number of times an error occurs so that the InfiniBand system manager can refer to it at any time.

In the Infiniband physical layer 100 illustrated in FIG. 3, four modules 110 are provided for each lane so that four Infiniband physical lanes (LX) can be connected in parallel to have a 4x data rate. However, the circuits 150 and 160 for controlling the lanes exist one by one.

Here, the detailed configuration and operation of the training state machine 170 will be described.

4 is a block diagram illustrating a training state machine of FIG. 3.

The training state machine 170 shown in FIG. 4 performs an InfiniBand physical layer 100 initialization operation and a link error recovery operation. The training state machine 170 may be divided into a transmitter and a receiver. Configure state machines and have a total of six internal state machines. That is, the transmitting and receiving portions of the training state machine 170 are polled state machines 171 and 174, configuration state machines 172 and 175, and a recovery state machine, respectively. 173 and 176 may be configured respectively.

When in the disabled state 178, as shown in FIG. 4, the InfiniBand port maintains the output signal at the stop level and does not respond to received data.

In the sleep state 177, the infiniband port maintains the output signal at the stop level as in the disable state, and responds only to the received training sequence TS.

On the other hand, in the polling state, the state is basically a transition when the power is applied. The InfiniBand port sends out training sequences at the output and only responds to incoming training sequences.

The polling state can identify 1x and 4x connections when receiving a training sequence, and can automatically maintain this setting. By monitoring whether data is transmitted to the lane, 1x and 4x connections can be checked.

The configuration state is a temporary state for the transmitter and receiver to go active.

Perform this step on the InfiniBand port and transition to the linkup state. The link up state is a normal link operation state, and the InfiniBand port is in a state capable of transmitting packets. The recovery state performs physical layer resynchronization and returns the link to normal state. This state is entered when link synchronization fails, a major error occurs, or a retry request is made at the link layer. When such an error occurs, the training state machine 170 informs the error controller 180 of the content.

Hereinafter, a detailed configuration and operation of the transmitter 120 shown in FIG. 3 will be described.

5 is a block diagram illustrating an internal block configuration of the transmitter shown in FIG. 3.

As shown in FIG. 5, the transmitter 120 includes a transmission symbol multiplexer and an 8b / 10b encoder 129.

The transmission symbol multiplexer includes a TS1 training sequencer 121, a TS2 training sequencer 123, a skip sequencer 125, and an idle sequencer 127.

The TS1 training sequence 121 is connected to a counter 122 used to generate a TS1 symbol, and the TS2 training sequencer 123 is connected to a counter 124 used to generate a TS2 symbol, and a SKIP sequencer ( 125 is connected a counter 126 used to generate a SKIP symbol.

The idle sequencer 127 is connected with a counter 128 used to generate idle symbols.

These counters are used to specify the order for generating the symbol at the correct time. The selection signal of the transmission multiplexer is driven by the training state machine 170. After the training state machine 170 confirms which sequencer to operate, it drives the enable signals (TS1 Enable, TS2 Enable, Skip Enable, and Idle Enable) of each sequencer.

The training sequencers 121 and 123 generate TS1 and TS2 which are sequencers for link initialization. The purpose of using TS1 and TS2 is as follows. Lane skew removal function to remove skew between lanes when transmitting 4x or more data, lane identification function to correct when lane change is different between two points connected by IB cable, and +/- connection of one lane It provides a polarity function to correct the change in case of change. Accordingly, the training sequencers 121 and 123 periodically generate TS symbols during a predetermined time interval to eliminate skew that may occur between lanes generated during 4x transmission.

The skip sequencer 125 is used for clock tolerance compensation and consists of COM and three consecutive skip symbols. Since the unit interval of symbols is 400 ps +/- -100 ppm, the clock difference between the receiving side and the transmitting side becomes 200 ppm in the worst case. Thus, if 5000 clocks have elapsed since the link was trained, the clock phases of reception and transmission may differ by one clock.

In addition, the serial converter 140 shown in FIG. 3 maintains the received signal and the clock domain of the transmitting side by using an imperial buffer. However, the clock domain should be performed in a safe time domain when using an emergency buffer. In order to provide such a safe time domain, the skip sequencer 125 transmits skip symbols at regular time intervals.

Meanwhile, the idle sequencer 127 shown in FIG. 5 drives the IDLE symbol when there is no packet transmission request in the link layer. While the link is not transmitting packets, no packets are transmitted, but idle symbols generated in the idle sequencer 127 continue to be transmitted according to a unique generation algorithm.

The pseudo-random data pattern order of idle symbols may be expressed as in Equation 1 below.

LFSR = X ¹¹ + X ⁹ + 1

Meanwhile, the 8b / 10b encoder 129 converts the packet bitstream generated under the above conditions into a 10-bit stream according to the 8b / 10b coding scheme. The generated 10-bit stream is transmitted to the serial converter 140.

FIG. 6 is a diagram illustrating a connection configuration of a receiver, a lane recognizer, and a word aligner illustrated in FIG. 3.

The receiving unit 130 includes a control symbol remover 131, a lane recognizer 132, a word alignment buffer 133, a symbol decode buffer before the inter-lane skew adjustment (BDSB) 134, and a 10b / 8b decoder. And 135. In addition, the receiver 130 is connected to the lane recognition controller 150 and the word aligner 160.

Here, the lane recognition controller 150 and the word aligner 160 may be configured one by one, but the control symbol controller 131, the lane recognizer 132, the word alignment buffer 133, and the symbols before the interlane skew adjustment are performed. Since the storage buffer 134 and the 10b / 8b decoder 135 should be one for each lane, four storage buffers 134 and 4 may be configured to support 4x lanes.

The control symbol remover 131 removes the received symbols for physical layer control from the symbols transmitted after word alignment is completed, and extracts only pure data. These physical layer control symbols are COM, IDLE, TS, SKIP symbols.

The control symbol remover 131 transmits data to the link layer when the physical link is normally in an up state.

The lane recognizer 132 performs a function of changing the received data according to the lane by changing the lane.

The lane recognition controller 150 detects whether the data is received in the normal lane or the changed lane based on the received TS value, and then controls the lane recognizer 132 according to the detected signal to the correct lane. It is to control data to be received.

In addition, the lane recognition controller 150 notifies the training state machine 170 illustrated in FIG. 3 when the lane change is detected. Training state machine 170 drives a lane change signal in the configuration state machine. Accordingly, when the signal is driven, the lane recognition controller 150 changes the selection signal of the lane recognizer 132 and transmits data to the changed lane from that time.

When the word aligner 160 receives the training sequence TS, the word aligner 160 removes the skew generated between the signals input through the four lanes and performs a function of positioning the word.

Meanwhile, the word aligner 160 receives training sequences sent to four TBIDE outputs as inputs, checks the order of COMs in each lane, and corrects the difference between the first COM input and the later COM input to perform synchronization between lanes. do. Symbol storage buffer before inter-lane skew adjustment to align the symbols output from four word alignment buffers 133, one word aligner 160, and 10b / 8b decoder 135 in units of 16 bits for word alignment. (BDSB) 134.

The 10b / 8b decoder 135 shown in FIG. 6 converts the received 10-bit stream into an 8-bit stream using the 10b / 8b decoder 135. It has a function of detecting an error on the received 10-bit stream, and when an error occurs, it is notified to the error handler 180.

7 is a diagram showing the configuration of the serial converter shown in FIG. 3, which is an internal configuration diagram of transmitting and receiving a bit stream through a cable line by converting a serial bit into a byte or a byte into a serial bit.

The serial converter 140 as shown in FIG. 7 includes a parallel / serial converter 141, a serial / parallel converter 145, a clock recovery 143, a clock synchronizer 142, and a COM detector 144. Can be.

The parallel / serial converter 141 converts the parallel input byte data encoded by the 8b / 10b encoder shown in FIG. 3 into serial bit data and provides the same to the IB 4x connector 500 through the Tx buffer.

The serial / parallel converter 145 converts the serial bit stream received through the Rx buffer into parallel byte data according to the clock signal provided by the clock recovery 143, and then converts the converted parallel byte data into the comma detector 144. To provide.

The clock recovery 143 regenerates a clock from a serial bitstream input from the outside 200 and provides the clock recovery signal to the serial / parallel converter 145 as a clock signal used for data conversion.

The clock synchronizer 142 synchronizes an external clock with an internal clock, and the comma detector 144 is a comma that is a control symbol in parallel byte data converted by the serial / parallel converter 145. After detecting the signal, the converted parallel byte 10b data is provided to the 10b / 8b decoder of FIG. 3.

The high-speed data transmission and reception apparatus of the Infiniband system according to the present invention as described above is applied to the physical layer of the Infiniband system that is widely expected to be used as a connection network in a high-performance clustering computer system.

Infini Band has completed international standardization work, but no specific implementation is mentioned. Accordingly, the present invention proposes a method for efficiently performing a physical layer protocol in a computer system using an Infiniband connection network, and proposes a physical layer structure capable of implementing the same.

Since the present invention has proposed a method and structure for implementing an Infiniband physical layer, the present invention can be applied to all devices physically connected to the Infiniband network, for example, HCA and TCA, as well as Infiniband switches and routers. . In addition, since the present invention proposes an implementation method and structure to comply with the Infiniband standard protocol, it can be connected and operated with other Infiniband disadvantage layer devices implemented in any way. In addition, since the inside of the physical layer is implemented to have 4x performance, it is possible to transmit and receive data four times as fast and efficiently as the physical layer having a normal 1x lane.

Claims (11)

In the high-speed data transmission and reception apparatus of the Infiniband system, Transmission means for multiplexing according to a selection control signal provided among symbols for controlling a physical layer and symbols requested to be transmitted in the link layer, and then converting the output packet byte stream into a bit stream; Training sequence generating means for generating a training sequence for initializing the physical layer and providing a selection control signal to the transmitting means; Lane recognition means for converting the received data by changing the lane according to the corresponding lane; Word alignment means for aligning words by eliminating skew generated between signals output when the training sequence is received through four lanes; Conversion means for converting the byte stream outputted from the transmission means into a serial bit stream and transmitting it externally through a connector, and converting the serial bit stream received from the outside into a parallel byte stream and outputting the same; And a receiving means for decoding the serial byte stream provided by the converting means, and extracting only necessary data from the decoded stream and providing it to the link layer. The method of claim 1, And an error recovery means for recovering the generated error if an error occurs in the data received by the receiving means. The method of claim 1, The transmission means, A sequence generator for generating a plurality of sequences; And an encoder for converting the packet byte stream received from the link layer into a 10-bit stream according to an 8b / 10b coding scheme and providing the converted signal to the converting means. The method of claim 3, The sequence generator, A training sequence generator for generating a training sequence; A skip sequence generator for generating a skip sequence; High speed data transmission and reception apparatus of an Infiniband system including an idle sequence generator for generating an idle sequence. The method of claim 4, wherein Each of the sequence generators includes a counter for specifying a sequence for generating each sequence at the correct time. The method of claim 1, The training sequence generating means, The InfiniBand port maintains an output signal at a stop level and does not generate any response to received data; The InfiniBand port includes a sleep state machine that maintains the output signal at a stop level and generates a response only to the received training sequence; A polling state machine that starts when power is applied and sends a training sequence at the output and generates a response to the received training sequence; A configuration state machine for generating a temporary state signal for the transmitting means and the receiving means to go into an active state; A linkup state machine capable of transmitting packets over an InfiniBand port while maintaining normal link operational status; A recovery state machine that performs physical layer resynchronization and returns the link to a normal state, and recovers the link when link synchronization fails, an error occurs, or a retry request signal is received from the link layer. High speed data transmission and reception device. The method of claim 1, The conversion means, A parallel / serial converter for converting the parallel byte stream output from the transmitting means into a serial bit stream; A serial / parallel converter for converting a serial bit stream received from the outside into parallel byte data according to a provided clock signal; A clock player for reproducing a clock from an externally input serial bit stream to provide a clock signal used for data conversion to a serial / parallel converter; A clock synchronizer for synchronizing a driving clock of the parallel / serial converter according to an externally provided clock; A high-speed data transmission of an infiniband system including a comma detector for detecting a comma signal which is a control symbol from the parallel byte data converted by the serial / parallel converter and then providing the converted parallel byte data to the receiving means; Receiving device. The method of claim 1, The receiving means, A decoder for converting the received 10-bit stream into an 8-bit stream; A word aligner that aligns words by removing skew generated between signals input through a plurality of lanes when a training sequence is received; A control symbol remover which removes received symbols for physical layer control from the symbols transmitted after word alignment is completed and extracts only pure data to provide to the link layer; The lane recognizer 132 is a high speed data transmission / reception apparatus of an Infiniband system including a lane recognizer that converts data received by changing lanes according to a corresponding lane. The method of claim 8, The symbol for controlling the physical layer is a COM, IDLE, TS, SKIP symbol high speed data transmission, reception apparatus of the system. The method of claim 8, And the control symbol remover transmits data to the link layer when the physical link is normally in an up state. The method of claim 8, The word sorter, Infiniband high-speed data transmission / reception device that receives the training sequence sent to 4 TBIDE outputs as input and checks the order of COM of each lane and corrects the difference between COM input first and COM input later. .