JP2003218747A - Test system and operational method of the test system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an improved parallel channel bit error rate tester and a method for testing communication networks or the like which use the tester. <P>SOLUTION: Test systems (10, 25) contain generators (12, 22) and analyzers (13, 21) that co-operate for testing a device (11) provided with a plurality of device communication channels. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION This invention relates to testing high speed communication channels and, more particularly, to an improved parallel channel bit error rate tester and method for testing such channels using the same. The invention also relates to the identification and synchronization of alternating channels in a parallel channel bit error rate tester.

[0002]

Parallel channel bit error rate testers are commonly used in communication systems having a plurality of separate channels. Such a tester provides a means to test many channels simultaneously, thus reducing the time required to test a communication system. In addition, such testers can detect errors that are present only when multiple channels are operating simultaneously. For example, errors resulting from crosstalk between two channels will only appear when data is present on both channels. A parallel channel bit error rate tester is typically a pattern generator that produces a signal for each channel to be tested (pattern generator), and whether the received signal matches the signal produced by the pattern generator. An analyzer is included to test the signal received at the end of the communication channel to determine if.

Parallel channel bit error rate testers may be utilized to test communication channels having higher data rates than those of the tester's individual channels. To do this, the individual test signals from the pattern generator channels are multiplexed together to form the high speed signal transmitted to the high speed channel. At the end of the communication channel, the high speed data stream is demultiplexed and fed to the parallel channel bit error rate tester's error analyzer channel.

Depending on the application, the multiplexer and demultiplexer circuits may be part of the instrument or the device under test (D
UT; Device Under Test). Communication systems are well known in the communication arts, where, for example, a number of relatively low speed signals are multiplexed to form a single high speed signal that is transmitted on a high speed link and then demultiplexed. In such systems, parallel channel bit error rate testers need not include multiplexers and demultiplexers if they are part of the communication system being tested.
On the other hand, if the communication system being tested has only one input and output channel, multiplexers and demultiplexers must be provided as part of the test system to test the high speed link.

The conversion of a parallel stream into a serial stream through a multiplexer and demultiplexer and then into a parallel stream is such that the pattern input at the i th channel of the transmitter is not received at the i th channel of the receiver. Such rearrangement of the data pattern may lead to. This can occur if the phases of the various multiplexers and demultiplexers are not properly synchronized. This lack of synchronization can result from the multiplexers not being synchronized with each other, the demultiplexers not being synchronized with each other, or the demultiplexers as a group not being synchronized with the multiplexers as a group. is there. Often an unknown time delay through the communication link results in loss of synchronization between the multiplexer and the demultiplexer. Each of these conditions may result in reconstruction of the data pattern.

These data reconstructions pose a problem, since the bit error rate test is performed on the basis of the recognition of the data pattern expected in the respective channel by the error analyzer. If the predicted data pattern is reconstructed, the test is invalid unless this reconstruction can be identified. Once identified, appropriate compensation can be set.

Basically, the reconfiguration can be eliminated by synchronizing the multiplexer circuits with each other and / or by synchronizing the demultiplexer circuits with each other and then by synchronizing the demultiplexer circuits with the multiplexer circuits. At this point, the data streams entering the analyzer can be synchronized with each other in time. While communication multiplexers that are synchronized with each other (and also have synchronized phases) can be constructed, it is almost practical to realize a communication demultiplexer that can be synchronized with each other and share a common internal phase. is not. This is mainly due to two phenomena. First, the demultiplexer often recovers the data clock from the data passing through it. The clock recovery circuit (clock generation circuit) in these demultiplexer circuits has n division circuits. Here, n is the fanout number (output number) of the demultiplexer. These circuits are typically initialized in a relatively random state with respect to the multiplexer, and therefore are generally not properly synchronized. Second, the unavoidable time delay of the propagation of the data stream through the communication link connecting the multiplexer and demultiplexer results in the data arriving at a phase that is relatively unknown to the multiplexer data.

[0008]

SUMMARY OF THE INVENTION In general, it is an object of the present invention to provide an improved parallel channel bit error rate tester and method for using it to test communication networks and the like.

[0009]

These and other objects of the present invention will become apparent to those skilled in the art from the detailed description of the invention set forth below and the accompanying drawings.

The present invention is a test system that includes a generator and an analyzer that work together to test a device having multiple device communication channels. The device has a plurality of input terminals and their corresponding output terminals, each input terminal routing data to a corresponding one output terminal. The generator includes a plurality of test pattern channels. Each test pattern channel includes a pattern generator reference memory for storing the test sequence to be communicated to the input of the device and circuitry for repeatedly transmitting the test sequence to one channel of the device. The analyzer includes a plurality of analyzer channels. Each analyzer channel has an input terminal for receiving a channel input signal, an analyzer pattern reference memory for storing a reference pattern utilized by the analyzer channel, a signal received in one communication channel of the device and its And a comparison circuit for comparing the reference patterns. The comparison circuit provides a bit error value indicative of the degree of mismatch between the reference pattern and the received signal.
The test system includes a program that operates an analyzer and a generator, which program provides a mapping from device input channels to device output channels. The program is included here by (a) a set of mapping test patterns that are mutually exclusive, such that one of the generator and the analyzer has its own test pattern stored in each reference memory. Loading the reference memory; (b) causing the other of the generator and the analyzer to load all memories with one of the set of mapping test patterns; (c) the channel of each analyzer, Comparing a reference pattern stored in a channel with a channel input signal received in that channel; (d) 1 provided by a comparison circuit
Determining whether one bit error value is less than a bit error threshold and, if so, mapping an analyzer channel having a bit error value less than said bit error threshold to a generator channel having the same mapping test pattern. To do. The test system repeats the operations of (a)-(d) until the controller can assign all input channels to their corresponding output channels, the different one of the mapping test patterns being (b). Loaded into memory at. The test system utilizes the above algorithm to test one or more corresponding channels when mapped, and to test the remaining channels in association with the one or more channel mappings. Information about is also available. In the preferred embodiment of the invention, the reference memory of the generator, rather than the analyzer, is loaded during the input-to-output channel mapping operation with mutually exclusive sets of mapping test patterns. After the test system maps the input and output channels of the device, the generator loads a set of bit error test patterns into the controller's reference memory and to continue the bit error test.

[0011]

DETAILED DESCRIPTION OF THE INVENTION The manner in which the present invention provides its advantages is that the device under test (DUT; device under test) 11 (hereinafter
It can be more easily understood by reference to FIG. 1, which is a schematic diagram of a parallel channel bit error rate tester (test system) 10 connected to a DUT). In its simplest form, the parallel channel bit error rate tester 10 comprises a pattern generator 12 and an error analyzer 13 connected via a DUT 11. The pattern generator 12 generates a predetermined pattern for the input of the DUT 11. This pattern is the pattern memory 121
Remembered in. The error analyzer 13 compares the received data with the known patterns stored in the pattern memory 131 and measures the bit error (BER). The pattern generator has a clock source 15, which triggers the generation of test data. In order to perform the bit error rate test, the error analyzer 13 must be clocked at the same rate as the incoming data stream. This is accomplished by triggering the error analyzer 13 and the pattern generator 12 from a common clock source 15 or by having the error analyzer work with a clock recovered from the data. In the embodiment shown in FIG. 1, it is assumed that the error analyzer 13 is close enough to the pattern generator 12 to share the same clock. The choice is made depending on the application and the proximity of the error analyzer 13 to the pattern generator 12. When the analyzer portion is far from the pattern generator 12, the clock recovery circuit (clock generation circuit) 20 is included in the analyzer 21, as shown in FIG. The embodiment contained in the container 13 can also be implemented.
FIG. 2 shows a parallel channel bit error rate tester 2 when the analyzer 21 is located far from the pattern generator 22.
5 is a schematic diagram of 5. To simplify the drawing, the pattern memory is omitted from the drawing. Clock generation circuit 20
Are conventional and therefore will not be described in detail here. Error analyzer 21 and pattern generator 22
Generally have a communication path 17 for communicating instructions between each other.

The pattern sent to the DUT 11 must be a known pattern. The most common type of pattern is the pseudo-random bit sequence (PRBS;
Pseudo Random Bit Sequences), Pseudo Random Word Sequences (PRWS)
s) and a memory-based pattern. The memory base pattern is a pattern to be sequentially read during the test and is a pattern loaded in the memory before the test. PRBS is a sequence generated from the combination of shift register and logic. The data in such a sequence appears random, but is in fact deterministic. There is a known family of standard PRBS used to test different types of channels. The main advantage of PRBS is that these sequences are deterministic, while they probably have the same statistical and spectral properties of random data. P
RWS is a parallel variant of PRBS, where the sequences are spread over multiple parallel channels, so that the bits of the PRBS appear in a periodic sequence over all channels. The memory base pattern can take any form, including that of PRBS / PRWS. The only restrictions on the memory base pattern are the size of the memory and the speed at which it can be accessed. The memory-based pattern simulates various communication protocols by constructing a pattern of repetitive patterns such as those utilized for headers having PRBS / PRWS patterns in place within groups that simulate data. Can be used to In many cases, synchronizing channels utilizing the PRBS / PRWS pattern is
Once the S / PRWS algorithm is known, it is easier than the memory-based pattern because it only needs a small set of bits to uniquely determine the test sequence.

Basically, parallel channel bit error rate testers are well suited for testing telecommunications and network systems. These systems often have multiple data streams that are multiplexed into one or more higher speed streams before being transmitted over the high speed channel. The high speed stream received at the far end of the channel is then demultiplexed into its constituent or tributary streams. Reference is now made to Figures 3 and 4, which are schematic diagrams illustrating the types of multiplexing schemes typically utilized in telecommunications systems. Multiplexing can be done at a single level as shown in FIG. 3 or at multiple levels as shown in FIG. According to FIG. 3, the tributary data stream 30
Are input to a multiplexer 31, which in turn selects one bit from each data stream and outputs the combined high speed data stream to a communication link 32 to combine the data streams. At the terminal terminal of the communication link, the demultiplexer 33 receives the high speed data stream and
Route bits to successive ones of the output data streams shown in FIG.

The multiplexer and demultiplexer are
It can be thought of as including a pointer that indicates the next channel to service. In the case of a multiplexer, the pointer indicates the next data input to use as the source of the bits to place on the communication link 32. In the case of a demultiplexer, the pointer indicates the next data output line indicator to receive a bit from the communication link 32. Each pointer is incremented modulo N after M data bits have been transmitted in the 1: N multiplexer or demultiplexer. In the simplest case, M = 1. If the pointers are not properly synchronized, the data stream leaving the demultiplexer channel will displace relative to the data stream entering the multiplexer. This problem,
It can be modified by resetting the pointers in the multiplexer or demultiplexer to synchronize the multiplexer and demultiplexer. Note that if M> 1, then one of the counters must be reset to synchronize the multiplexer and demultiplexer.

According to FIG. 4, the multiplexer and demultiplexer can be made up of cascaded stages of smaller multiplexers and demultiplexers, respectively. In the example shown in FIG. 4, the multiplexer 31 shown in FIG. 3 has been replaced by a two-stage smaller multiplexer shown at 41-44. Similarly, demultiplexer 33 has been replaced by a two-stage smaller demultiplexer shown at 51-54. In a staged multiplexer and demultiplexer, the component multiplexers and demultiplexers must also be synchronized with each other.

The present invention is based on an algorithm which identifies the channel permutation that occurs when parallel data passes through a communication multiplexer and a communication demultiplexer. By identifying and compensating for these channel permutations, the present invention avoids the problem of resynchronization of various multiplexers and demultiplexers. The manner in which the algorithm operates can be more easily understood with reference to FIG. Figure 5
3 is a flow chart of one embodiment of an algorithm according to the present invention for identifying channel swaps resulting from the loss of synchronization. Let N be assumed to be greater than 1 to represent the number of the channel to be tested. The algorithm starts by loading N unique bit patterns into N different generator channels, as shown in step 61. In the following discussion, patterns are numbered by the generators associated with them, i.e. pattern k
Is the pattern generated by generator k.

The tester then selects a pattern and loads this pattern into all N analyzer channels, as shown in steps 62 and 63. After that, the tester, as shown in step 64,
Try to synchronize the generator channel with all analyzer channels. This requires the generator to output a continuous data stream, with the analyzer timing adjusted to minimize the bit error rate. Note that this adjustment can be done manually or automatically, entirely in hardware, or in the context of software. In this step, the same delay is preferably added to each channel and the bit error rate of each channel is measured. This process is repeated for a particular value of delay until a channel is found whose bit error rate is below a predetermined threshold σ. Thus, this channel is considered synchronized.

Of the N different patterns received by the N individual analyzer channels, only one matches the pattern loaded into all analyzers.
To do. Therefore, the parser receiving the matched bit pattern (designated parser j) is the only one that can be synchronized. The bit error rate in the other channels remains large due to the mismatched patterns.
The input to analyzer j is known to come from generator k, as shown in step 65, and a single input-output pair is identified.

Next, the tester determines, as shown in step 66, if any of the analyzer channels are not assigned to generator channels. If such a channel exists, the algorithm loops back to step 62 with that channel as the analyzer channel. This step is repeated until all N analyzer channels have been assigned to the corresponding generator channels.

The analyzer channel can be synchronized utilizing a wide variety of sync test patterns, including special sync patterns. In general, these patterns are different from the patterns that one seeks to utilize during actual testing. However, actual test pattern data can be used if they match the unique pattern criteria described above. If the data to be transmitted is the desired data for the test, a time synchronization to align the analyzer channels with each other can be done to obtain all the identified channels that are time synchronized. And then the testing phase can start.

The analyzer and generator generally have a microcontroller that implements the algorithms described herein.
In the following description, the part of the test program that operates in the controller of the analyzer will be referred to as the “analyzer control program”, and the part of the program that operates in the controller of the generator will be referred to as the “generator control program”. To call. Also, the test sequence utilized to link the input channel from the generator to the input channel at the analyzer is referred to as the "synchronous test pattern". Also, the pattern used to perform the actual bit error rate measurement is referred to as the bit error rate pattern.

If the bit error rate pattern differs from the synchronous test pattern, the test pattern must be switched in both the generator and the analyzer before starting the actual bit error rate test. This switching is preferably accomplished by the analyzer program sending a signal / message telling the generator control program that the identification (same) portion of synchronization is complete. Upon receiving this message, the generator control program triggers the loading of the bit error rate pattern. When this is done, it sends a command to the analyzer control program that instructs the analyzer to prepare for the test. When the parser control program receives this command, it reloads that data segment to match the corresponding bit error rate pattern sent by the generator. The analyzer then time synchronizes to align the channels in time. To do this, the test data must contain a unique bit sequence that defines the known points in the test data in each channel. Once aligned, the system is ready for bit error rate testing.

In the embodiment where the analyzer obtains its clock signal from the data stream, or the demultiplexer generates its clock from the data stream, when the generator stops transmitting data, the clock at the analyzer side is Note the drift. If this drift is not important, or if the analyzer obtains its clock independent of the data, then two variants of this algorithm are that all channels are synchronized and available. Until it detects that the analyzer is loaded with N different patterns and the generator continues to be reloaded with one different pattern at a time.

From the above discussion it will be apparent that there are three distinct steps in a bit error rate test for communication systems etc., there are an identification or mapping step, a synchronization step and a test step. . Synchronization involves linking each generator channel to its corresponding analyzer channel to modify for all channel reconstructions. This step can be accomplished by modifying the physical wiring between the system under test and either the tester's analyzer or generator. Linking operations can also be achieved by changing the "logic wiring" within the analyzer or generator. For example, the data read into the analyzer portion from the demultiplexer output is typically stored in memory associated with a digital processor in the analyzer. The data for a particular channel is stored at a location defined by one or more memory pointers. Therefore, channels can be swapped by changing these pointer values. As used herein, the term "rewrite" refers to both physical and logical rewrite. There are two generally preferred embodiments of the tester according to the present invention.

In the first embodiment, the permutation found during the identification step is used to identify a rewrite between the demultiplexer output terminal and the analyzer input terminal. In the second embodiment, the test patterns in the analyzer are shuffled to compensate for the shuffle measured in the channel. Embodiments based essentially on a combination of these strategies can also be constructed. For example, the reshuffling of the connection between the demultiplexer output terminal and the analyzer input terminal can identify channel permutations. Then for the actual test,
In the analyzer memory, the rewriting is canceled and the test pattern is replaced.

An embodiment in which rewriting is basically performed on the generator side can also be realized. However, if these operations require interruption of the data generation, the multiplexer / demultiplexer circuit may not have a known phase when data generation resumes, and, therefore, in the identification step. The identification obtained is no longer valid. Since the state of the analyzer does not affect the phase of the multiplexer or demultiplexer, it is desirable to suspend the analysis of the data rather than the generation of the data.

If the bit error test pattern differs from the sync test pattern, the analyzer must communicate to the generator the need to switch the data set. Changes to the test pattern must occur so as not to interfere with synchronization, or the system must resynchronize utilizing the bit error test pattern or a portion thereof. If the channel is synchronized using the synchronization test pattern, the analyzer sends a message to the generator indicating that it is ready to start the bit error test. After that, the generator joins in a loop that switches the test sequence and repeatedly transmits each bit error test pattern. The analyzer must then determine when to start making bit error measurements. This is equivalent to determining at the analyzer side of the network under test when the start of the first bit error test pattern occurs.

If the analyzer is close to the generator and the delay in the communication between the respective control programs is negligible, then the analyzer and the generator will have some kind of signal during the signal where the switching took place. You just have to have a match. For example,
The generator can send an acknowledgment signal with a relative timing to the start of the bit error pattern in a manner known to the analyzer. If the delay through the network under test is significantly shorter than the time required to send a sequence, then the test data shall be sent in the middle of the current test sequence and start after the completion of the current sequence. The signal to represent can be utilized. Since the analyzer knows the length of the sync test pattern, it can switch patterns at the appropriate points.

If the analyzer is far from the generator, the time required for the analyzer to signal the generator and receive a positive response is to send one bit error rate test pattern. It can be considerably longer than that required. In this case, the analyzer must detect the point in the data stream entering its input terminal that corresponds to the beginning of the bit error test pattern. 1 of the present invention
In one preferred embodiment, the synchronization test pattern is
Forced to be the same length as the bit error test pattern. In such an embodiment, the analyzer may limit its search at the beginning of the bit error test pattern to that point in time corresponding to the beginning of a sequence of this length. This approach also
Note that the search time is improved if the bit error test pattern has an integer multiple length of the sync test pattern.

An alternative embodiment includes avoiding switching between sync data and test data. To do this, a unique sync bit must be embedded in the test data. This can be achieved by utilizing certain features of existing parallel channel bit error rate tester systems. Such systems utilize a memory device in which the sequence utilized to synchronize the timing in the channels consists of the sequence stored at a particular location in memory. The synchronization sequence is
It is typically a small part of the actual test sequence.
For example, the first 48 bits are specified in the Agilent 81250 tester for time synchronization test patterns. In this tester, the bit error test pattern is typically on the order of 3000 bits or more. For example, a common test frame desired by telecommunications equipment vendors is the SONET frame.
SONET frames to the emerging OC-768 standard contain more than 4 million bits. Further, the test sequence may include multiple copies of such frames. The analyzer utilizes 48 bits to synchronize the analyzer and generator channels, assuming that the corresponding channels are connected. Therefore, a parallel channel bit error rate tester according to the present invention can be implemented by inserting a control code to perform channel identification and rewriting prior to the synchronization and test phase switching normally performed in this tester. It can be realized in various testers.

The fixed small number of synchronization bits presents two problems for the implementation of the invention in such a system. First, the rest of the test pattern must be met by a pattern that keeps the clocks in the demultiplexer and analyzer synchronized. To do this, the pattern must include a long sequence of "1" s and "0" s. The maximum length of such a sequence is
It depends on the particular device or network being tested. To avoid such issuance, the data block should have a roughly balanced number of "1" s and "0" s and limit the duration of either "1" s or "0" s. To This can be done via a request in the user data or by a duration limit coding (RLL).
Can be achieved by utilizing some form or scrambling of the data. Note that the scrambling of data by its XOR logical combination with a PRBS sequence results in almost always a limited continuation of "1" s and "0s", except in pathological cases where the data and scrambling bits are identical. . In this case, the scrambled sequence is all changed to "0".

The second problem relates to tests where the test stage utilizes data that simulates a particular telecommunications format such as SONET or SDH. These formats typically have header information within each group identified by a particular format, and
Therefore it is not available for test data. These formats provide a particular location within the data group for the data to be transmitted. When testing a communication system configured to carry such a group, the test sequence typically includes these headers with the test data in locations provided for data transmission. The header is included, although it is not actually needed during the bit error test, so that the test data has the same frequency spectrum as the actual data transmitted within such a group. In many cases, the header data overlaps the area of test data memory designated for the time synchronization test pattern. The header data is fixed,
In addition, since it must include format-specific information, it cannot be conveniently used as a synchronization test pattern. In an advantageous embodiment of the invention, this problem is
It is avoided in such a tester by circularly shifting the data group so that the header information is placed in the portion of memory that is not used for synchronization at this time. The part of the group with its own sequence can then be placed in the part of the memory designated for synchronization.
Since every cyclic shift of the group preserves the frequency spectrum of the group, the shifted group is
It allows to continue on such existing test equipment while simulating the communication format in question.

The third embodiment utilizes separate sync and test blocks. The sync block is configured as described above. However, the test block also contains synchronization bits that are used by the test block to obtain timing synchronization once the channel connection is identified. The synchronization bits do not have to be unique for a given channel, since the channel has already been identified. This is
The requirement that the identification block must be the same size as the test block can be relaxed and the size of the test block utilized to verify the channel ID can be reduced. This reduces the time required for channel ID. Timing synchronization still has to be done in the test data block.

The above embodiment of the present invention provides a channel matching algorithm that determines the correspondence between each generator output channel and analyzer input channel without citing any matching found in the previous search. To use. If the structure of the multiplexer and demultiplexer is known, the previously determined match can be used to reduce the effort of finding the remaining match. Consider the simple case where the network under test includes a single stage multiplexer and a single stage demultiplexer. It is also assumed that the pointers in the multiplexer and demultiplexer increase by modulo M after each bit is transmitted or received. Here, M is the number of input and output channels. Knowing the relationship between the values of the pointers in the multiplexer and demultiplexer, the input-to-output port mapping can be calculated without further searching. In this case, the relationship can be determined, independent of M, from the first pair of input and output ports mapped in the analyzer. Therefore, the M-1 step search can be replaced by finding the first matched pair of channels and calculating the rest.

In more complex networks, additional pairs of input-output pairs must be determined before the rest can be calculated from the knowledge of the network.
However, the total number of pairs that must be determined by the search can still be significantly reduced if the structure of the multiplexer and demultiplexer is known.

The above is summarized as follows. That is, the test system (10, 25) comprises a generator (12, 22) and an analyzer (13, 2) working together to test a device (11) having multiple device communication channels.
Including 1). The device (11) has a plurality of input terminals and their corresponding output terminals, each input terminal being connected to a corresponding one of said output terminals. Correspondence between the input terminal and the output terminal corresponds to when the device (11) is switched to an off state or an on state, or the device (11) actively transmits data from the input terminal to the output terminal. If not, you can change it. Before performing a bit error rate test using the mapping test pattern, the test system (10, 25) determines (determines) the mapping between the input terminal and the output terminal of the device (11). Thereafter, the test system (10, 25) is able to switch the bit error rate test pattern without causing drift in the device (11) such that the correspondence between the input and output channels is impaired. it can.

Various modifications of the invention will be apparent to those skilled in the art from the foregoing description and accompanying drawings. Accordingly, the invention is limited only by the scope of the following claims.

[Brief description of drawings]

FIG. 1 is a schematic diagram of a parallel channel bit error rate tester connected to the device under test.

FIG. 2 is a schematic diagram of a parallel channel bit error rate tester when the analyzer is remote from the pattern generator.

FIG. 3 is a schematic diagram showing the types of multiplexing schemes typically utilized in telecommunications systems.

FIG. 4 is a schematic diagram showing the types of multiplexing schemes typically utilized in telecommunications systems.

FIG. 5 is a flow chart of one embodiment of an algorithm according to the present invention for identifying channel swaps resulting from loss of synchrony.

[Explanation of symbols]

10, 25 Parallel channel bit error rate tester (test system) 11 Device under test 12, 22 Pattern generator 13, 21 Error analyzer 15 Clock source 20 Clock recovery circuit 31 Multiplexer 33 Demultiplexer 121 Pattern memory 131 Pattern memory 131

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Daniel Wye Abramovich             California 94306,             Palo Alto, Kipling Street             3372 (72) Inventor Michael Jay Weinstein             California 94024,             Los Altos, Ferndan Avenue             ー 2025 (72) Inventor Heinz Earl Pritchuka             Halleberg, Alze, Federal Republic of Germany             Central Straße 22 F term (reference) 2G132 AA00 AB01 AC03 AD06 AE14                       AE23 AG02 AG08 AL00                 5K014 AA01 GA02 GA03 HA10                 5K028 AA01 AA14 MM14 PP02 PP12                       PP22 QQ02 RR04 SS24                 5K042 AA01 BA07 CA05 CA15 DA01                       DA27 EA02 EA06 FA15 GA02                       JA02 MA03

Claims (23)

[Claims] 1. A plurality of device communication channels, and
What is claimed is: 1. A test system comprising a generator and an analyzer cooperating to test a device connecting each input terminal of said communication channel to one output terminal of said communication channel, wherein said generator comprises a plurality of A generator pattern reference memory for storing a test sequence to be communicated to an input terminal of the device, and a test pattern in one of the communication channels of the device. And a circuit for repeatedly transmitting, wherein the analyzer has a plurality of analyzer channels, each analyzer channel receiving an input terminal for receiving a channel input signal, and a reference pattern used by the analyzer channel. An analyzer pattern reference memory for storing
A comparison circuit for comparing a signal received on one of the communication channels of the device with its reference pattern,
The comparison circuit provides a bit error value representative of the degree of mismatch between the reference pattern and the received signal, and the test system further comprises a program for operating the analyzer and the generator. And including: (a) a set of mutually exclusive mapping test patterns in one of the generator and the analyzer such that each reference memory has its own test pattern stored therein. Loading the reference memory contained therein by: (b) causing the other of the generator and the analyzer to load one of the sets of mapping test patterns into all the memories; (C) For each analyzer channel, the reference pattern stored in that channel and the reference pattern received in that channel. A channel input signal, and (d) determining if the one bit error value provided by the comparison circuit is less than a bit error threshold and, if so, the bit error value is Mapping the analyzer channels smaller than the bit error threshold to the generator channels having the same mapping test pattern. 2. The steps (a) to (3) of the program
The test system of claim 1, wherein (d) is repeated and different ones of the mapping test patterns are loaded into the memory in step (b). 3. The test system according to claim 1, wherein the reference memory of the generator is the reference memory loaded by the sets of mutually exclusive mapping test patterns. 4. The test system according to claim 1, wherein the comparison circuit compares the received signal shifted in time with the reference pattern. 5. Each mapping test pattern is a first unique to the mapping test pattern.
And a second sequence shared by all of the mapping test patterns, the second sequence being selected such that the device under test remains synchronized to the test system. The test system according to claim 1, wherein: 6. The second sequence comprises alternating "1" s.
And the test system according to claim 5, wherein the test system comprises "0". 7. The analyzer of claim 1, wherein the analyzer further includes a clock generation circuit that generates a clock signal from the received signal, the clock signal being utilized by the comparison circuit. Test system. 8. The analyzer or the generator contains information defining at least one structural element of the device to be tested, and the program includes that information and previously mapped generator channels and 8. The test system of claim 7, wherein information about one pair of analyzer channels is used to map one generator channel to one analyzer channel. 9. After the program maps each generator channel to a corresponding analyzer channel,
The test system of claim 1, wherein the program causes the generator to load a set of bit error test patterns into the reference memory in the generator. 10. The test system of claim 9, wherein the bit error test pattern has the same length as the mapping test pattern. 11. The analyzer loads the bit error test pattern into the reference memory in the analyzer channel in response to a signal indicating that the generator has loaded the bit error test pattern. The test system according to claim 10, wherein: 12. The program causes the analyzer to measure a bit error value when the generator sends the bit error test pattern, and the analyzer causes the analyzer channel and the generator channel to be measured. 10. The test system of claim 9, utilizing the mapping to determine a correspondence between. 13. The bit error test pattern is S
The test system according to claim 9, wherein the test system follows an ONET frame. 14. The bit error test pattern is S
The test system according to claim 9, wherein the test system follows a DH frame. 15. A generator and analysis cooperating to test a device having a plurality of device communication channels and connecting each input terminal of said communication channel to one output terminal of said communication channel. A generator pattern reference memory for storing a test sequence to be communicated to an input terminal of the device, the generator pattern reference memory comprising: A circuit for repeatedly transmitting the test sequence to one of the communication channels, the analyzer having a plurality of analyzer channels, each analyzer channel having an input terminal for receiving a channel input signal; An analyzer pattern reference memory for storing a reference pattern utilized by the analyzer channel,
A comparison circuit for comparing a signal received on one of the communication channels of the device with its reference pattern,
A method for operating a test system, wherein the comparison circuit is configured to provide a bit error value representative of a degree of mismatch between the reference pattern and the received signal, the method comprising: ) In one of said generator and said analyzer, said reference included by a mutually exclusive set of mapping test patterns such that each reference memory has its own test pattern stored therein. Loading a reference memory, (b) causing the other of the generator and the analyzer to load one of the sets of mapping test patterns into all the memories, and (c) respectively. In the analyzer channel of the reference pattern stored in the channel and the channel input signal received in the channel. Comparing; (d) determining whether the one bit error value provided by the comparison circuit is less than a bit error threshold and, if so, the bit error value is the bit error value. Mapping said analyzer channels smaller than a threshold to said generator channels having the same mapping test pattern. 16. The method further comprising repeating steps (a)-(d), wherein a different one of the mapping test patterns is loaded into the memory in step (b). Item 15. The method according to Item 15. 17. The method of claim 15, wherein the comparison circuit compares the received signal shifted in time with the reference pattern. 18. Each mapping test pattern is a first unique to the mapping test pattern.
And a second sequence shared by all of the mapping test patterns, the second sequence being selected such that the device under test remains synchronized to the test system. 16. The method according to claim 15, characterized in that 19. The test system includes information defining at least one structural element of the device to be tested, and the test system includes that information and previously mapped generator and analyzer channels. 16. The method of claim 15, wherein information on one pair of is used to map one generator channel to one analyzer channel. 20. After mapping each generator channel to a corresponding analyzer channel,
16. The method of claim 15, further comprising loading a set of bit error test patterns in the reference memory at the generator. 21. The method of claim 20, wherein the bit error test pattern has the same length as the mapping test pattern. 22. The bit error pattern is SONE
The method according to claim 20, characterized in that it corresponds to T frames. 23. The method of claim 20, wherein the bit error pattern corresponds to an SDH frame.