JP2003218179A - Inspection device and burn-in testing device for semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an inspection device and a burn-in testing device for a semiconductor device capable of specifying a defective mode and a fault mode, performing analysis and predicting market defects further. <P>SOLUTION: The burn-in testing device 300 is provided with a test pattern generation means 301 for generating a test pattern for performing a burn-in test, a semiconductor device 302 to be tested, a scan judgement means 303, and a time measurement means 305 controlled by the output signals of the scan judgement means 303 and the output signals of a memory judgement means 304. The burn-in test of the semiconductor device 302 to be tested is performed by supplying scan-in signals S102, memory test signals S103 and test mode control signals S101 from the test pattern generation means 301 to the semiconductor inspection device 100, time measurement is performed in the time measurement means 305 for the test result and the generation time of a defect/a fault is specified. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an inspection device for a semiconductor device having at least a logic circuit and a memory having a scan path design built therein, and in particular, a functional stress is applied to an internal circuit of the semiconductor device to perform a reliability test. Burn-in test equipment

[0002]

2. Description of the Related Art Conventionally, a burn-in test of a semiconductor device (hereinafter referred to as LSI) having a built-in scan path circuit is introduced in Japanese Patent Publication No. 7-70573 (cited reference 1).

Reference 1 discloses a scan path circuit for passing scan data inside an LSI, a test control circuit for controlling a test operation according to a test mode signal, and scan data based on a control signal from the test control circuit. It shows a scan data generating circuit for generating a signal and a scan clock generating circuit from the test control circuit.

Further, in the cited document 1, scan data is generated inside the LSI only by applying a test mode signal from the outside of the LSI, and a burn-in test operation is performed through a scan path circuit.

Further, among the burn-in tests, a so-called wafer level burn-in test in which the test is performed in a wafer state is introduced in Japanese Patent Laid-Open No. 2001-183425 (Cited document 2). In addition, reference document 2
Include a determination circuit that compares the outputs of the flip-flop circuits with a scan function, which is the final stage of each scan chain in a circuit composed of multiple test scan chains, and determines whether the values match. Shows.

[0006]

However, as many circuit functions are built in semiconductor devices and LSIs, not only are these inspections complicated and complicated, but some defects occur during the burn-in test. It will be difficult to identify. In addition, when a defect or failure occurs, the time cannot be specified, which makes it extremely difficult to predict the defect in the market and set appropriate burn-in test conditions and time.

Therefore, the invention of the present application eliminates such inconveniences, and is capable of specifying a defective portion in a burn-in test, specifying and analyzing a defective mode and a failure mode, and further capable of predicting a market defect. The purpose is to provide.

[0008]

In order to solve the above problems, a semiconductor device inspection apparatus according to the present invention is a semiconductor device inspection apparatus including at least a scan-designed logic circuit and a memory. A scan-in signal applied to a scan-designed logic circuit, a memory test signal applied to the memory, and an external test mode control signal are input to the semiconductor device, and the scan-in signal and the scan-designed logic circuit are input. Scan determining means for comparing and determining the scan out signal, memory determining means for comparing and determining the memory test signal and the output signal of the memory, and the scan determining means and the memory determining means by the test mode control signal. A test mode control means, and an output side of the memory determination means and the scan determination means An inspection apparatus of a semiconductor device to retrieve the memory determination signal and the scan determination signal to another Luo each.

According to this structure, it is possible to specify which side of the semiconductor device, which has at least the logic circuit and the memory, has the fault or the defect.

Further, the burn-in test apparatus of the present invention is a burn-in test apparatus for testing a semiconductor device, the burn-in test apparatus including a time measuring unit controlled by the output signal of the scan determining unit and the output signal of the memory determining unit. It is a test device.

According to such a configuration, it is possible to specify a defect occurrence time during the burn-in test, and predict a defect in the market or a defect transition.

[0012]

(First Embodiment) FIG. 1 is a block diagram of a semiconductor device inspection apparatus according to an embodiment of the present invention. A test mode control signal S101 is input from the outside of the semiconductor inspection device 100, and when the signal is in the burn-in test mode, a scan-in signal S102 is input to the scan design circuit 102 and a memory test signal S103 is input to the memory 102. Then, the scan determination signal S104 which is the test determination result of the scan design circuit and the memory determination signal S105 which is the test determination result of the memory 103.
And are output separately.

In the burn-in test mode, the input terminal of the semiconductor device having the semiconductor device inspection device for the burn-in test is controlled to a predetermined state, and the scan-in signal S102 is input to the scan design circuit 102. This is to set the memory test signal S103 to be input to the memory 103.

The scan-in signal S102 and the memory test signal S103 are the test mode control signal S101.
Based on the above, it may be automatically generated inside the semiconductor inspection apparatus 100.

A test mode control signal S10 is supplied to the test mode control means 101 from outside the semiconductor inspection apparatus 100.
1 is input to control the semiconductor inspection device 100. The scan design circuit 102 includes at least one scan chain (not shown). The scan-in signal S102 corresponding to this scan chain is input. It is input to the determination means 104.

A memory test signal S103 consisting of an n-bit input data signal, an m-bit address signal and a write enable signal is input to the input side of the memory 103, and an n-bit output data signal S112 is output from its output side.
Is output and is also input to the memory determination means 105.

Although not shown, even when the memory 103 has a read enable terminal and a chip enable terminal, the same operation can be performed by adding signals corresponding to these terminals to the memory test signal S103. You can

In consideration of the polarity of the scan chain, the scan determining means 104 receives both signals of the scan-in signal S102 and the scan-out signal S111 and has a parallel comparison configuration. The scan determination signal S104 is such that the logical value becomes "H" when the test mode control signal S101 matches and the logical value becomes "L" when the test mode control signal S101 does not match.
Is output.

In the scan judging means 104,
The determination of the logical value may be reversed. That is, the logical value may be set to “L” when the test mode control signal S101 and the scan signal S102 match, and “H” when they do not match.

The memory test signal S103 is applied to the memory 103 in the semiconductor inspection apparatus 100. Memory 10
An output data signal S112 is taken out from the output side of No. 3, and is supplied to the memory judging means 105. In addition to the output data signal S112, the memory test signal S103 is also applied to the memory determination means 105 so as to perform so-called parallel comparison. This is because the memory test signal S1
The polarity of the n-bit data input signal and the n-bit memory output signal corresponding to the address signal composing 03 is taken into consideration.

Further, the scan determination signal S104 is output so that the logic value becomes "H" when the test mode control signal S101 matches and the logic value becomes "L" when the test mode control signal S101 does not match.

The memory determining means 105 may be set in the reverse of the above logic. That is, the logical value may be set to "L" when the polarities of the two signals match, and the logical value may be set to "H" when they do not match.

Further, in the present description, the configuration provided with the combination of the scan design circuit 102 and the scan determination means 104 and the combination of the memory 103 and the memory determination means 105 is shown, but any one of these combinations may be used. Good.

(Second Embodiment) FIG. 2 shows a main part of the scan determination means 104 shown in FIG. Scan determination means 1
04 is a test mode signal S110 and a scan-in signal S
102 and the scan-out signal S111 are input, and the parallel comparison is performed in consideration of the polarity of the scan chain. Here, when the test mode signal 110 and the scan-in signal S102 and the test mode signal 110 and the scan-out signal S111 coincide with each other, a logical value "H",
When they do not match, the scan determination signal S104 is output so that the logical value becomes “L”.

The comparison means 201 is a scan design circuit 102.
N stages are prepared according to the number of scan chains. The scan-in signal S102 and the scan-out signal S111 are input to the comparing means 201, and these two signals are compared by each comparing means. If both signals match, "H"
The logical value of “L” is output for each scan chain when the values do not match.

The comparison means 201 may reverse the setting of the logical value of the comparison result. That is, the logical value “L” may be output when the values match, and the logical value “H” may be output when the values do not match.

The judging means 202 includes n comparing means 20.
When the logical value of all outputs is “H”, “H” is output as the scan determination signal S104, and when the logical value is “L”, “L” is output.

The determination means 202 may be set so that "L" is output when all outputs are "H" and "H" is output when all the logical values are "L".

(Embodiment 3) FIG. 3 shows a burn-in test apparatus according to an embodiment of the present invention. The burn-in test apparatus 300 has a function of determining the quality of the semiconductor device used in the burn-in test. The test pattern generating means 301 generates a test pattern for inspecting the semiconductor device under test 302. Test pattern generating means 3
01, the test mode control signal S101, the scan-in signal S102, and the memory test signal S103 are given to perform the burn-in test of the semiconductor device under test 302, and the pass / fail judgment of the semiconductor device under test 302 is performed. The failure occurrence part of the is identified and the defect occurrence time is displayed.

The test pattern generating means 301 generates a test pattern set in advance for carrying out a burn-in test of the semiconductor device under test 302. The semiconductor device under test 302 includes the semiconductor inspection device 100, receives the test mode control signal S101, the scan-in signal S102, and the memory test signal S103 from the test pattern generation device under preset voltage conditions, and outputs the scan determination signal. S104 and the memory determination signal S10
5 is output.

The test pattern generating means for the scan-in signal S102 and the memory test signal S103 may be integrated with the semiconductor device under test 302.

The scan determination storage means 303 electrically or physically stores the logical state of the scan determination signal S104. The memory determination storage unit 304 electrically or physically stores the logical state of the memory determination signal S105.

The time measuring means 305 inputs the scan determination signal S104 and the memory determination signal S105, measures the time at the start of the burn-in test, and outputs either the scan determination signal S104 or the memory determination signal S105 during the burn-in test. When the logical value becomes "L", the time measurement is stopped.

In the time measuring means 305,
When the logical value of either the scan determination signal S104 or the memory determination signal S105 becomes "L", the time measurement can be stopped.

[0035]

EFFECTS OF THE INVENTION It is possible to judge pass / fail of a semiconductor device under test during a burn-in test, streamline the evaluation / analysis process, and clarify the defect occurrence time during the burn-in test. Therefore, market defect prediction and burn-in time estimation It is possible to appropriately analyze the failure mode. Further, it is possible to separate the defective design portion from the scan design circuit or the memory, and it becomes easy to identify the defective location.

[Brief description of drawings]

FIG. 1 is a block diagram of a semiconductor device inspection apparatus according to a first embodiment of the present invention.

FIG. 2 is a block diagram of scan determination means according to a second embodiment of the present invention.

FIG. 3 is a block diagram of a burn-in test apparatus according to a third embodiment of the present invention.

[Explanation of symbols]

100 semiconductor inspection equipment 101 Test mode control means 102 scan design circuit 103 memory 104 scan determination means 105 memory determination means S101 Test mode control signal S102 scan-in signal S103 Memory test signal S104 Scan determination signal S105 Memory judgment signal S110 Test mode signal S111 Scan out signal S112 Output data signal 201 n comparison means 202 determination means 300 Burn-in test equipment 301 Test pattern generating means 302 Semiconductor device under test 303 scan determination storage means 304 memory determination storage means 305 time measuring means

Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) G01R 31/28 HP G F term (reference) 2G003 AA08 AC01 AD07 AF02 AH05 2G132 AA01 AA08 AB03 AC14 AE06 AE14 AE16 AG01 AK14 AK15 AK23 AL11 AL12 4M106 AA01 BA01 BA14 CA27 5L106 DD08 DD24 DD25 DD35 EE00

Claims (4)

[Claims] 1. A semiconductor device inspection apparatus comprising at least a scan-designed logic circuit and a memory, comprising:
A scan-in signal applied to the scan-designed logic circuit, and a memory test signal applied to the memory,
Input an external test mode control signal to the semiconductor device,
A scan determination unit that determines and compares the scan-in signal and a scan-out signal of the scan-designed logic circuit, a memory determination unit that determines and compares the memory test signal and the output signal of the memory, and the test mode control signal. A semiconductor, comprising: the scan determination means and a test mode control means for controlling the memory determination means, wherein a memory determination signal and a scan determination signal are respectively taken out from the output side of the memory determination means and the scan determination means. Equipment inspection equipment. 2. The scan determining means according to claim 1, wherein a logical value is “H” or “L” depending on a plurality of comparing means for comparing the scan-in signal and the scan-out signal and an output signal of the comparing means. The memory determining means includes a plurality of comparing means for comparing the memory test signal with the output signal of the memory, and the logical value is “H” or “depending on the output signal of the comparing means. An inspection apparatus for a semiconductor device, comprising: a determination unit that outputs one of L ″. 3. A burn-in test apparatus for testing the semiconductor device according to claim 1, further comprising time measuring means controlled by an output signal of the scan determining means and an output signal of the memory determining means. Burn-in test equipment. 4. The burn-in test apparatus according to claim 3, comprising scan determination storage means for storing the output signal of the scan determination means, and memory determination storage means for storing the output signal of the memory determination means. Burn-in test equipment.