JP2003216129A - Video display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a video display device capable of evading defects such as runaway of the video display device, lowering of quality and excess omission of information even when vertical synchronization signal frequencies are fluctuated. <P>SOLUTION: The video display device is constituted so that the number of lines are detected, that operations for automatically varying a starting position, an ending position of enable pulses as control pulses of an image display device are performed by detection results of the number of lines and an operating point of control is further set. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention prevents the runaway of a display element and prevents the display quality even when the vertical synchronizing signal cycle of a signal input during special reproduction of a VTR becomes irregular. The present invention relates to a video display device for digital signal processing, which suppresses the deterioration of the video signal to a minimum.

[0002]

2. Description of the Related Art FIG. 6 is a block diagram showing an image display device capable of displaying an image on the display device without trouble even when the vertical synchronizing frequency changes during special reproduction of a VTR.
(See Japanese Laid-Open Patent Publication No. 10-136290) As shown in FIG. 6, as a first decoder 101, a second decoder 104, a first vertical counter 102, a second vertical counter 105, a determination unit and a reset unit. The vertical synchronization (V synchronization) coincidence determination block 103, various video signal processing units 100, and a liquid crystal panel 106 which is a display device. Although not shown, the first and second vertical counters 102 and 105 count pulses that are synchronized with the horizontal synchronizing signal and have a frequency twice that of the horizontal synchronizing signal, and count their count values. It outputs to the first and second decoders 101 and 104, respectively. Further, the first and second vertical counters 102 and 105 are each reset by a reset signal output from the V sync coincidence determination block 103.

The first decoder 101 generates operation pulses for various video signal processing units 100 based on the counter value of the first vertical counter 102. Second decoder 104
Is based on the counter value of the second vertical counter 105,
A pulse for controlling the liquid crystal panel 106 is generated.

The V sync coincidence judgment block 103 judges whether or not the vertical sync signal from the outside and the internal V sync signal 110 from the first decoder 101 are input and the input timings of the respective signals match. To do. When the determination result is “match”, a reset signal is output to the first and second vertical counters 102 and 105. When the determination result is “mismatch”, a reset signal is output to each of the first and second vertical counters 102 and 105 by the input of the V sync signal from the outside, and the first vertical counter is input by the input of the internal V sync signal 110. The reset signal is output only to 102.

By virtue of the configuration provided with a plurality of counters having different reset conditions as described above and the control thereof, even if the vertical synchronizing frequency fluctuates during VTR special reproduction, an image can be displayed on the display device without any trouble. I can.

[0006]

However, in the above configuration, although it is possible to change the end position of the counter, the position of the image actually displayed on the display device 106 cannot be controlled and is unnecessary. It is conceivable that this will lead to the loss of important information. In addition, the display position becomes unstable because it operates even with a slight change in the input vertical synchronizing signal.

In order to solve the above problems, the present invention uses an enable pulse indicating a video display period as a pulse for driving a display device, and makes it possible to change the end position even if the input vertical synchronizing signal frequency fluctuates. Thus, a video display device that eliminates display problems is provided. In addition, by providing variable start and end positions of the enable pulse, we provide a video display device that stabilizes the center position of image display. On the other hand, a video display device that does not cause a malfunction is provided.

[0008]

In order to solve the above problems, the present invention compares the number of lines of an input signal detected by a line number detection circuit with an enable pulse end position set from the outside and When the number of lines of the input signal is smaller than the set end position, the setting of the end position is automatically changed to avoid a malfunction such as a runaway of the display device.

Further, in addition to the above-mentioned structure, the present invention is characterized in that the start position of the enable is also controlled so that the video display position can always be set to the optimum.

Furthermore, the present invention is characterized in that by setting an operating point for varying the start position and the end position, it is possible to avoid the occurrence of malfunction due to a minute fluctuation of the vertical synchronizing signal frequency.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention provides a video signal processing means for performing various video signal processing which operates by a clock synchronized with a video signal input from the outside, and a horizontal sync signal and a vertical sync signal from the video signal. A sync separation means for separation,
Clock generating means for generating a clock synchronized with the video signal from the horizontal synchronizing signal, clock counting means for counting clocks operating with the clock generated by the clock generating means, and counting clocks generated by the clock counting means Then, the horizontal pulse count means reset by the vertical sync signal output from the sync separation circuit and the free-run clock output from the free-run clock generation means are input to output the horizontal sync signal output from the sync separation circuit. The number of lines detecting means for counting and resetting by the vertical synchronizing signal, the comparing means for comparing the result of detecting the number of lines with the set vertical enable pulse end position, and the vertical enable according to the comparison result from the comparing means. The calculation means for calculating the pulse end position, and Outputs a vertical enable pulse set by selection means for selecting a value calculated from the result of the comparator or a set end position, and a vertical enable end position and a vertical enable start position which are outputs of the selection means. Second decoding means for outputting and a first horizontal enable pulse output for setting a start position and an end position
Decoding means, the first decoding means and the second
And a dot matrix display unit driven by a control signal output from the video signal processing unit and a video signal output from the video signal processing unit. Is.

With this configuration, even if the vertical synchronizing frequency of the input signal fluctuates during VTR special reproduction or the like, the pulse for driving the display element can be stably supplied, and malfunctions such as runaway can be avoided. .

The present invention is also directed to a video signal processing means for performing various video signal processings operated by a clock synchronized with a video signal input from the outside, and a synchronization for separating a horizontal synchronization signal and a vertical synchronization signal from the video signal. Separation means, clock generation means for generating a clock synchronized with the video signal from the horizontal synchronizing signal, clock counting means for counting clocks operating with the clock generated by the clock generation means, and clock generation means for the clock counting means The horizontal pulse counting means for counting the clocks and resetting by the vertical synchronizing signal output from the sync separation circuit, and the free-run clock output from the free-run clock generation means are input and output from the sync-separation circuit. The horizontal sync signal is counted and reset by the vertical sync signal. Line number detecting means, comparing means for comparing the line number detecting result with the set vertical enable pulse end position, and first calculating means for calculating the vertical enable pulse end position based on the comparison result of the comparing means. And a second calculation means for calculating the vertical enable start position set from the comparison result, and a value calculated by the first calculation means or the set end position from the comparison result of the comparison means. First selecting means, second selecting means for selecting either the value calculated by the second calculating means or the set start position, and the vertical enable which is the output of the first selecting means. Second decoding means for outputting a vertical enable pulse set by an end position and a vertical enable start position of the output of the second selecting means, and a start position and an end position are provided. A video signal output from the video signal processing means, a first decoding means for outputting a horizontal enable pulse to be output, a logical operation means for performing a logical operation on outputs of the first decoding means and the second decoding means, and a video signal processing means. The present invention relates to an image display device including a dot matrix image display unit driven by a signal and a control pulse output from the logical operation unit.

With this configuration, even if the vertical synchronizing frequency of the input signal fluctuates during VTR special reproduction or the like, the pulse for driving the display element can be stably supplied, and malfunctions such as runaway can be avoided. By adding control to the start position and end position of the pulse that controls the display means, it also has the effect of avoiding deterioration of quality.

Further, the present invention is a video signal processing means for performing various video signal processings operated by a clock synchronized with a video signal input from the outside, and a synchronization for separating a horizontal synchronization signal and a vertical synchronization signal from the video signal. Separation means, clock generation means for generating a clock synchronized with the video signal from the horizontal synchronizing signal, clock counting means for counting clocks operating with the clock generated by the clock generation means, and clock generation means for the clock counting means The horizontal pulse counting means for counting the clocks and resetting by the vertical synchronizing signal output from the sync separation circuit, and the free-run clock output from the free-run clock generation means are input and output from the sync-separation circuit. The horizontal sync signal is counted and reset by the vertical sync signal. Number detecting means for comparing the number of lines to be detected, a first comparing means for comparing the result of detecting the number of lines with the set vertical enable pulse end position, and a first comparing means for calculating the vertical enable pulse end position. Second calculating means for calculating the vertical enable start position set based on the comparison result, second operating means for comparing the set operating point with the line number detection result, and The third calculation means for deciding whether to select the output of the first comparison means according to the detection result of the comparison means, and the value calculated by the first calculation means from the output of the third selection means or First selection means for selecting the set end position, second selection means for selecting either the value calculated by the second calculation means or the set start position, and the first selection At the output of the means Second enable means for outputting a vertical enable pulse set at a vertical enable end position and a vertical enable start position of the output of the second selecting means, and a horizontal enable pulse output for setting a start position and an end position. A first decoding means for performing the above, a logical operation means for performing a logical operation of the outputs of the first decoding means and the second decoding means, and a video signal output from the video signal processing means and the logical operation means. The present invention relates to an image display device provided with a dot matrix display means driven by a control pulse output from the.

With such a configuration, even if the vertical synchronizing frequency of the input signal fluctuates during VTR special reproduction or the like, the pulse for driving the display element can be stably supplied, and a malfunction such as runaway can be avoided. Furthermore, by adding control to the start position and end position of the pulse that controls the display means, it also has the effect of avoiding deterioration of quality.

Further, since the operating point for controlling the pulse start position and the end position can be set, it is possible to add an unnecessary control to a minute frequency change of the input signal without adding unnecessary control.
It also has the function of avoiding malfunctions.

An example of the embodiment will be described below with reference to the drawings.

(Embodiment 1) FIG. 1 is a block diagram of a video display device showing a first embodiment of the present invention. An NTSC composite signal, for example, is input from the video input signal input terminal 1. The input video signal is branched and input to the video signal processing circuit 10 and the sync separation circuit 11. In the video signal processing circuit 10, for example, YC separation, based on a clock generated in a PLL circuit 13 described later,
Various processes such as color demodulation, matrix conversion, image quality correction, and IP conversion are performed.

On the other hand, the sync separation circuit 11 operates to separate the horizontal sync signal (HD) and the vertical sync signal (VD). The PLL circuit 13 generates a clock for operating the entire system on the basis of the horizontal sync signal separated by the sync separation circuit 11.

The free-run clock generating section 12 is made of, for example, a crystal and generates a free-run clock used for detecting the number of lines. The line number detection circuit 14 counts the number of lines by hitting the horizontal synchronization signal from the synchronization separation circuit 11 with the clock generated by the free-run clock generation unit 12. The count value is reset by the vertical sync signal from the sync separation circuit 11 as well.

The clock (CLK) counter 15 has a PL
In response to the clock output from the L circuit 13, the number of horizontal dots corresponding to the number of horizontal dots of the liquid crystal panel 23 of the dot matrix display system is counted, and the input horizontal synchronizing signal and a pulse having a moving frequency are generated.

The horizontal counter 16 is the clock counter 1
The pulse having the same frequency as the horizontal synchronizing signal of the input video signal generated in 5 is counted. Similar to the clock counter 15, the count number corresponds to the number of horizontal dots on the liquid crystal panel 23. However, the count is based on the number of horizontal lines of the liquid crystal panel 23, and is reset by the vertical sync signal output from the sync separation circuit 11.

The first decoder 19 receives the count value of the clock counter 15 and the signals indicating the horizontal enable start position and the end position which are set from the outside, and the liquid crystal panel 23.
A horizontal enable signal indicating a horizontal display area to be displayed is generated.

The comparator 17 detects how much the number of lines of the video input signal detected by the line number detection circuit 14 decreases with respect to the vertical enable end position which is also set from the outside. Further, the reduced number is output to the calculator 18.

The arithmetic unit 18 performs an arithmetic operation for subtracting the line number reduction number of the input signal with respect to the set vertical enable (EMB) end position detected by the comparator 17, from the end position setting. .

The selector 21 is controlled by the signal from the comparator 17, and controls switching between the signal indicating the vertical enable end position set value from the outside and the signal indicating the calculated value from the calculator 18. The number of lines detection circuit 14 in the comparator 17
If the number of lines of the video input signal detected in step 3 is smaller than the vertical enable end position that is also set from the outside, that is, the number of lines of the input signal is smaller than the number of horizontal lines counted by the horizontal counter 16. If so, select the calculator output, and if the numbers are the same, select the external setting end position.

The second decoder 20 generates a vertical enable signal indicating a vertical display area to be displayed on the liquid crystal panel 23 from the signal selected by the selector 21 and the vertical enable start position externally set.

The logic gate 22 includes a first decoder 19,
The horizontal enable signal and the vertical enable signal output from the second decoder 20 are ANDed to generate an enable pulse.

The liquid crystal panel 23 receives a video signal (R / G / B) from the video signal processing circuit 10 and an enable signal indicating a video display period to display a video.

Next, FIG. 2 is a timing chart of the image display device according to the present embodiment. The operation will be described with reference to the contents in FIG.

"Vertical sync (VD) normal time" means a vertical sync signal output when the sync separation circuit 11 sync-separates an input composite signal. The horizontal counter value indicates the value actually counted by the horizontal counter 16, and in the figure, counting is performed between 0 and 524 assuming NTSC input.

The start position set value and the end position set value set a vertical enable period indicating a vertical image display period, and are arbitrarily set from the outside. For example, the start position is "40", the end position is "520", and 480 lines are the video display area.

The vertical enable is output from the setting of the horizontal counter value and the start position and end position. It is "H" when the counter value and the start position match, and "L" when the counter value and the end position match.

"During vertical sync (VD) fast-forward reproduction" means
The VTR special reproduction, particularly the vertical synchronization of the input signal during fast-forward reproduction is separated. As shown in the figure, the frequency tends to be higher than in the standard state. Horizontal counter 16
Is reset by the separated vertical synchronizing signal, so it is cleared before the count value reaches the set value at the end position. The vertical enable signal is not output during fast forward playback. This is the next waveform.

In order to avoid the above-mentioned symptom, the arithmetic circuit subtracts the reduced number of lines from the set value to obtain a new set value.

(Embodiment 2) FIG. 3 is a block diagram of a video display device showing a second embodiment of the present invention. An NTSC composite signal, for example, is input from the video input signal input terminal. The input video signal is branched and input to the video signal processing circuit 30 and the sync separation circuit 31.

In the video signal processing circuit 30, a PL which will be described later is used.
Based on the clock generated in the L circuit 33, for example, YC
Various processes such as separation, color demodulation, matrix conversion, image quality correction, and IP conversion are performed. On the other hand, in the sync separation circuit 31,
An operation for separating the horizontal synchronizing signal (HD) and the vertical synchronizing signal (VD) is performed. The PLL circuit 33 generates a clock for operating the entire system on the basis of the horizontal sync signal separated by the sync separation circuit 31.

The free-run clock generating section 32 is made of, for example, crystal, and generates a free-run clock used for detecting the number of lines. The line number detection circuit 34 counts the number of lines by hitting the horizontal synchronization signal from the synchronization separation circuit 31 with the clock generated by the free-run clock generation unit 32. The count value is also designed to be reset by the vertical sync signal from the sync separation circuit 31.

The clock counter 35 receives the clock output from the PLL circuit 33 and is a dot matrix display type device, which is the liquid crystal panel 45 in the present invention.
The number of horizontal dots corresponding to the number of horizontal dots is counted, and a pulse of the input horizontal synchronizing signal and a moving frequency is generated. The horizontal counter 36 counts pulses having the same frequency as the horizontal synchronizing signal of the input video signal generated by the clock counter 35. The count number is the clock counter 35.
Similarly, the number corresponds to the liquid crystal panel 45. However, the count is based on the number of horizontal lines on the liquid crystal panel 45,
It is reset by the vertical sync signal output from the sync separation circuit 31. The first decoder 40 generates a horizontal enable signal indicating a horizontal display area to be displayed on the liquid crystal panel 45 from the count value of the clock counter 35 and the horizontal enable start position and end position set from outside.

The comparator 37 detects how much the number of lines of the video signal input from the outside, which is detected by the line number detecting section 34, decreases with respect to the vertical enable end position which is also set from the outside. There is. Further, the reduced number is passed to the arithmetic units 38 and 39.

The computing unit 38 performs a computation for subtracting the line number reduction number of the input signal with respect to the set vertical enable end position detected by the comparator 37 from the end position setting. In 39, a calculation is performed to add the number of line number reductions of the input signal with respect to the set vertical enable start position detected by the comparator 37 from the start position setting.

The selector 42 is controlled by the comparator 37 and controls to switch the vertical enable end position set value from the outside and the calculated value from the calculator 38. When the number of lines of the input signal is smaller than the number of horizontal lines counted by the horizontal counter 36, the arithmetic unit output is selected, and when the number is the same, the end position of the external setting is directly selected.

The selector 43 is controlled by the comparator 37 and controls to switch the vertical enable start position set value from the outside and the calculated value from the calculator 39. When the number of lines of the input signal is smaller than the number of horizontal lines counted by the horizontal counter 36, the arithmetic unit output is selected, and when the number is the same, the end position of the external setting is directly selected.

The second decoder 41 generates a vertical enable signal indicating a vertical display area to be displayed on the liquid crystal panel 45 from the value selected by the selector 42 and the value selected by the selector 43. The logic gate 44 ANDs the horizontal enable signal and the vertical enable signal output from the first decoder 40 and the second decoder 41 to generate an enable pulse. The liquid crystal panel 45 receives a video signal (R / G / B) from the video signal processing circuit 30 and an enable signal indicating a video display period and displays a video.

FIG. 4 is a timing chart of the video display device of this embodiment. The operation will be described with reference to the contents in FIG.

"Vertical sync (VD) normal time" indicates the vertical sync signal output when the sync separation circuit 31 sync-separates the input composite signal. The horizontal counter value indicates the value actually counted by the horizontal counter 36, and in the figure, counting is performed between 0 and 524 assuming NTSC input. The start position set value and the end position set value set a vertical enable period indicating a vertical video display period, and are arbitrarily set from the outside. For example, the start position is "40", the end position is "520", and 480 lines are the video display area. The vertical enable in the next stage is output from the setting of the horizontal counter value and the start position and end position. It is "H" when the counter value and the start position match, and "L" when the counter value and the end position match.

"Vertical synchronization (VD) fast-forward playback" means
The VTR special reproduction, particularly the vertical synchronization of the input signal during fast-forward reproduction is separated. As shown in the figure, the frequency tends to be higher than in the standard state. Since the horizontal counter is reset by the separated vertical synchronizing signal, it is cleared before the count value reaches the set value at the end position. The vertical enable signal is not output during fast forward playback. This is the next waveform.

In order to avoid the above-mentioned symptom, the first arithmetic circuit 38 subtracts the reduced number of lines from the end position set value to obtain a new set value. Further, the second arithmetic circuit subtracts the reduced number of lines from the start position set value to obtain a new set value. The vertical enable pulse that is decoded and output from the two new setting values is described in the final stage.

(Embodiment 3) FIG. 5 is a block diagram of a video display device showing an embodiment of the present invention. An NTSC composite signal, for example, is input from the video input signal input terminal. The input video signal is branched and input to the video signal processing circuit 50 and the sync separation circuit 51. In the video signal processing circuit 50, for example, YC separation, color demodulation,
Various processes such as matrix conversion, image quality correction, and IP conversion are performed.

On the other hand, the sync separation circuit 51 operates to separate the horizontal sync signal (HD) and the vertical sync signal (VD). The PLL circuit 53 generates a clock for operating the entire system on the basis of the horizontal sync signal separated by the sync separation circuit 51.

The free-run clock generating section 52 uses, for example, a crystal, and generates a free-run clock used for detecting the number of lines. The line number detection circuit 54 counts the number of lines by hitting the horizontal sync signal from the sync separation circuit 51 with the clock generated by the free-run clock generator 52. The count value is also designed to be reset by the vertical sync signal from the sync separation circuit 51.

The clock counter 56 receives the clock output from the PLL circuit 53 and is a dot matrix display type device, that is, a liquid crystal panel 67 in the present invention.
The number of horizontal dots corresponding to the number of horizontal dots is counted, and a pulse of the input horizontal synchronizing signal and a moving frequency is generated.

The horizontal counter 57 is the clock counter 5
The pulse having the same frequency as the horizontal synchronizing signal of the input video signal generated in 6 is counted. Like the clock counter 56, the count number corresponds to the liquid crystal panel 67. However, the count is based on the number of horizontal lines of the liquid crystal panel 67, and is reset by the vertical sync signal output from the sync separation circuit 51. The first decoder 61 determines the liquid crystal panel 6 from the count value of the clock counter 56 and the horizontal enable start position and end position set externally.
A horizontal enable signal indicating a horizontal display area to be displayed at 7 is generated.

In the first comparator 58, the line number detecting section 5
It is detected how much the number of lines of the video signal input from the outside detected in step 4 has decreased with respect to the vertical enable end position which is also set from the outside. Further, the reduced number is passed to the first computing unit 59 and the second computing unit 60.

In the first computing unit 59, the number of line number reduction of the input signal with respect to the set vertical enable end position detected by the first comparator 58 is subtracted from the end position setting. The second calculator 60 adds the line number reduction number of the input signal with respect to the set vertical enable start position detected by the first comparator 58 from the start position setting. The calculation is done.

The first selector 64 is controlled by a third selector 63, which will be described later, and controls to switch the vertical enable end position set value from the outside and the calculated value from the first calculator 59. If the number of horizontal lines of the input signal is smaller than the number of horizontal lines counted by the horizontal counter 57, the output of the arithmetic unit is selected, and if the number is the same, the end position of the external setting is directly selected.

The second selector 65 is controlled by a third selector 63, which will be described later, and controls to switch the vertical enable start position set value from the outside and the calculated value from the second calculator 60. If the number of horizontal lines of the input signal is smaller than the number of horizontal lines counted by the horizontal counter 57, the output of the arithmetic unit is selected, and if the number is the same, the end position of the external setting is directly selected.

The third selector 63 has a line number detecting section 5
It is controlled by the value of the second comparator 55 that compares the number of lines detected in 4 with the operation start point set value set from the outside. When the detected number of lines is less than the set operating point, the "L" signal is output and the first selector 64 and the second
If the selector 65 selects the set value from the outside and the number of lines reaching the operating point is detected, "H"
It outputs a signal, and the first selector 64 and the second selector 6
5 operates to select the set values of the first computing unit 59 and the second computing unit 60, respectively.

The second decoder 62 includes the first selector 6
A vertical enable signal indicating a vertical display area to be displayed on the liquid crystal panel 67 is generated from the value selected by 4 and the value selected by the second selector 65. The logic gate 66 ANDs the horizontal enable signal and the vertical enable signal output from the first decoder 61 and the second decoder 62 to generate an enable pulse. The liquid crystal panel 67 displays the video signal (R / G) from the video signal processing circuit 50.
/ B) and an enable signal indicating a video display period are displayed.

In the present invention, the configuration described in this embodiment,
In addition to the operation, the operation start point can be set. According to the conventional technology and the technology up to claim 3, even if the number of lines fluctuates by several lines, the control pulse for driving the image display device fluctuates. When the display quality is a problem, the vertical display area of the screen becomes a problem. This problem can be avoided by setting whether or not to use the calculation result based on the second comparator 55 and the line number detection result.

[0062]

As described above, according to the above embodiment, the number of lines is detected, and from the detection result, the start position and the end position of the enable pulse which is the control pulse of the image display element are automatically changed, and the control is performed. By setting the operating point, V
Even when the frequency of the vertical synchronizing signal fluctuates during TR special reproduction, it is possible to provide a video display device capable of avoiding problems such as runaway of the display element, deterioration of quality, and excessive loss of information.

[Brief description of drawings]

FIG. 1 is a block diagram showing a video display device according to a first embodiment of the present invention.

FIG. 2 is a waveform diagram showing the operation of the device.

FIG. 3 is a block diagram showing a video display device according to a second embodiment of the present invention.

FIG. 4 is a waveform diagram showing the operation of the device.

FIG. 5 is a block diagram showing an image display device according to a third embodiment of the present invention.

FIG. 6 is a block diagram of a video display device showing an embodiment according to a conventional technique.

[Explanation of symbols] 10 Video signal processing circuit 11 Sync separation circuit 12 Free run clock generator 13 PLL circuit 14 Line number detector 15 clock counter 16 Horizontal counter 17 Comparator 18 arithmetic unit 19 First Decoder 20 second decoder 21 selector 22 gates 23 LCD panel module 30 Video processing device 31 Sync separation circuit 32 Free run clock generator 33 PLL circuit 34 Line number detector 35 clock counter 36 horizontal counter 37 Comparator 38 First computing unit 39 Second arithmetic unit 40 First Decoder 41 Second Decoder 42 first selector 43 Second selector 44 gates 45 LCD panel module 50 Video signal processing circuit 51 Synchronous separation circuit 52 Free-run clock generator 53 PLL circuit 54 Line number detector 55 First Comparator 56 clock counter 57 Horizontal counter 58 Second comparator 59 First computing unit 60 Second computing unit 61 First Decoder 62 second decoder 63 Third Selector 64 first selector 65 Second selector 66 gates 67 LCD panel module

   ─────────────────────────────────────────────────── ─── Continued front page    F-term (reference) 5C006 AA01 AA22 AF42 AF44 AF46                       AF50 AF51 AF52 AF53 AF61                       AF72 BB11 BF14 BF22 BF26                       FA18                 5C058 AA06 BA35 BB25                 5C080 AA06 AA10 BB05 CC03 DD01                       DD09 JJ02 JJ04 KK43

Claims (6)

[Claims] 1. A video display device for performing liquid crystal display, etc., comprising various video signal processing devices and synchronization signal processing devices,
A device for detecting the number of lines by a free-run clock is provided, and the detection result from the line number detection device is used to
It controls the end position of the control pulse supplied to the liquid crystal panel generated from the clock generated in the L circuit, and prevents the panel runaway from occurring in response to the frequency fluctuation of the input vertical synchronizing signal generated during the special reproduction of the VTR. Video display device to avoid. 2. A video signal processing means for performing various kinds of video signal processing operated by a clock synchronized with a video signal input from the outside, and a sync separation means for separating a horizontal sync signal and a vertical sync signal from the video signal. A clock generating means for generating a clock synchronized with the video signal from the horizontal synchronizing signal; a clock counting means for counting clocks operated by the clock generated by the clock generating means; and a clock generated by the clock counting means. Horizontal pulse counting means that counts and is reset by the vertical synchronizing signal output from the sync separation circuit, and a horizontal sync signal output from the sync separation circuit by inputting the free-run clock output from the free-run clock generating means The number of lines to be reset by the vertical sync signal. Output means, comparing means for comparing the result of detecting the number of lines with the set vertical enable pulse end position, and calculating means for calculating the vertical enable pulse end position based on the comparison result from the comparing means,
A vertical enable pulse set by a selection unit that selects a value calculated from the result of the comparator or a set end position, and a vertical enable start position that is an output of the selection unit and a vertical enable start position that is set. A second decoding means for outputting, a first decoding means for outputting a horizontal enable pulse whose start position and an end position are set, and a logical operation for the outputs of the first decoding means and the second decoding means. An image display device comprising: an arithmetic means; and a dot matrix display means driven by a video signal output from the video signal processing means and a control pulse output from the arithmetic means. 3. A video display device for performing liquid crystal display, comprising various video signal processing devices and synchronization signal processing devices,
A device for detecting the number of lines by a free-run clock is provided, and the detection result from the line number detection device is used to
The control pulse is generated from the clock generated in the L circuit and is supplied to the liquid crystal panel. The start position and the end position of the control pulse are controlled to prevent the runaway of the panel from the frequency fluctuation of the input vertical synchronizing signal generated during the special reproduction of the VTR. An image display device that can avoid the occurrence of the image and minimize the fluctuation of the image position. 4. A video signal processing means for performing various video signal processings operated by a clock synchronized with a video signal input from the outside, and a sync separation means for separating a horizontal sync signal and a vertical sync signal from the video signal. A clock generating means for generating a clock synchronized with the video signal from the horizontal synchronizing signal; a clock counting means for counting clocks operated by the clock generated by the clock generating means; and a clock generated by the clock counting means. Horizontal pulse counting means that counts and is reset by the vertical synchronizing signal output from the sync separation circuit, and a horizontal sync signal output from the sync separation circuit by inputting the free-run clock output from the free-run clock generating means The number of lines to be reset by the vertical sync signal. Output means, comparing means for comparing the result of detecting the number of lines with the set vertical enable pulse end position, first calculating means for calculating the vertical enable pulse end position based on the comparison result of the comparing means, and Second computing means for computing a vertical enable start position set from the comparison result, and first computing means for selecting the value computed by the first computing means or the set ending position from the comparison result of the comparison means. Selection means, second selection means for selecting either the value calculated by the second calculation means or the set start position, and the vertical enable end position which is the output of the first selection means. Second decoding means for outputting a vertical enable pulse set by the vertical enable start position of the output of the second selecting means, and a horizontal decoder for setting a start position and an end position. First decoding means for outputting a clock pulse, a logical operation means for performing a logical operation on the outputs of the first decoding means and the second decoding means, a video signal output from the video signal processing means, and the logic An image display device comprising: a dot matrix image display unit driven by a control pulse output from an arithmetic unit. 5. A video display device for performing liquid crystal display, comprising various video signal processing devices and synchronization signal processing devices,
A device for detecting the number of lines by a free-run clock is provided, and the detection result from the line number detection device is used to
The control pulse is generated from the clock generated in the L circuit and is supplied to the liquid crystal panel. The start position and the end position of the control pulse are controlled to prevent the runaway of the panel from the frequency fluctuation of the input vertical synchronizing signal generated during the special reproduction of the VTR. It is possible to avoid the occurrence and to minimize the fluctuation of the video position. Furthermore, if the frequency fluctuation of the input vertical synchronizing signal is minute, it is equipped with a switching device that can not activate the above control. A video display device that can minimize the so-called information loss by reducing the video display period for slight vertical frequency fluctuations. 6. A video signal processing means for performing various video signal processings operated by a clock synchronized with a video signal input from the outside, and a sync separation means for separating a horizontal sync signal and a vertical sync signal from the video signal. A clock generating means for generating a clock synchronized with the video signal from the horizontal synchronizing signal; a clock counting means for counting clocks operated by the clock generated by the clock generating means; and a clock generated by the clock counting means. Horizontal pulse counting means that counts and is reset by the vertical synchronizing signal output from the sync separation circuit, and a horizontal sync signal output from the sync separation circuit by inputting the free-run clock output from the free-run clock generating means The number of lines to be reset by the vertical sync signal. Output means, first comparing means for comparing the result of line number detection with the set vertical enable pulse end position, and first calculating means for calculating the vertical enable pulse end position based on the comparison result of the comparing means. A second calculating means for calculating a vertical enable start position set based on the comparison result, a second comparing means for comparing the set operating point and the line number detection result, and a second comparing means. From the output of the third selecting means for determining whether to select the output of the first comparing means and the output of the third selecting means, the value calculated or set by the first calculating means is set. First selection means for selecting an end position, second selection means for selecting either the value calculated by the second calculation means or the set start position, and the output of the first selection means Vertical enable Second decoding means for outputting a vertical enable pulse set by the end position and the vertical enable start position of the output of the second selecting means, and horizontal enable pulse output for setting the start position and the end position. First decoding means, logical operation means for performing logical operation of outputs of the first decoding means and the second decoding means, video signal output from the video signal processing means, and output from the logical operation means And a dot matrix display means driven by the control pulse.