JP2003203009A - Processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To set information about the operating mode of a synchronized dynamic memory from a processor LSI. <P>SOLUTION: This processor outputs an access address for obtaining access to the memory. The access address has a low address, a column address and a bank address in it. The processor includes a control circuit 608 for designating the position of the bank address of the access address. Thus, the information about the operating mode of the synchronized dynamic memory can be set from the processor LSI. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing system, and more particularly to a microprocessor LSI and a portion of a microprocessor peripheral circuit for controlling a memory.

[0002]

2. Description of the Related Art A dynamic memory is generally a DRAM (Dy
Namic Random Access Memory). The specifications of a typical dynamic memory LSI are described in "Hitachi IC Memory Data Book 3 (DRAM, DRAM Module, 445th to 464th pages"). Although it has an input terminal, the address given through the input terminal is multiplexed with the row / column (page 448).
For write access, it is necessary to give addresses to the dynamic memory LSI in the order of row and column (page 454),
At that time, the read access time from the confirmation of the external address is
It is 70 nanoseconds (1 nanosecond = 10 (-9) th second). Separately, by using the fast page mode (page 461), after the first row and column address transfer, the row address transfer can be omitted as long as the second and subsequent accesses are performed in the same row access. The read access time after the second and subsequent external address determination is suppressed to a small 20 nanoseconds.

Non-Patent Document 1 describes an example of a DRAM control function of a conventional microprocessor (hereinafter simply referred to as a processor). A page in which the processor LSI and the DRAM chips of two banks are directly connected is described on page 4.2.3 of the lecture material collection. Also, in Non-Patent Document 1, Section 4.
2.8 The timing diagram on page `` Check fast page cache
There is a description such as "-hit" (fast page cache hit), and it can be inferred to use the fast page mode of dynamic memory under some kind of hit condition inside the processor.
This operation can be performed, for example, by storing a row address when the dynamic memory is accessed last time. However, no mention is made of how the two banks of DRAM are used, and the relationship between the high-speed page cache hit and the two banks of DRAM.

[Non-Patent Document 1] "4th Hot Chips Lecture Collection,
Pages 4.2.1 to 4.2.12, August 1992 '' (Hot C
hips IV, pp. 4.2.1-4.2.12, Aug. 1992, held in Stan
ford Univ.)

It is assumed that a conventional processor LSI has a row / column and a multiplexed address for a dynamic memory among terminals of the processor. FIG. 2 shows an example of access made by the processor LSI. However, in Fig. 2, the horizontal direction is the time axis, 201 is the access request of the processor, 202 is the dynamic address pin A0-9 of the processor, 203 is the low address strobe (RAS-n) signal of the dynamic memory. , 204 are column address strobe (CAS-n) signals of the dynamic memory. Further, "-n" added to the end of the signal line indicates a negative signal. This access is, for example, block copy,
That is, when the contents of the memory of one area are copied to the memory of another area. In FIG. 2, the area starting at address A000 is copied to the area starting at address 7040. However, in this application, the address is displayed in hexadecimal. Reference numeral 205 is an explanatory diagram showing how a 32-bit physical address is used. Bits (30 to 31) of the physical address
1 to 29) are assigned to the column address of the dynamic memory, and bits (11 to 20) are assigned to the row address of the dynamic memory. Bit (i) indicates the i-th bit when the left end is bit 0. At that time, if you follow the operation in chronological order, it will be as follows. Operation 1: Read to address A000. Transfer the row / column address to the dynamic memory. The row address is 14 because it is the address bits (11 to 20). The column address is 0 because it is the address bit (21 to 29). Action 2: Lead to address A004. Since the row address is the same as the previous row address, the transfer to the dynamic memory is omitted. Transfer column address to dynamic memory. Action 3: Write to address 7040. Transfer the row / column address to the dynamic memory. Operation 4: Lead to address 7044. Since the row address is the same as the previous row address, the transfer to the dynamic memory is omitted. Transfer column address to dynamic memory. The following four accesses perform the same operation and will be omitted.

As shown in this example, in the prior art example, when the row address on the read (source) side and the write (destination) side are different in the block copy processing, the access source There is a problem that the high-speed mode that omits the row address of the dynamic memory cannot be used every time the destination is switched.

An object of the present invention is to solve the problem that the high speed mode in which the row address of the dynamic memory is omitted cannot be used.

Another object of the present invention is to enable use of a high speed mode in which a row address of a dynamic memory is omitted in a processor having no multiplexed address terminal for the dynamic memory, and at the same time, a logical quantity external to the processor LSI is used. It is to provide a signal line interface of a processor LSI for minimizing the above.

Another object of the present invention is to provide a signal line interface of a processor LSI for setting information on an operation mode of a synchronous dynamic memory from the processor LSI and minimizing a logic amount outside the processor LSI. It is in.

[0008]

A processor for outputting an access address for accessing a memory, comprising:
The access address has a row address, a column address and a bank address, and the processor is configured to have a control circuit for designating a position of the bank address in the access address.

[0009]

BEST MODE FOR CARRYING OUT THE INVENTION FIG. 3 shows an access pattern of an information processing apparatus using the present invention. 301, 114, 117, 116, and 305 correspond to 201-205 in FIG. 2, respectively, and description thereof will be omitted. As shown by 205, in this example, the least significant 2 bits of the 32-bit physical address (30 to 31) are the in-word address, the bits (21 to 29) are the column address of the dynamic memory, and the bit (20). Is assigned to the bank address of the dynamic memory, and bits (9 to 19) are assigned to the row address of the dynamic memory. Reference numeral 115 is a processor LSI terminal indicating a bank bit. Dynamic memory LS specified by bank bit in one access
Only I is accessed. In the dynamic memory, only one part divided by the bank bit is accessed in one access. Specific examples of the configuration of the memory will be described in detail in other embodiments. During the access period of addresses A000 and A004, the dynamic memory LSI corresponding to bank 0 is accessed. During the access period of addresses 7040 and 7044, the dynamic memory LSI corresponding to bank 1 is accessed, but the dynamic memory L corresponding to bank 0 is accessed.
SI is not accessed. After that, when the address A008 is read, the row address of the dynamic memory LSI corresponding to bank 0 is the same as that of the previous time, so the transfer of the row address can be omitted. Further, the dynamic memory LSI corresponding to bank 1 during that period is not accessed. When the address 7070 is read thereafter, the row address of the dynamic memory LSI corresponding to bank 1 is the same as that of the previous time, so the transfer of the row address can be omitted. Comparing Figure 3 and Figure 2, A0
Row address transfer when accessing address 08,7048 can be omitted. The access time in that case can be short as described above, and as a result, it is useful for improving the processing speed. If this block copy process continues,
As long as the source / destination continues to access the same row, the fast page mode is used and row address transfer can be omitted. The effects of the present invention for other purposes will be described through the following examples.

FIG. 1 shows an example of the processor of the information processing apparatus according to the embodiment of the present invention. 100 is a processor. Ten
Reference numerals 1 and 102 are row address registers (register = storage unit). 103 and 104 are bits indicating the validity of 101 and 102, respectively, and are called valid bits. 105 and 106 are selection circuits. 105 selects one of the outputs of 103 and 104 and transmits the selection result to the control circuit 108. 106 is 101
And outputs any one of the outputs 102 and 102 to output to the signal line 112. Reference numeral 107 denotes a coincidence comparator that compares the row address of the access request address 110 with one of the row addresses of the row address registers 101 and 102 selected by the selection circuit 106. Reference numeral 108 is a control circuit. 109 is a selection circuit. The processor 100 selects a row address or a column address part of the access request address 110 when an access is made to an external dynamic memory.
Address pin A for dynamic memory selected using 109
(0:10) Output to (114). The control circuit 108 includes a selection circuit 1
The output of the valid bit of 05 and the output signal 113 of the comparison of the row address of the match comparator 107 are input. Further, the bank bits of the address bus 110 are input to the control circuit 108. The control circuit 108 is BANK (115), RAS-n (117).
(-n indicates a negative polarity signal), CAS-n (116) outputs the signal value of three external terminals. 32-bit physical address is figure
Row addresses, column addresses, and bank addresses are assigned as described in 3. The flow of processing when the processor 100 issues an access request is as follows. First of all, an access request signal from a data processing unit (not shown because the relationship is thin) consisting of an instruction processing unit and an operand processing unit inside the processor is transmitted to the control circuit 108 via the signal line 111. Address bus PA at the same time
(0 to 31) The requested access address is transmitted via (110). The control circuit 108 uses the bank address (bit 20) of the request address to set the row address registers 101, 10
One of the two outputs is selected by the selection circuit 106. Also, one of the valid bits 103 and 104 is selected by the selection circuit 105 using the bank address. The row address selected by the selection circuit 106 is equal to the row part of the requested address,
A bit of 1 is called a hit. If it is a hit, the same row address as in the previous access will be accessed for the bank, and at that time, the dynamic memory is accessed in an operation mode in which transmission of the row address of the dynamic memory is omitted. If not a hit, the dynamic memory is first accessed in an operating mode that transfers both row and column addresses of the dynamic memory. Second, register the low part of the requested address on the side selected by the bank address of 101 and 102, and use the valid bit (103 or 104) on the same side.
Is rewritten to 1. The valid bits 103 and 104 have a value of 0 in the initial state after the power is turned on, and have a function of not accidentally hitting when the row address happens to coincide with the first access after the power is turned on.

FIG. 4 shows a system diagram including the processor 100. 401 and 402 are synchronous dynamic memory LSIs.
Processor LSI 100 control signal A (0:10) (114), BANK (1
15), RAS-n (117) and CAS-n (116) are connected to 401 and 402. However, the internal memory of the synchronous dynamic memory LSI 401 is divided into two banks, 403 and 404, and when the memory 404 is BANK (115) = 0, the memory 403 is BAN.
Accessed when K (115) = 1. However, 0 of the signal line means potential low, and 1 of the signal line means potential high. When the BANK (115) signal is 0, a logical value of 1 is generated at the output of the inverter (logic inverter) 407, and it is transmitted to the bank 0 memory control circuit 406. This translates into an instruction to access bank 0 memory. BANK (115) signal is 1
At the time of, the logical value 1 is transmitted to the bank 0 memory control circuit 405. This translates into an instruction to access bank 1 memory. In addition, the dynamic memory has the following terminals. i / O 0-7 (409, 410) are 8-bit data input / output signals. WE-n (411, 412) is a write instruction signal having a negative polarity and has a logical value of 0 when writing. CLK (41
3, 414) is a clock input terminal. CKE (415, 416) is a clock enable signal and controls whether or not the clock is transmitted internally. DQM (407) is an access mask signal, and data input / output signal i /
As an output enable of O0-7, it functions as a write enable signal in clock units at the time of write access.
Further, the dynamic memories 401 and 402 have some operation modes in the case of synchronous operation. They are RAS delay (the number of clock cycles from RAS to data access), CAS delay (the number of clock cycles from CAS to data access), and burst length (the cycle until the address counts up once and returns to the original). is there. These mode information are RAS-n (117), CAS-n (116), WE-n (41
It is written via address terminals A0-10 when all three of 1) are potential L.

FIG. 5 shows a dynamic memory and its control circuit in another system diagram including the processor 100. 50
Each of 1 and 503 is an inverter (logic inverter). Each of 502 is a 2-input AND circuit, and the output value becomes 1 only when both of the input values are 1. 504 is bank 0
505 is a dynamic memory of bank 1, and 505 is a dynamic memory of bank 1. 506 and 507 are negative row address strobe and column address strobe signals of the dynamic memory 504 of bank 0, respectively. 508, 509
Are negative row address strobe and column address strobe signals of the dynamic memory 505 of bank 1, respectively. RAS-n (117) when signal BANK (115) is 0,
Negative pulse appearing on CAS-n (116) (303, 304 in Figure 3)
50) to 506 and 507, respectively.
8, 509 can not be told. As a result, the dynamic memory 504 of bank 0 is accessed. When BANK (115) is 1, the negative pulse appearing on RAS-n (117) and CAS-n (116) is transmitted to 508 and 509, but not to 506 and 507, respectively. As a result, the dynamic memory 505 of bank 1 is accessed.

An example of another processor using the present invention is shown in FIG.
Shown in. 600 is a processor. 601-608, 610, 611
Since -613 is made of the same as 101-108, 110, 111-113 in FIG. 1, description thereof will be omitted. The processor 600 does not have a row / column multiplexed address terminal for a dynamic memory, but has a 32-bit address terminal A (0:31) (614) containing a row address and a column address. 6
Reference numeral 15 is a 2-input selector, which selects either the access request address 610 or the register 617 to address terminal A (0:31).
Output to (614). 616 is an output buffer of the LSI, and its input and output logical values are the same. 2-input selector 615
When selecting the access request address 610, the operation is similar to that described with reference to FIG. The case of selecting the access request address 610 will be described below. Processor 600
When a request for access is issued, the flow of processing is as follows. First, an access request signal is transmitted from the processing section including the instruction processing section and the operand processing section inside the processor to the control circuit 608 via the signal line 611. At the same time, the access address is transmitted via the address bus PA (0:31) (610). The control logic 608 selects one of the outputs of the row address registers 601 and 602 using the bank address of the request address. Further, one of the valid bits 603 and 604 is selected by the selection circuit 605 using the bank address. If it is a hit, the control circuit 608 outputs the output terminal SAR (60
Set 9) to 1. SAR is an output signal that means access to the same row region. The definition of hit is the same as the definition in the explanation of FIG. If not hit, control circuit 60
8 sets SAR (609) to 0. Information is registered in the 601, 602, 603, and 604 similarly to the example of the processor 100. The external circuit of the processor LSI 600 can use the high-speed operation mode in which it is possible to detect that the SAR (609) becomes 1 and omit the transmission of the row address of the dynamic memory.

Unlike the processor LSI100, the processor LSI600 does not have fixed bank bit positions. FIG. 7 shows a block diagram of a portion related to the bank bit selection method.
In FIG. 7, 601, 602, 606, 608, 612 have already been described, so a new description will be omitted. The 2-input selector 606 of FIG. 7 is controlled by the bank bit control signal 703. 702 is a 21-input selector, and input signals 704, 705,
, 706, 707 is output to the bank bit control signal 703 according to the control signal 701 from the control logic 608. Note that 704, 705, 706, and 707 are individual address signals of the request address PA (0:31) of the address bus 610 in FIG. The processor 600 can arbitrarily set the control signal 701 by using a specific instruction. By summing up the above, it becomes possible to use any bit between bit positions 0 and 20 of the request address as the bank address. Then, the 2-input selector 615 of FIG.
The case of selecting 17 will be described. The register 617 stores the operation mode of the synchronous dynamic memory (RAS delay,
(CAS delay, burst length) information is set. The 2-input selector 615 selects the register 617 by executing a specific instruction in the processor 600, and the address terminal A (0:31)
Output to (614). By combining with an appropriate external circuit, the operation mode setting operation of the synchronous dynamic memory connected to the outside of the processor 600 is achieved.

FIG. 8 shows a block diagram of an information processing apparatus using the processor LSI 600. 8 is roughly divided into a processor LSI6
00, an external circuit control LSI 801, and a main memory LSI 402 using a synchronous dynamic memory. First the processor
The transmission path of the address signal 614 of the LSI 600 will be described. The address signal 614 is input to the external circuit control LSI 801, and first stored in the address register 802. 805
Is a row address of the main memory LSI 402, and 806 is a main memory LSI 402 column address. 2-input selector 803
805 or 806 is selected by the system address bus
Sent to 811. The address of the system address bus 811 is further transferred to the address terminal of the main memory LSI 402. The upper address 807 of the addresses in the address register 802 is decoded by the address decoder 814, and the result of the decoding is transmitted to the chip select terminal 813 of the main memory LSI 402. 812 is a 32-bit system data bus,
Data exchange between the processor LSI 600 and the main memory LSI 402 is performed via 812. Since the data terminal of the LSI 402 has an 8-bit width, this device includes at least four LSIs 402 in order to transfer and receive 32-bit data. External circuit control LSI801
Within is the access request management logic 804. Reference numeral 804 is for managing a state regarding access. Processor LSI600
From the access request management logic 804 to the access request signal 808
Then, the same address designating signal 609 and the dynamic memory operation mode setting request signal 815 are transmitted. The operation of the access request management logic 804 when the signal 815 has the logical value 0 is as follows. First, when the access request is in the signal 808 and the same address designating signal 609 has a logical value of 0, RAS-n (809)
To the main memory LSI 402 and simultaneously
Apply 5 to system address bus 811. Then CAS-n (80
9) is issued to the main memory LSI 402, and at the same time, the column address 805 is given to the system address bus 811. Secondly, when the access request is in the signal 808 and the same address designating signal has the logical value 1, the issuing of the RAS-n (809) and the row address 805 is omitted as compared with the first case. When the specific instruction described above (the instruction described in the description of the register 617) is executed by the processor 600, the operation mode setting request signal 815 becomes the logical value 1. When the signal 815 has a logical value of 0, the access request management logic 804 sets RAS-n (809), CAS-n (810), and WE-n (816) to the potential L. At the same time, the value of the operation mode register 617 is transmitted to the main memory LSI 402 via the system address bus 811. In this way, the setting processing of the operation mode of the main memory LSI 402 is achieved. This processing is performed at power-on initial processing and at reset. Since the processor 600 has the operation mode setting request signal 815, the main memory LSI 402
The logic conventionally required for generating the signal for generating the operation mode setting process start signal, such as the address decode logic, is unnecessary.

The present invention is not limited to the above specific embodiments, and various modifications can be made within the scope of the technical idea thereof. For example, the number of row address registers and the number of banks of dynamic memory are two, but the number of registers and the number of banks can be increased to 4, 8, .... Also, the row address register and the match comparator do not necessarily have to exist in the processor LSI, and the processor L
It is also possible to perform processing equivalent to that of the present embodiment outside the SI, for example, with the external circuit control LSI 801.

According to the embodiment of the present invention, in the case of a block copy process, the row address transfer is omitted for each of the source / destination so that the transfer of the row address can be omitted. Can be used. Further, in the embodiment of the present invention, the row address hit information 609 is stored in the processor LSI.
A high-speed operation mode of a dynamic memory in which a processor having an address terminal that is not multiplexed for the dynamic memory and having the external logic amount of the processor LSI minimized to omit the transfer of the row address by providing as an output signal of 600 It enables the use of. Further, in the embodiment of the present invention, the processor 600 is provided with the operation mode setting request signal 815, so that the logic conventionally required to generate a signal for generating the setting processing start signal of the operation mode of the main memory LSI 402, for example, Address decode logic may be unnecessary.

[0018]

According to the present invention, information on the operation mode of the synchronous dynamic memory can be set from the processor LSI.

[Brief description of drawings]

FIG. 1 is a processor LS of an information processing device using the present invention.
It is a block diagram of I.

FIG. 2 is an access pattern (time change) in a conventional information processing apparatus.

FIG. 3 is an access pattern (time change) in the information processing apparatus using the present invention.

FIG. 4 is a system diagram including a synchronous dynamic memory having a 2-bank configuration.

FIG. 5 shows a dynamic memory and its control circuit in an information processing apparatus using the present invention.

FIG. 6 is a configuration diagram of a processor LSI of another information processing apparatus using the present invention.

7 is a bank selection circuit and a bank bit selection circuit of the processor shown in FIG.

8 is a configuration diagram of an information processing apparatus using the processor shown in FIG.

[Explanation of symbols]

100 ... Processor LSI, 101, 102 ... Row address register (storage unit), 103, 104 ... Valid bit, 105, 106 ...
Selection circuit, 107 ... Matching comparator, 108 ... Control circuit, 109 ... Selection circuit, 110 ... Address bus, 111 ... Access request signal,
112 ... Selected row address, 113 ... Comparison result, 114 ...
Address terminal for dynamic memory, 115 ... Bank control signal, 116 ... Row address strobe signal, 117 ... Column address strobe signal, 201 ... Processor access request, 202 ... Dynamic memory address signal, 203 ... Row address Strobe signal, 204 ... Column address strobe signal, 205 ... Physical address address allocation diagram, 301 ... Processor access request, 302 ... Dynamic memory address signal, 303 ... Row address strobe signal, 304 ... Column Address / strobe signal, 305 ... Address assignment diagram of physical address, 306 ... Bank control signal, 401, 402 ... Synchronous dynamic memory of two-bank configuration, 403, 404 ... Memory,
405, 406 ... Memory access control circuit, 407 ... Inverter (logic inverter), 408 ... Input / output data mask control signal, 409, 410 ... Data terminals, 411, 412 ... Write (write) enable signal, 413, 414 ... Clock signal, 415, 4
16 ... Clock enable signal, 501, 503 ... Inverter (logic inverter), 502 ... 2-input AND gate, 504, 505
... dynamic memory, 506, 508 ... row address strobe signal, 507, 509 ... column address strobe signal, 600 ... processor LSI, 601, 602 ... row address register, 603, 604 ... valid bit, 605, 606 , 61
5 ... Selection circuit, 607 ... Matching comparator, 608 ... Control circuit, 609 ...
Same row area instruction signal, 610 ... Address bus, 611 ... Access request signal, 612 ... Selected row address, 613 ... Comparison result, 614 ... Address terminal, 616 ... Output buffer, 617
... Dynamic memory operation mode register, 701 ... Bank bit bit position selection signal, 702 ... Selection circuit, 703
... Bank bit signal, 704, 705, 706, 707 ... Request address individual bit signal line, 801 ... External circuit control LS
I, 802 ... Address register, 803 ... Selection circuit, 804 ... Access request management logic, 805 ... Row address, 806 ... Column address, 807 ... Upper address, 808 ... Access request signal,
809 ... Row address strobe signal, 810 ... Column address strobe signal, 811 ... System address bus, 812 ...
System data bus, 813 ... Chip select signal, 814 ...
Address decoder ... 815, Synchronous dynamic memory operation mode setting request signal, 816 ... Write (write)
Enable signal.

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Noriharu Hiratsuka             1-280, Higashi Koikekubo, Kokubunji, Tokyo             Central Research Laboratory, Hitachi, Ltd. (72) Inventor Tetsuhiko Okada             1-280, Higashi Koikekubo, Kokubunji, Tokyo             Central Research Laboratory, Hitachi, Ltd. (72) Inventor Hiroshi Takeda             5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Stock             Ceremony Company Hitachi Semiconductor Division F-term (reference) 5B060 AB19 HA06

Claims (8)

[Claims] 1. A processor for outputting an access address for accessing a memory, wherein the access address has a row address, a column address and a bank address, and the processor is the bank address of the access addresses. A processor having a control circuit for designating the position of the processor. 2. The processor according to claim 1, further comprising a first selector to which the access address is input, the first selector receiving the control signal output from the control circuit, A processor which outputs a bank bit control signal corresponding to the bank address among access addresses. 3. The memory according to claim 2, wherein the memory has a plurality of banks, and the processor has a plurality of address registers provided corresponding to the plurality of banks and a second address register connected to the plurality of address registers. A processor further comprising a selector, wherein the second selector selects one of the plurality of address registers according to the bank bit control signal. 4. The address register according to claim 3, wherein the plurality of address registers hold a row address of an access address issued to the corresponding plurality of banks, and the first selector issues the row address to the memory. Output a bank bit control signal corresponding to the bank address of the current access address, and the processor stores a row address stored in an address register selected by the second selector based on the bank bit control signal. A processor further comprising a comparator for comparing a current access address with a row address. 5. The processor according to claim 3, wherein when the row address held in the address register selected by the second selector matches the row address of the current access address, A processor having an operation mode in which a row address of an access address is not output. 6. The processor according to claim 1, wherein the processor can set the position of the bank address by a specific instruction. 7. The processor according to claim 1, wherein the processor outputs the row address and the column address of the access address in parallel. 8. A processor capable of setting a position of a bank address in an access address to a memory.