JPH06259370A - Data processing system and processor used for the same - Google Patents

Abstract

PURPOSE:To provide the high-speed system including a processor and a clock synchronous type dynamic memory and to guarantee conditions under which an input/output controller can attain direct memory access DMA to a main storage all the time. CONSTITUTION:An address of the clock synchronous DRAM 102 is supplied at a high speed directly from the processor through a dedicated address bus 108. Further, when an access object is the clock synchronous DRAM 102 at the time of DMA processing by the input/output controller 104, the processor 101 sends the address from a processor system bus 109 to an address bus 108 to access the DRAM 102. Consequently, high-speed access to the clock synchronous DRAM 102 by the processor 101 can be performed through the dedicated address bus 108.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing system and a processor used therefor, and more particularly to a high speed access technique when a main memory is a clock synchronous dynamic memory.

[0002]

2. Description of the Related Art A description of an external terminal of a conventional microprocessor (hereinafter simply referred to as a processor) is given, for example, in "i".
486 _TM Microprocessor User's Manual, 1989 "(Intel i486 _TM Microprocessor, 1989)
1.0 TABLE OF CONTENTS, 7.2.1 NON-CACHEABLE NON-B
It is described in URST SINGLE SYSLE, 7.2.9 BUS HOLD.

In a conventional processor system, a main memory for storing data or instructions is constructed by using a low-priced general-purpose dynamic memory. The specifications of such a general-purpose dynamic memory are described on pages 389 to 3 of "Hitachi IC Memory Handbook 2"('91 .9).
See page 93. As described above, the conventional dynamic memory does not have a clock input as an input signal of the chip, and an internal operation clock is generated from another control input signal inside the chip at the time of reading / writing. In addition, since there is no mode register inside which defines the operation mode of the dynamic memory, the operation mode is basically single in the conventional dynamic memory. Further, the inside of the dynamic memory is composed of a single bank.

On the other hand, a dynamic memory LSI for inputting a clock terminal is disclosed in "Nikkei Electronics, June 8, 1992 (No. 556)", pages 109 to 113.
It is described on the page. On page 111 of this document, 100
The figure shows a DRAM in which a clock signal of MHz can be input to access data at a rate of once per clock, and a DRAM in which a clock signal of 250 MHz can be input to access data at a rate of twice per clock.

The above "i486 _™ microprocessor
According to the User's Manual, the i486 _™ processor uses a 30-bit address external terminal A31-A2 and a 32-bit data external terminal D3 as a processor bus.
1-D0. Further, it is described that the external input terminals RDY # and BRDY # are provided and asserted (the signal becomes a logical value 1) in synchronization with the completion of the access operation of the processor external circuit. Further, it is described that it has an external input terminal called HOLD and is asserted when a processor external circuit requests the use of the processor bus. It is also described that it has an external output terminal called HLDA, responds to HOLD, and asserts when the processor external circuit can use the processor bus. The signal HOLD is a bus right acquisition request signal, and the signal HLDA is a bus right acquisition approval signal.

Generally, the bus right acquisition request signal and the bus right acquisition approval signal are DMA (Direct) in which a device other than the processor, for example, an input / output controller directly accesses the main memory.
Memory Access) is provided to enable processing.

[0007]

Prior art processor LS
An information processing system constructed using the technology of I
It is FIG. In FIG. 2, 201 is a processor LSI, 2
Reference numeral 02 is an input / output controller, 203 is a magnetic disk device, 204 is a main storage device, 205 is a graphic memory, 206 is a 30-bit processor / address bus,
207 is a 32-bit processor data bus, 20
8: HOLD is a bus right acquisition request signal, 209: HLDA
Is a bus right acquisition approval signal, 210: RDY # is a data transfer completion signal, and 211 is an input / output bus. By checking the assertion of 208: HOLD and 209: HLDA by the I / O controller 202 in FIG.
The use of processor buses 206 and 207 is approved, and DM
The A processing makes it possible to directly access the main memory.

On the other hand, in the system of FIG. 2, some problems occur especially when the main memory LSI has a high speed. The most problematic aspect of the system of FIG.
1 is the difficulty of the timing design when the address is transmitted to the dynamic memory which is the main memory device 204 via the processor address bus 206. In a system using dozens of memory LSIs, a buffer LSI for address terminals is required due to the problem of load capacity. In particular, since the address signal must be supplied to all the devices on the processor bus for decoding the address and all the memory LSIs, the total load capacity of the address bus 206 is larger than that of the data bus 207. Further, a signal delay time is generated in order to pass through the buffer LSI, which requires an access time longer than the original access time of the dynamic memory. Further, when a memory LSI that operates in synchronization with a high-speed clock described in the above-mentioned “Nikkei Electronics” document is used, a processor and a memory L are used.
Interposing a buffer with SI causes a problem that timing design becomes more difficult due to the short cycle time.

Therefore, an object of the present invention is to minimize the access time of a main memory in a system including a processor and a dynamic memory LSI which is a main memory. Another object of the present invention is to enable a controller performing DMA in a DMA processing of a system including a processor and a dynamic memory LSI which is a main memory device to correctly access all the main memory devices.

[0010]

A typical embodiment of the present invention is an LSI which is a processor 101, and a main storage device 1.
02, a clock synchronous dynamic memory, a processor LSI 101, and external devices 103, 104, 10
First address bus 10 connecting 5, 106, 107
9, processor LSI 101, and dynamic memory 1
02 is directly connected to the second address bus 108. The clock synchronous dynamic memory is a dynamic memory LSI having an external clock input terminal and operating in synchronization with an external clock input signal.

In a further preferred embodiment of the present invention,
When the input / output controller 104, which is one of the external devices connected to the first address bus 109, performs DMA processing, and the address accessed by this DMA processing is the address of the dynamic memory 102, the processor The address is transmitted from the address bus 109 to the second address bus 108.

[0012]

The address supplied from the processor to the clock synchronous dynamic memory, which is the main storage device, is separate from the first address bus for transferring the address supplied from the processor to an external device other than the clock synchronous dynamic memory. Since the data is transferred via the second address bus provided, a signal delay for passing through the conventional buffer LSI does not occur during the transfer via the second address bus. D performed by devices other than the processor
During the MA process, the processor transmits the address issued by the DMA to the clock synchronous dynamic memory, which is the main storage device, so that the DMA process can be correctly executed. Other objects and features of the present invention will be apparent from the following examples.

[0013]

1 shows a data processing system according to an embodiment of the present invention. 101 is a processor LSI, and 101 is a single LSI. Reference numeral 102 denotes a clock synchronous dynamic memory LSI as a main storage device.
2 is realized by a plurality of LSIs, a detailed description of which will be given later. Dynamic memory LSI 102
The major feature is that the address is supplied from the processor LSI 101 via a dedicated address bus 108. 109 is a processor address bus, 110 is a processor data bus, and 109 and 110 are collectively referred to as a processor bus. Processor bus 109,
A processor LSI 101, a floating point processor 103, an input / output controller 104, an additional main storage device 106, and a graphic memory 107 are connected to 110. A clock synchronous dynamic memory LSI 102 is connected to the processor / data bus 110. The additional main storage device 106 is used to increase the memory capacity of the main storage of this data processing system. Reference numerals 111, 112 and 113 are control signal lines of the processor buses 109 and 110. 111: hr
q is a signal that is set to "1" when a device other than the processor LSI 101 becomes a bus master and directly requests to use the processor buses 109 and 110. 11
2: Hack is a response signal to hreq, and
When (112) becomes "1", the processor LSI1
A request for a device other than 01 is acknowledged by the processor 101, and the requesting device is the processor bus 10
Indicates that 9,110 may be used. 113: rea
dy is a signal indicating the end of data transfer. ready
Since it is a promise that the bus cycle will end when (113) is set to "1", by extending the setting of ready (113) to "1", it is possible to use a storage device with a long access time. is there. Further, the input / output controller 104 has a DMA function. Although not shown, individual input / output devices such as a keyboard and a display are connected to the input / output controller 104 via the input / output device bus 114. Magnetic disk drive 1
Reference numeral 05 is an example of a typical input / output device. The address of the processor address bus 109 during the DMA processing of the input / output controller 104 can be transferred to the clock synchronous dynamic memory LSI as the main memory device 102 via the processor 101 and the dedicated address bus 108. . Reference numeral 115 denotes a clock pulse generator, which generates a system clock of the data processing system. Reference numerals 116 and 117 are the clock output signals. 1
The frequencies of 16 and 117 have a 2: 1 relationship, and 11
At the rise of 7 (transition from "L" to "H"),
116 is also synchronized so that it also starts up.

The address and data flow when the processor LSI 101 accesses the main memory will be described. When the location of the memory to be accessed is the synchronous dynamic memory LSI 102 which is the main storage device, the processor LSI 101 uses the dedicated address bus 108.
And the processor data bus 110 are used to access the synchronous dynamic memory 102. When the location of the memory to be accessed is the additional main storage device 106, the processor LSI 101 uses the processor address bus 109 and the processor data bus 110 to access the additional main storage device 106.

A block diagram of the LSI of the main memory device 102 is shown in FIG. The main storage device 102 is composed of four dynamic memory LSIs 301, 302, 303, 304. These dynamic memory LSIs 301, 302, 30
The interface signals of 3, 304 are as follows. A0-A11 (108): Address signal. input. Row and column addresses are entered in a multiplex fashion. That is, 11 bits of A0-A10 are used for the row address, and 9 bits of A0-A8 are used for the column address. Incidentally, A11 at the time of inputting a row address is used for designating a bank. / RAS (305): Row address strobe signal. input. When sending a row address, it is asserted (Low level, hereinafter, L). / CAS (306): Column address strobe signal. input. Assert (L) when sending the column address. / DQM (307): Data mask signal. input. It becomes an output enable signal of IO7-IO0 (110) at the time of reading. At the time of reading, the output 110 remains in the high impedance state unless this signal is asserted (“L” level). On the other hand, when writing, it becomes a write enable signal. At the time of writing, by asserting this signal (“L” level), data is actually written. IO0-IO7 (110): Data signal. Input and output. Data signal interface for read / write. / WE (309): Write enable signal. input. Assert (“L” level) when instructing data writing. CLK (117): Clock signal. input. The value on the input signal of this chip is taken into the chip in synchronization with this signal at the rising edge. An output is sent to the outside of this chip in synchronization with this signal at the rising edge. / CKE (308): Clock enable signal. When this signal is negated (H), the clock input CLK (11
7) is not transmitted inside the LSI. Note that / WE (309) is the four memory LSIs 301-
Since it is independent of 304, rewriting for each byte is possible. Also, / CKE (308) does not function in this device and is fixed at L level. Clock synchronous LSI
301 and 304 have mode registers inside, / RA
When all three of S, / CAS and / WE are at L level, the mode register is written via IO0-IO7. The value of the internal mode register is RA
S delay: Number of clocks from RAS input to data output,
CAS delay: Specifies the number of clocks from CAS input to data output, wrap length: size of address to wrap around. For example, if you specify 4 for the lap length,
Address is 0-1-2-3, 1-2-3 in clock units
Wrap around like -0, 2-3-0-1, 3-0-1-2. Although not shown in FIG.
305, 306, 307, 309 are processor LSI1
It is supplied from 01. The clock synchronous dynamic memories 301, 302, 303, 304 are synchronized with the clock signal 117 of the data processing system. At the time of reading the memory, in synchronization with the rising edge of the clock signal 117, 301-304 output valid data and the processor LSI 101 takes in the data. When writing to the memory, the processor LSI 101 outputs valid data and the processors 301 to 304 take in the data in synchronization with the rising edge of the clock signal 117. reading,
The clock signal 117 is used for both the writing and the data transfer.
1 clock pitch.

FIG. 4 shows an operation flowchart when the input / output controller 104 directly accesses the main storage device by using the DMA mechanism. The operation is, for example, a memory swap operation that occurs in the operation of the virtual storage system and the magnetic disk device 105 and the main storage device 102 or 106.
Occurs when transferring data to and from. Process 401: Start. Go to process 402. Process 402: Set the hreq (111) signal to 1. Go to processing 403.

Step 403: Check the hack (112) signal. If 1, go to process 404. If 0, go to step 403. Process 404: Data transfer is performed in synchronization with ready (113). In the case of a write (write) operation to the main memory, the data is transmitted from the input / output controller 104 to the main memory 102 or 106. In the case of a read operation from the main memory, data is stored in the main memory 102.
Alternatively, it is transmitted from 106 to the input / output controller 104. Go to processing 405. Process 405: If the transfer is completed, go to process 406. Otherwise, go to process 404. Process 406: The hreq (111) signal is set to 0. Go to processing 407. Process 407: End of the flowchart.

Further, a bus right acquisition request signal hreq (11
1) Processor LSI 101 when a signal is asserted
FIG. 5 shows a flowchart of the above operation. Process 501: Start. Go to processing 502. Process 502: Check whether or not the processor LSI 101 itself is using the processor bus. Process 50 if in use
Go to 2. Otherwise, go to processing 503. Process 503: The hack (112) signal is set to 1. Go to processing 504. Process 504: The address on the processor address bus 109 is decoded. Go to processing 505. Process 505: If the address on the processor address bus 109 is the address assigned to the main memory 102, proceed to process 506. Otherwise, go to processing 509. Process 506: The main memory 102 is accessed. The address on the processor address bus 109 is divided into a row address and a column address and transmitted to the dedicated address bus 108. Then, the data in the main memory 102 is transferred. Go to processing 507. Process 507: Assert ready (113). Go to processing 508. Process 508: Check the hreq (111) signal. ”
If it is 0 ", proceed to processing 510. If it is" 1 ", proceed to processing 509. Processing 509: Check whether or not the next data transfer has started. If starting, proceed to processing 504. Otherwise, processing 50.
Go to 8. Process 510: End of the flowchart.

FIG. 6 is a diagram showing the configuration of an address decoding device existing inside the processor LSI 101. The address decoding device 601 includes an address register 6
02 and a comparator 603. Address register 60
Reference numeral 2 is a register that can be set from the processor LSI 101, and is a synchronous dynamic memory LS that is a main storage device.
It has a function of designating the address position of I102. Processor address bus 1 during bus cycles generated by external circuits
The 9-bit value of 09 is compared with the 9-bit value (603) of the address register 602, and the comparison result is the signal line 605.
Is transmitted to another control circuit via. This comparison operation enables the determination operation of 505 in FIG.

The embodiment of the present invention has been described in detail above.
The present invention is not limited to the above embodiments, but various modifications can be made within the scope of the technical idea thereof. For example, the processor 101 can have a primary cache memory of on-chip instruction cache and data cache in its LSI chip, and the synchronous dynamic memory 102 can have a secondary cache memory such as cache SRAM in its LSI chip. You can

[0021]

The address supplied from the processor to the clock synchronous dynamic memory which is the main memory is
High-speed transfer is performed via a dedicated address bus provided separately from an address bus for transferring an address supplied from the processor to an external device other than the clock synchronous dynamic memory.

DM performed by a device other than the processor
At the time of A processing, the processor transmits the address issued by the DMA to the synchronous dynamic memory which is the main storage device, so that the DMA processing can be correctly executed.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a data processing system using a processor according to an embodiment of the present invention.

FIG. 2 is a configuration diagram of a conventional data processing system.

FIG. 3 is a clock synchronous dynamic memory 10 of FIG.
It is a figure which shows the structure of 2.

4 is a diagram showing a process when the input / output device 104 of FIG. 1 performs a DMA process.

5 is a diagram showing a process performed by a processor 101 of FIG. 1 when a bus right acquisition request signal hreq is asserted.

6 is a diagram showing the configuration of an address decoding device inside the processor 101 of FIG.

[Explanation of symbols]

101 ... Processor LSI, 102 ... Clock synchronous dynamic memory LSI, 103 ... Floating point processor, 104 ... Input / output controller, 105 ... Magnetic disk device, 106 ... Extended main storage device, 107 ... Graphic memory, 108 ... Dedicated address bus, 109 ... Processor address bus, 110 ... Processor data bus, 111 ... Bus right acquisition request signal, 112 ... Bus right acquisition approval signal, 113 ... Data transfer completion signal, 114 ... Input / output bus, 115 ... Clock pulse generator, 116 ... Clock signal, 117 ... Clock signal, 201 ... Processor LSI, 202 ... Input / output controller, 203 ... Magnetic disk device, 204 ... Main memory device, 205 ... Graphic memory, 206 ... Processor address bus, 207
... processor / data bus, 208 ... bus right acquisition request signal, 209 ... bus right acquisition approval signal, 210 ... data transfer completion signal, 211 ... input / output bus, 301, 302, 30
3, 304 ... Clock synchronous dynamic memory, 30
5 ... Row address strobe signal, 306 ... Column address strobe signal, 307 ... Data mask signal, 308 ... Clock enable signal, 309 ... Write enable signal, 401 ... Flowchart start, 402 ... 406
... Processing 407 ... End of flowchart 501 ... Start of flowchart 502 ... 509 ... Processing 510
... End of flow chart, 601 ... Address decoder, 602 ... Address register, 603 ... Match comparator,
604 ... Signal line, 605 ... Matching determination result.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Noriharu Hiratsuka 1-280 Higashi Koikekubo, Kokubunji City, Tokyo Inside Hitachi Central Research Laboratory

Claims (8)

[Claims] 1. A data processing system comprising a processor, an address bus connected to the processor, and a main memory device and an external device accessed via the address bus, wherein the main memory device comprises: A clock synchronous dynamic memory to which a clock signal synchronized with the clock of the processor is supplied, wherein the address bus is a first address bus connecting the processor and the external device, the processor and the clock synchronous type Second connection with dynamic memory
Data bus, wherein the processor has a first address terminal connected to the first address bus and a second address terminal connected to the second address bus. Processing system. 2. The external device comprises an input / output device for executing a direct memory access process with respect to the main memory device, wherein the access target of the direct memory access process is the clock synchronous dynamic memory. 2. The data according to claim 1, wherein the processor is configured to detect and transfer the address of the second address bus to the first address bus in response to the detection result. Processing system. 3. The data processing system according to claim 2, wherein the processor is capable of bidirectionally transmitting an address with respect to the second address terminal. 4. The data processing system according to claim 1, wherein the external device includes an additional main storage device different from the clock synchronous dynamic memory. 5. A main memory device and an external device connected to an address bus, wherein the main memory device is a clock synchronous dynamic memory, and the address bus is a first address connected to the external device. A processor used in a data processing system comprising a bus and a second address bus connected to the clock synchronous dynamic memory, the clock being synchronized with a clock signal supplied to the clock synchronous dynamic memory. A first address terminal that operates and outputs an address to the first address bus; and a second address terminal that outputs an address to the second address bus
And an address terminal of the processor. 6. A means for detecting that an access target of a direct memory access process for the main memory by an input / output device in the external device is the clock synchronous dynamic memory, and a response to a detection result of the detecting means. 6. The processor according to claim 5, further comprising means for transferring an address of the second address bus to the first address bus. 7. The processor according to claim 6, wherein an address is bidirectionally signaled with respect to the first address terminal. 8. The detecting means comprises a first means for storing address information of the clock synchronous dynamic memory and a second means for comparing the stored address information with information of an address of the second address bus. 8. A processor according to claim 7, comprising means.