JP2003198598A - Address table management method and address table management device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress to a minimum the movement of an entry associated with the entry registration and deletion of IP addresses. <P>SOLUTION: The head and tail of a storage area for each block in an address table 13a registered with IP addresses are pointed by a pointer and the address of a unused entry caused by the deletion of an entry is registered in a stack memory 11b. When registering an IP address in the address table 13a, a processor 12 for device management detects the unused entry from the stack memory 11b and a network processor 14 performs the entry registration of this IP address in the unused area of the address table 13a. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an address table management method and an address table management device for registering an entry of an upper layer address in an address table and deleting an entry of an upper layer address from the address table.

[0002]

2. Description of the Related Art Conventionally, data flowing on the Internet is composed of, for example, a unit of digital data called a packet. In a network relay device such as a router provided between networks, the network processor for relay processing recognizes this packet received from one network, relays the data, and then transfers it to the other network. There is. With regard to the relay processing in this network relay device, the demand for very high-speed processing has been increasing with the increase in the capacity of data communication in recent years, and various methods have been devised for solving the problem. .

The main operation of this relay process is to obtain the transfer destination port from the destination address or the source address stored in the header of the packet. For example, the address is used to obtain the transfer destination port using this address as a search key. Was used to store the address table. This address table is configured in the memory connected to the network processor for relay processing. To enable high-speed address search and efficient memory use of this address table, management of this address table is required. Method was an important issue.

Such an address table is used, for example, in a CAM (Content) which is a special memory capable of high speed retrieval.
nt Addressable Memory), it has become possible to greatly improve the performance of the network relay device.

In this address table, in order to easily search the entry to be registered, the memory is divided into blocks in advance by the number of different prefix lengths. And C
A general-purpose memory different from the AM is provided, and this general-purpose memory has a management table as shown in FIG. 17, which is controlled by a processor for device management, and registers and deletes entries so that the order of blocks does not change. . That is, a pair of floor pointer (FloorPTR) and next free pointer (NextFreePTR) is prepared for each block 0, 1, 2, ..., N (n is an arbitrary integer). This floor pointer indicates the top address entered in the corresponding block, and the next free pointer is
It shows the beginning of the unused area of the corresponding block.

CIDR (Classless Inte)
An address table using an address management method based on r Domain Routing) is divided into, for example, three blocks 0, 1, and the entries registered in each block have different prefix lengths. This entry is indexed (Inde
x) Sorts are arranged such that long prefixes are grouped and arranged to the smaller number.

FIG. 18 shows a case where the network processor registers address information in the entry indicated by the next free PTR corresponding to a block having the same prefix length in such an address table and reconfigures the block. The flowchart will be described with reference to the flowchart of FIG. For example, the entry “164.99.42.X”
(X matches any decimal number from 0 to 255)
In the case of registering in the address table shown in, the block 0 having the same prefix length (index number (table address) "01000" to "01FF"
F "). That is, as shown in FIG. 18, the device management processor uses the management table (see FIG. 17) to enter an entry (next free) indicating the beginning of the unused area of the corresponding block 0. PTR (0)) is acquired (step 101), and this block 0 is acquired.
It is determined whether there is an unused area (step 10).
2).

If there is this unused area,
Transfer the registration program to the network processor.
Based on this registration program, the network processor sets "16" at the position indicated by the next free PTR (0).
4.99.42. X "is registered in the address table (step 103). Further, the device management processor
As shown in FIG. 20, the next free PTR (0) is +
The management table is updated in association with the index number "01701" (step 104).

However, in step 102, if there is no unused area for entry registration in the corresponding block, a block reconfiguration procedure is required, so the block reconfiguration program is transferred to the network processor. (Step 105). When the network processor newly registers the entry “134.68.XX.X”, for example, based on this block reconfiguration program, the block 1 (index number “0200
0 ”to“ 02FFF ”). However, in this block, as shown in FIG. 19, the next free PTR (1) = floor PTR (2) is already set and a new entry is added. You cannot register.

In this state, in order to register the above-mentioned entry in the block 1, it is necessary to carry out the following procedure for expanding the block based on the program for reconstructing the block. First, the network processor is shown in FIG.
, The entry "1" indicated by the floor PTR (2)
92. X. X. X ″ is moved to an unused area indicated by the next free PTR (2).

This movement requires a procedure of reading this entry from the index number "03000", invalidating the entry (see FIG. 21), and adding an entry to the index number "03101" (see FIG. 22). Come on. Then, if the floor PTR (2) is modified to +1,
An unused area appears at the position of the index number “03000” indicated by the next free PTR (1).

Then, the network processor registers a new entry "134.68.XX.X" in the area indicated by the next free PTR (1) which has become the unused area (step 103), and the next free PTR. (1)
Was changed to +1 and the address table was updated (step 104), and entry registration in block 1 was completed.

Next, the case of deleting an entry will be described with reference to the flowchart of FIG. 23 and the address table configuration diagrams of FIGS. 24 and 25. Deleting this entry requires not only invalidating the entry, but also reconfiguring the block so that the entry can be reused. For example, as shown in FIG. 24, consider a case where it is desired to delete the entry "186.X.XX.X" of the index number "03050" located near the center of the block 2.

First, the network processor invalidates the entry "186.XX.XX.X" to be deleted based on the deletion program transferred from the device management processor (step 201). Next, the network processor reconfigures the block 2 based on the block reconfiguration program transferred from the device management processor in order to prevent a free area from being created in the middle of the block (step 202). ). In the reconfiguration of the block 2, the previous entry "192.X.XX.X" indicated by the next free PTR (2) is written to the invalidated entry (index number "03050").

In this writing operation, reading from the index number "03101" of this entry,
Invalid entry (see Fig. 24), index number "0"
The procedure of writing an entry to the 3050 ″ (see FIG. 25) is required.

Then, the device management processor updates the management table by changing the next free PTR (2) to -1 (step 203), and collects the unused areas into one, whereby the entry of the block 2 is deleted. The deletion was completed.

[0017]

However, in the above conventional example, the operation of adding or deleting an entry to the CAM is
The need for frequent block restructuring has arisen. The read / write operation of the CAM entry accompanying this reconfiguration takes much longer than the search, and causes a delay in other operations. Therefore, there is a problem that the processing performance of the entire device is deteriorated. It was

The present invention has been made in view of the above problems, and it is an object of the present invention to provide an address table management method and an address table management apparatus capable of minimizing the movement of entries due to entry registration and deletion of addresses. To aim.

[0019]

In order to achieve the above object, according to the present invention, an address table management method is provided which has an address table divided into a plurality of storage areas and manages the address table. An entry step of registering or deleting a layer address in a predetermined storage area of the storage area of the address table;
A first setting step of setting first and second instruction information for instructing the beginning and the end of the storage area in which the upper layer address is registered in each of the storage areas, and an unused state caused by deleting the entry. A registration step of registering the address of the entry in the registration table; and a second setting step of setting in the registration table the third instruction information for instructing the address of the unused entry caused by the deletion of the entry. A featured address table management method is provided.

According to the present invention, by indicating the head and tail of the storage area in which the upper layer address is registered and registering the address of the unused entry generated by the deletion of the entry in the registration table, When registering an upper layer address in the storage area, it is sufficient to make an entry in an unused area of this storage area, so that the movement of the entry due to the entry registration and deletion of the address is minimized.

According to a second aspect of the present invention, in the above invention, when the upper layer address is input in the entry step, an unused entry in the predetermined storage area is detected, and the upper layer address is detected. The unused entry is registered, and the first and second instruction information are used to indicate the head and tail of the storage area in which the upper layer address is registered by the first setting step. The unused entry address in which the upper layer address is registered is deleted from the registration table, and the second
In the setting step, the address of the next unused entry registered in the registration table is instructed by the third instruction information.

According to the present invention, when an upper layer address is input, an unused entry is detected and registered in this unused entry, and the address of this unused entry is deleted from the registration table to delete the address entry. Register and delete quickly.

According to claim 3 of the present invention, in the above invention, when the entry is deleted, in the entry step,
The entry of the corresponding upper layer address registered in the predetermined storage area is deleted, and in the registration step, the address of the unused entry generated by the deletion is registered in the registration table.

According to the present invention, when an entry is deleted, the entry in which the upper layer address of the corresponding storage area is registered is invalidated, and the address of the unused entry is registered in the registration table. Reduce the number to minimize the movement of entries due to entry registration and deletion of addresses.

According to a fourth aspect of the present invention, in the above invention, the upper layer address is an IP address.

According to the present invention, the upper layer address is an IP (Internet Protocol) at the layer 3 level.
l) By using an address, it can be used on the Internet.

According to a fifth aspect of the present invention, in the address table management device for managing an address table which is divided into a plurality of storage areas and stores an input upper layer address in a predetermined storage area of the storage areas, Address table control means for registering an entry of the upper layer address in the table and deleting the entry, a registration table for registering an address of an unused entry caused by the deletion of the entry, and an address of the unused entry in the registration table Registration table control means for performing registration and deletion, first and second instruction information for instructing the head and tail of the storage area, and a third for instructing the address of an unused entry generated by deleting the entry.
Table for storing instruction information of the storage area, first instruction means for instructing the head and tail of the storage area by the first and second instruction information, and addresses of unused entries stored in the registration table. Is provided by the second instruction means for instructing by the third instruction information.

According to the present invention, a registration table is provided in addition to the address table to register the addresses of unused entries, thereby eliminating the need for frequent block reconfiguration as in the conventional case, and Improves overall processing performance.

According to a sixth aspect of the present invention, in the above invention, when the upper layer address is input, the table control means detects an unused entry in the predetermined storage area in which the upper layer address is registered. Then, the upper layer address is registered in the unused entry, and the first instructing means sets the head and tail of the predetermined area to the first and second areas.
And the registration table control means deletes the address of the unused entry when the upper layer address is registered in the unused entry,
The second instructing means causes the address of the next unused entry stored in the registration table to be instructed by the third instructing information.

According to the present invention, when the upper layer address is input, the table control means detects an unused entry and registers it in the unused entry, and the table control means records the unused entry from the registration table. Delete addresses to quickly register and delete address entries.

According to a seventh aspect of the present invention, in the above invention, when the entry is deleted, the table control means deletes the entry of the corresponding upper layer address registered in a predetermined storage area of the address table. The registration table control means registers the address of an unused entry generated by the deletion in the registration table.

According to the present invention, when an entry is deleted, the entry in which the upper layer address of the storage area of the corresponding address table is registered is invalidated by the table control means, and the unused entry is registered by the registration table control means. By registering these addresses in the registration table, the number of steps can be reduced and the movement of entries due to entry registration and deletion of addresses can be minimized.

[0033]

BEST MODE FOR CARRYING OUT THE INVENTION Preferred embodiments of an address table management method and an address table management device according to the present invention will be described below with reference to the accompanying drawings.

(First Embodiment) FIG. 1 is a block diagram showing the arrangement of an embodiment of an address table management device according to the present invention. In the figure, this address table management device 1
0 is the management table 11a and the stack memory 11b
General-purpose memory 11 including a memory, a device management processor 12 that controls the general-purpose memory 11, and an address table 13a.
And a network processor 14 that controls the CAM 13, and an internal bus 15 that connects the device management processor 12 and the network processor 14.

As shown in FIG. 2, the management table 11a has a floor pointer (FloorPTR) and a ceiling pointer (Ceil) for each block 0, 1, 2 ,.
ingPTR), empty stack pointer (Emp
Three pointers (tyStackPTR) are prepared as one set. The floor PTR indicates the head of the corresponding block, the ceiling PTR indicates the tail of the corresponding block, and the empty stack PTR is a general-purpose memory for registering the IP address (index number) of an unused entry generated when the entry is deleted. 11 shows the top of the stack memory above 11.

As shown in FIG. 3, the stack memory 11b is divided into, for example, three blocks 0, 1, 2, and each block (Block) has a memory address (Address) of the device management processor 12.
And the content (Content) in which the index number of the unused entry generated when the entry is deleted
And an empty stack PTR that indicates the beginning of the free area of each block. Note that FIG. 3 shows the stack memory in the initial state in which the index number indicating the unused area is not registered in the content.

The device management processor 12 controls not only the management table 11a but also the stack memory 11b for updating data, and registers or deletes index numbers so that the order of blocks does not change. Further, the device management processor 12 transfers a program for block reconfiguration, registration, or deletion to the network processor 14 via the internal bus 15 depending on the situation.

CIDR (Classless Inte)
As shown in FIG. 4, the address table 13a using the address management method based on r Domain Routing, for example, has three blocks 0,
The entry is divided into 1 and 2, and the entries registered in the respective blocks have different prefix lengths.
The entries are sorted so that the ones with long prefixes are grouped and arranged in the smaller index number.

The network processor 14 performs address registration, deletion and block reconfiguration for this address table 13a. Note that these operations are performed based on each program transferred from the device management processor 12. Next, the network processor 14 in the address table 13a
5 to 7 are flowcharts of the case of registering address information and the case of reconfiguring a block in the entry of the unused area of the block, and the configuration diagrams of the stack memory of FIG. 8 and the address table of FIGS. 9 to 11. It will be described based on. For example, when the entry “233.64.XX.X” is registered in the address table shown in FIG. 4, the block 1 having the same prefix length (index number (table address) “02000” to “02FF”) is registered.
F ”). In the stack memory, as shown in FIG.
For example, the index “02400” is assigned to the address “001
It is assumed that the entry is registered in 6000 ".

The device management processor 12 acquires the empty stack PTR (1) of the corresponding block of the management table 11a for the input address, and the empty stack PTR (1 of the corresponding block from the stack memory 11b of FIG. ) To search for an unused area (step 201). In this case, the area immediately before the area designated by the empty stack PTR (1) is searched for unused area information (step 2).
01). Then, it is judged whether or not there is an unused area in the corresponding block to be registered (step 202).

If there is an unused area in the block, the index number "02400" is fetched from the area immediately before the empty stack PTR and transferred to the network processor 14 together with the registration program. To the registration process (step 203), and the device management processor, as shown in FIG.
The management table 11a and the stack memory 11b are associated with the address "0016000" by decrementing (1) by -1.
Is updated (step 204).

The network processor 14 performs the registration operation of FIG. 6 based on this registration program, and registers the entry "233.64.XX.X" at the position indicated by the index number "02400" in the address table (step). 301).

If there is no unused area in the block 1 in step 202 in FIG. 5, a block reconfiguration procedure is required, so the device management processor 1
2 transfers the block reconstruction program to the network processor 14 (step 205).

The network processor 14 uses, for example, the block 1 based on this block reconstruction program.
In the case of newly registering the entry "68.128.XX." in the table, the ceiling PTR (1) and the floor PTR (2) are continuous as shown in FIG. For those who are not registered.

In this state, in order to register the above-mentioned entry in the block 1, it is necessary to carry out the following procedure for expanding the block based on the program for reconfiguring the block. First, the network processor 14
As shown in FIG. 10, the entry “192.X.XX.X” indicated by the floor PTR (2) is read (step 40
1) Move to the destination of the unused area shown next to the ceiling PTR (2) (entry to index number “03101”) and write (step 402). Then, as shown in FIG. 11, the network processor 14 moves the entry (index number “0300”
0 ”entry“ 192. X. X. X ″) is invalidated (step 403), and this floor PTR (2)
Is corrected to +1, the index number "03000"
An unused area appears at the position.

Next, the network processor 14 performs the registration operation of FIG. 6 based on the registration program to register the entry "68.128.XX.X" at the position indicated by the index number "03000" in the address table. (Step 301).

As described above, in this embodiment, since the IP address of the unused entry of the CAM registered in the stack memory is designated by using the pointer of the empty stack PTR, a plurality of unused entries are stored in the CAM. Even if they exist, it is possible to identify them.

(Embodiment 2) Next, the case of deleting an entry will be described with reference to the flowcharts of FIGS. 13 and 14, the address table of FIG. 15 and the stack memory configuration diagram of FIG. The purpose of deleting this entry is not only to invalidate the entry, but also to store the index number in the area indicated by the empty stack PTR. In this case, it is not necessary to move the entry due to the block rearrangement, which is conventionally required.

First, the device management processor 12 prepares a program for deleting the designated IP address from the address table 13a and transfers it to the network processor 14 (step 501).

As shown in FIG. 14, the network processor invalidates, for example, the entry "233.44.XX.X" to be deleted based on the received deletion program (step 601). This entry “233.44.
X. The deletion of X "is to invalidate the entry of the index" 02400 "of the address table 13a as shown in the configuration diagram of the address table of FIG.

When this entry is invalidated, the device management processor 12 causes the corresponding block 1 of the stack memory 11b indicated by the empty stack PTR (1) as shown in the stack memory configuration diagram of FIG. The index number "02400" is updated and registered as the unused area information in the address "0016000" (step 502 in FIG. 13).

As described above, in this embodiment, since the corresponding entry is invalidated and the index number thereof is stored in the area indicated by the empty stack PTR, the movement of the entry due to the reconfiguration of the block, which is conventionally required, is not required. The number of steps required for address deletion is drastically reduced, entry movement can be minimized, and the address table on the CAM can be efficiently used without degrading the processing performance of the entire device. Can be managed.

Here, the number of steps of the program in step 501 is n, step 601 is m, and otherwise 1
Then, the number of program steps in this case is 1 + n
+ M.

In addition, n is the transfer from the device management processor described in the conventional entry deletion, m is the invalidation of step 201, n is the transfer of the block reconfiguration program, m is the read of the entry, and m is the read of the read entry. M for writing, m for invalidating entries, 1 for updating the management table
Then, the number of program steps in this case is 1 + 2
It becomes n + 4m.

In general, the number of program steps n required to transfer a program is several tens to several hundreds of times that in one memory access. In addition, since the CAM is specialized for search execution, the network processor is CA
The number of program steps required to read / write M entries m is often several times the number of steps of search.

Therefore, when evaluated with n = 10 and m = 4, the evaluation value of this example was 15, and the evaluation value of the conventional example was 37. From this, this embodiment is
The number of steps could be greatly reduced in the deletion. It was also found that the algorithm works effectively in this embodiment in the case of an address table in which deletion can occur frequently.

The present invention is not limited to these embodiments, and various modifications can be made without departing from the gist of the present invention.

[0058]

As described above, according to the present invention, an address table divided into a plurality of storage areas is provided, and an input upper layer address is registered as an entry in a predetermined storage area of the storage areas of the address table. In addition to deleting, the address of the unused entry generated by deleting the entry from the address table is registered in the registration table. Therefore, when registering or deleting the upper layer address, the unused area of this address table is saved with a small number of steps. An entry or an entry can be deleted, and the movement of the entry due to the registration and deletion of the address entry can be minimized.

Further, according to the present invention, when an upper layer address is input, an unused entry is detected from the registration table, the upper layer address is registered in this unused entry, and the address of this unused entry is registered from the registration table. Since it is deleted, the unused area of the address table can be easily specified, and the address entry can be registered and deleted quickly.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing a configuration of an embodiment of an address table management device according to the present invention.

FIG. 2 is a table configuration diagram showing an example of a configuration of a management table shown in FIG.

FIG. 3 is a configuration diagram showing a first example (initial state) of the configuration of the stack memory shown in FIG.

FIG. 4 is a table configuration diagram showing a first example of the configuration of the address table shown in FIG.

5 is a flowchart for explaining an address registration operation of the device management processor shown in FIG.

6 is a flow chart for explaining a block reconfiguration operation of the network processor shown in FIG. 1. FIG.

FIG. 7 is likewise a flowchart for explaining the address registration operation of the network processor.

8 is a configuration diagram showing a second example of the configuration of the stack memory shown in FIG. 1. FIG.

9 is a table configuration diagram showing a second example of the address table shown in FIG.

FIG. 10 is also a table configuration diagram showing a third example of the address table.

FIG. 11 is also a table configuration diagram showing a change of the third example of the address table.

FIG. 12 is also a table configuration diagram showing a fourth example of the address table.

FIG. 13 is a flowchart for explaining an address deleting operation of the address table management device shown in FIG.

FIG. 14 is a flowchart for explaining an entry deletion operation of the network processor shown in FIG.

FIG. 15 is also a table configuration diagram showing a fifth example of the address table.

FIG. 16 is also a configuration diagram showing a third example of the configuration of the stack memory.

FIG. 17 is a configuration diagram showing a configuration of a conventional management table.

FIG. 18 is a flowchart for explaining conventional address registration and block reconfiguration operation.

FIG. 19 is a configuration diagram showing a configuration of a conventional address table.

FIG. 20 is also a configuration diagram showing the configuration of an address table.

FIG. 21 is a block diagram showing the structure of an address table.

FIG. 22 is a block diagram showing the structure of an address table.

FIG. 23 is a flowchart for explaining a conventional address deleting operation.

FIG. 24 is also a configuration diagram showing the configuration of an address table.

FIG. 25 is also a configuration diagram showing a configuration of an address table.

[Explanation of symbols]

0-2 blocks 10 Address table management device 11 General-purpose memory 11a management table 11b Stack memory 12 Device management processor 13 CAM 13a address table 14 Network processor 15 Internal bus PTR pointer

Claims (7)

[Claims] 1. An address table management method for managing an address table, comprising an address table divided into a plurality of storage areas, wherein an upper layer address to be input is a predetermined storage area of the storage areas of the address table. An entry step of registering or deleting an entry in, and a first setting step of setting first and second instruction information for instructing the beginning and the end of the storage area in which the upper layer address is registered in each of the storage areas. A registration step of registering an address of an unused entry caused by the deletion of the entry in a registration table, and setting third instruction information indicating an address of the unused entry caused by the deletion of the entry in the registration table An address table management method including a second setting step. 2. In the entry step, when the upper layer address is input, an unused entry in the predetermined storage area is detected, and the upper layer address is registered in the detected unused entry. Instructing the head and tail of the storage area in which the upper layer address is registered by the first setting step by the first and second instruction information,
In the registration step, the address of the unused entry in which the upper layer address is registered is deleted from the registration table, and in the second setting step, the address of the next unused entry registered in the registration table is deleted. The instruction is made by the third instruction information.
Address table management method described in. 3. When the entry is deleted, in the entry step, the entry of the corresponding upper layer address registered in the predetermined storage area is deleted, and in the registration step,
The address of an unused entry generated by the deletion is registered in the registration table.
Or the address table management method described in 2. 4. The address table management method according to claim 1, wherein the upper layer address is an IP address. 5. An address table management device for managing an address table which is divided into a plurality of storage areas and stores an input upper layer address in a predetermined storage area of the storage areas, wherein the upper layer to the address table is stored. Address table control means for registering an entry of an address and deleting an entry, a registration table for registering an address of an unused entry caused by the deletion of the entry, and registration for registering and deleting an address of the unused entry in the registration table Table control means, and first and second instructing the head and tail of the storage area
Management information for storing the third instruction information for instructing the address of an unused entry generated by deleting the entry, the head and tail of the storage area, and the first and second instruction information. Address table management comprising: first instructing means for instructing by the third instruction information; and second instructing means for instructing an address of an unused entry stored in the registration table by the third instruction information. apparatus. 6. When the upper layer address is input, the table control means detects an unused entry in the predetermined storage area in which the upper layer address is registered, and the upper layer address is used as the unused entry. The entry is registered in the entry, and the first instruction means sets the beginning and the end of the predetermined area to the first
And the second instruction information, the registration table control means deletes the address of the unused entry when the upper layer address is registered in the unused entry, and the second instruction means is operable to delete the address of the unused entry. The address table management device according to claim 5, wherein the address of the next unused entry stored in the registration table is instructed by the third instruction information. 7. When the entry is deleted, the table control means deletes the entry of the corresponding upper layer address registered in a predetermined storage area of the address table, and the registration table control means 7. The address table management device according to claim 5, wherein the address of the unused entry generated by the deletion is registered in the registration table.