JP2003198596A - Address table management method and address table management device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress to a minimum the movement of an entry associated with the entry registration and deletion of an IP address. <P>SOLUTION: The head of a storage area for each block in an address table 13a registered with IP addresses is pointed by a pointer, all the index numbers of unused entries caused by the deletion of entries are registered in a stack memory 11b and when registering an IP address on the address table 13a, a processor 12 for device management detects the index numbers of the unused entries from the stack memory 11b. Then, a network processor 14 performs the entry registration of this IP address in the unused area of the address table 13a. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an address table management method and an address table management device for registering an entry of an upper layer address in an address table and deleting an entry of an upper layer address from the address table.

[0002]

2. Description of the Related Art Conventionally, data flowing on the Internet is composed of, for example, a unit of digital data called a packet. In a network relay device such as a router provided between networks, the network processor for relay processing recognizes this packet received from one network, relays the data, and then transfers it to the other network. There is. With regard to the relay processing in this network relay device, the demand for very high-speed processing has been increasing with the increase in the capacity of data communication in recent years, and various methods have been devised for solving the problem. .

The main operation of this relay process is to obtain the transfer destination port from the destination address or the source address stored in the header of the packet. For example, the address is used to obtain the transfer destination port using this address as a search key. Was used to store the address table. This address table is configured in the memory connected to the network processor for relay processing. To enable high-speed address search and efficient memory use of this address table, management of this address table is required. Method was an important issue.

Such an address table is used, for example, in a CAM (Content) which is a special memory capable of high speed retrieval.
nt Addressable Memory), it has become possible to greatly improve the performance of the network relay device.

In this address table, in order to easily search the entry to be registered, the memory is divided into blocks in advance by the number of different prefix lengths. And C
A general-purpose memory different from the AM is provided, and this general-purpose memory has a management table as shown in FIG. 14 which is controlled by a processor for device management, and registers and deletes entries so that the order of blocks does not change. . That is, a pair of floor pointer (FloorPTR) and next free pointer (NextFreePTR) is prepared for each block 0, 1, 2, ..., N (n is an arbitrary integer). This floor pointer indicates the top address entered in the corresponding block, and the next free pointer is
It shows the beginning of the unused area of the corresponding block.

CIDR (Classless Inte)
An address table using an address management method based on r Domain Routing) is divided into, for example, three blocks 0, 1, and the entries registered in each block have different prefix lengths. This entry is indexed (Inde
x) Sorts are arranged such that long prefixes are grouped and arranged to the smaller number.

FIG. 15 shows a case where the network processor registers address information and reconfigures a block in the entry indicated by the next free PTR corresponding to a block having the same prefix length in such an address table. 16 and 19 and the table configuration diagram of the address table shown in FIGS. For example, the entry “164.99.42.X”
When X (matches any decimal number from 0 to 255) is registered in the address table shown in FIG. 16, block 0 having the same prefix length (index number (table address) is “01000”). ~ "01FFF")
You must register to. That is, the device management processor, as shown in FIG.
The entry (next-free PTR (0)) indicating the beginning of the unused area of the corresponding block 0 is acquired from (see step 4) (step 101). Then, it is determined whether or not there is an unused area in this block 0 (step 102).

If there is this unused area,
Transfer the registration program to the network processor.
Based on this registration program, the network processor sets "16" at the position indicated by the next free PTR (0).
4.99.42. X "is registered in the address table (step 103). Further, the device management processor
As shown in FIG. 17, the next free PTR (0) is +
The management table is updated in association with the index number "01701" (step 104).

However, in step 102, if there is no unused area for entry registration in the corresponding block, a block reconfiguration procedure is required, so the block reconfiguration program is transferred to the network processor. (Step 105). When the network processor newly registers the entry “134.68.XX.X”, for example, based on this block reconfiguration program, the block 1 (index number “0200
0 ”to“ 02FFF ”). However, as shown in FIG. 16, next free PTR (1) = floor PTR (2) is already set in this block, and a new entry is added. You cannot register.

In this state, in order to register the above-mentioned entry in the block 1, it is necessary to carry out the following procedure for expanding the block based on the program for reconstructing the block. First, the network processor is shown in FIG.
, The entry "1" indicated by the floor PTR (2)
92. X. X. X ″ is moved to an unused area indicated by the next free PTR (2).

This movement requires a procedure of reading this entry from the index number "03000", invalidating the entry (see FIG. 18), and adding an entry to the index number "03101" (see FIG. 19). Come on. Then, if the floor PTR (2) is modified to +1,
An unused area appears at the position of the index number “03000” indicated by the next free PTR (1).

Then, the network processor registers a new entry "134.68.XX.X" in the area indicated by the next free PTR (1) which has become the unused area (step 103), and the next free PTR. (1)
Was changed to +1 and the address table was updated (step 104), and entry registration in block 1 was completed.

Next, the case of deleting an entry will be described based on the flowchart of FIG. 20 and the address table configuration diagrams of FIGS. Deleting this entry requires not only invalidating the entry, but also reconfiguring the block so that the entry can be reused. For example, as shown in FIG. 21, consider a case where it is desired to delete the entry "186.X.XX.X" of the index number "03050" located near the center of the block 2.

First, the network processor invalidates the entry "186.XX.XX.X" to be deleted based on the deletion program transferred from the device management processor (step 201). Next, the network processor reconfigures the block 2 based on the block reconfiguration program transferred from the device management processor in order to prevent a free area from being created in the middle of the block (step 202). ). In the reconfiguration of the block 2, the previous entry "192.X.XX.X" indicated by the next free PTR (2) is written to the invalidated entry (index number "03050").

In this writing operation, reading from the index number "03101" of this entry,
Invalid entry (see Fig. 21), index number "0"
The procedure of writing an entry to the 3050 ″ (see FIG. 22) is required.

Then, the device management processor updates the management table by changing the next free PTR (2) to -1 (step 203), and collects the unused areas into one, whereby the entry of the block 2 is deleted. The deletion was completed.

[0017]

However, in the above conventional example, the operation of adding or deleting an entry to the CAM is
The need for frequent block restructuring has arisen. The read / write operation of the CAM entry accompanying this reconfiguration takes much longer than the search, and causes a delay in other operations. Therefore, there is a problem that the processing performance of the entire device is deteriorated. It was

The present invention has been made in view of the above problems, and it is an object of the present invention to provide an address table management method and an address table management apparatus capable of minimizing the movement of entries due to entry registration and deletion of addresses. To aim.

[0019]

In order to achieve the above object, according to the present invention, an address table management method is provided which has an address table divided into a plurality of storage areas and manages the address table. An entry step of registering or deleting a layer address in a predetermined storage area of the storage area of the address table;
A first setting step of setting first instruction information for instructing the beginning of a storage area in which the upper layer address is registered in each of the storage areas; and the upper layer address in the address table is not registered An address table including a registration step of registering an index number of an unused entry in a registration table, and a second setting step of setting second instruction information for instructing the unused entry in the registration table. A management method is provided.

According to the present invention, the storage area in which the upper layer address is registered is designated, and the index number of an unused entry in which the upper layer address is not registered is registered in the registration table to delete the entry. When an unused entry caused by the above occurs, the index number of this unused entry is registered in the registration table so that when the next higher layer address is registered, the second entry
Since it suffices to make an entry in an unused area of this storage area designated by the instruction information of 1, the movement of the entry due to entry registration and deletion of the upper layer address is minimized.

According to a second aspect of the present invention, in the above invention, when the upper layer address is input in the entry step, the head of an unused entry in a predetermined storage area is set based on the second instruction information. Detecting and registering the upper layer address in the detected unused entry, and instructing the head of the storage area in which the upper layer address is registered by the first setting step by the first instruction information, In the registration step, the index number of the unused entry in which the upper layer address is registered is deleted from the registration table, and in the second setting step, the address of the next unused entry registered in the registration table is deleted. It is characterized in that an instruction is given by the second instruction information.

According to the present invention, when the upper layer address is input, the head of an unused entry is detected and registered in this unused entry, and the index number of this unused entry is deleted from the registration table. Quickly register and delete upper layer address entries.

According to claim 3 of the present invention, in the above invention, when the entry is deleted, in the entry step,
The entry of the corresponding upper layer address registered in the predetermined storage area is deleted, and the index number of the unused entry generated by the deletion is registered in the registration table in the registration step.

According to the present invention, when an entry is deleted, the entry in which the upper layer address of the corresponding storage area is registered is invalidated, and the index number of the unused entry caused by this invalidation is stored in the registration table. By registering, the number of steps is reduced to minimize the movement of entries due to entry registration and deletion of upper layer addresses.

According to a fourth aspect of the present invention, in the above invention, the upper layer address is an IP address.

According to the present invention, the upper layer address is an IP (Internet Protocol) at the layer 3 level.
l) By using an address, it can be used on the Internet.

According to a fifth aspect of the present invention, in the address table management device for managing an address table which is divided into a plurality of storage areas and stores an input upper layer address in a predetermined storage area of the storage areas, Address table control means for registering an entry of the upper layer address in the table and deleting the entry; a registration table for registering an index number of an unused entry in the address table in which the upper layer address is not registered; Registration table control means for registering and deleting the index number of an unused entry in the registration table, first instruction information for instructing the head of the storage area, and second instruction for instructing the index number of the unused entry. A management table that stores information,
A first instructing means for instructing the head of the storage area by the first instructing information and a second instructing means for instructing an index number of an unused entry stored in the registration table by the second instructing information. There is provided an address table management device characterized by comprising an instruction means.

According to the present invention, a registration table is provided in addition to the address table to register the index numbers of unused entries, thereby eliminating the need for frequent block reconfiguration as in the prior art. Improve the processing performance of the entire device.

According to a sixth aspect of the present invention, in the above invention, when the upper layer address is input, the table control means starts the unused entry in the predetermined storage area in which the upper layer address is registered. Is detected, the upper layer address is registered in the unused entry, and the first instructing means causes the beginning of the predetermined area to be instructed by the first instructing information, and the registration table control means, When the upper layer address is registered at the head of the unused entry, the index number of the unused entry is deleted, and the second instruction means stores the address of the next unused entry stored in the registration table. The second
It is characterized in that the instruction is given by the instruction information.

According to the present invention, when the upper layer address is input, the head of the unused entry is detected by the table control means and registered in the unused entry, and at the same time, the table control means records the unregistered entry from the registration table. By deleting the index number of the used entry, the entry registration and deletion of the upper layer address can be performed quickly.

According to a seventh aspect of the present invention, in the above invention, when the entry is deleted, the table control means deletes the entry of the corresponding upper layer address registered in a predetermined storage area of the address table. The registration table control means registers the index number of an unused entry generated by the deletion in the registration table.

According to the present invention, when an entry is deleted, the entry in which the upper layer address of the storage area of the corresponding address table is registered is invalidated by the table control means, and the unused entry is registered by the registration table control means. By registering these addresses in the registration table, the number of steps is reduced and the movement of entries due to entry registration and deletion of upper layer addresses is minimized.

[0033]

BEST MODE FOR CARRYING OUT THE INVENTION Preferred embodiments of an address table management method and an address table management device according to the present invention will be described below with reference to the accompanying drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the address table management device according to the present invention. In the figure, this address table management device 10 includes a general-purpose memory 11 including a management table 11a and a stack memory 11b, a device management processor 12 for controlling the general-purpose memory 11, and a CAM including an address table 13a.
13, a network processor 14 that controls the CAM 13, and an internal bus 15 that connects the device management processor 12 and the network processor 14.

As shown in FIG. 2, the management table 11a prepares two pointers of a floor pointer (FloorPTR) and an empty stack pointer (EmptyStackPTR) for each block 0, 1, 2, ... This floor PTR indicates the head of the corresponding block, and the empty stack PTR is a general-purpose memory 1 for registering the index number of an unused entry.
1 shows the top of the stack memory located above 1.

As shown in FIG. 3, the stack memory 11b is divided into, for example, three blocks 0, 1 and 2, and each block (Block) has an index number of an unused entry in the address table 13a. An index (Index) to be registered and an empty stack PTR indicating the beginning of an empty area of each block
It consists of Note that FIG. 3 shows the stack memory in a state created in correspondence with the contents of the address table shown in FIG.

The device management processor 12 controls not only the management table 11a but also the stack memory 11b for updating data, and registers or deletes index numbers so that the order of blocks does not change. Further, the device management processor 12 transfers a program for block reconfiguration, registration, or deletion to the network processor 14 via the internal bus 15 depending on the situation.

As shown in FIG. 4, the address table 13a is divided into, for example, three blocks 0, 1 and 2, as in the conventional example shown in FIG. Fix lengths are different. This entry is, for example, CIDR (Classle) so that long prefixes are grouped and arranged in the smaller index (Index) number.
Sorting is performed by using an address management method according to ss Inter Domain Routing.

The network processor 14 performs address registration, deletion and block reconfiguration for this address table 13a. Note that these operations are performed based on each program transferred from the device management processor 12. Further, the network processor 14 sends the information of the index number corresponding to the unused entry of the address table 13a which is changed by the registration or deletion of the address to the device management processor 12. The device management processor 12 writes or deletes the index number in the stack memory 11b based on the input information of the index number.

Next, in the address table 13a, the network processor 14 registers the address information in the entry of the unused area of the block and reconfigures the block. The stack memory 11b of FIG. 8 and FIGS.
The address table 13a will be described with reference to FIG. For example, the entry “233.64.XX.X” is shown in FIG.
When registering in the address table 13a shown in (1), it is necessary to register in block 1 (index numbers “02000” to “02FFF”) having the same prefix length. In the stack memory 11b, as shown in FIG. 8, for example, an index "02400" is registered as an entry in the unused area of the block 1.

The device management processor 12 acquires the empty stack PTR (1) of the corresponding block of the management table 11a for the input address, and the empty stack PTR (1 of the corresponding block from the stack memory 11b of FIG. ) To search for an unused area (step 201). That is, the device management processor 12 retrieves the index designated by the empty stack PTR (1) in the block 1 and retrieves the index number information of the unused area therein (step 201). Then, it is judged whether or not there is an unused area in the corresponding block to be registered (step 202).

If there is an unused area in the block, the index number "02400" is fetched from the empty stack PTR area, transferred to the network processor 14 together with the registration program, and the network processor 14 is registered. (Step 203), and the device management processor further changes the empty stack PTR (1) by -1 to update the management table 11a and the stack memory 11b as shown in FIG. 3 (Step 204).

The network processor 14 performs the registration operation of FIG. 6 based on this registration program, and as shown in FIG. 9, the entry "233.6" is located at the position indicated by the index number "02400" of the address table 13a.
4. X. X "is registered (step 301).

If there is no unused area in the block 1 in step 202 in FIG. 5, a block reconfiguration procedure is required. Therefore, the device management processor 1
2 transfers the block reconstruction program to the network processor 14 (step 205).

The network processor 14 uses, for example, the block 1 based on this block reconstruction program.
In the case of newly registering the entry “65.128.XX.X” in the block 1, as shown in FIG. 3, there is no unused area in the block 1 and the unused area in the block 2 is also distant, and it is already used. Since the registered areas are continuous, it is impossible to register the larger index number as it is.

In this state, in order to register the above-mentioned entry in the block 1, it is necessary to perform the following procedure for expanding the block based on the program for reconfiguring the block. First, the network processor 14
As shown in FIG. 10, the entry “192.X.XX.X” indicated by the floor PTR (2) is read (step 40
1), the empty stack is moved to the destination of the unused area indicated by the empty stack PTR (2) (entry to the index number "03101") and written (step 402). Then, as shown in FIG. 11, the network processor 14 moves the entry (index number “0300”
0 ”entry“ 192. X. X. X ″) is invalidated (step 403), and this floor PTR (2)
Is corrected to +1, the index number "03000"
An unused area appears at the position. Accordingly, the index number “03000” of the unused area is stored in the stack memory 11b under the control of the device management processor 12.
Is written and the empty stack PTR (1) is moved to point to this unused area.

Next, the network processor 14 performs the registration operation of FIG. 6 based on the registration program to register the entry “68.128.XX.X” at the position indicated by the index number “03000” in the address table. (Step 301).

Note that the present invention is not limited to this, and FIG.
The block can be reconstructed by the method shown in FIG. That is, the network processor 14
On the basis of this block reconstruction program, for example, the entry “65.128.XX.X” is added to this block 1.
In the case of newly registering an empty stack PTR (1), an empty area index “01FFF” exists immediately before the empty stack PTR (1) as shown in FIG. Index "01FF
F ”) to expand the unused area of block 1, a new entry“ 65.128. X. X "can be registered.

Therefore, the device management processor 12 moves the empty stack PTR (1) upward (index "0").
1FFF ″) to expand the unused area of block 1. The network processor 14 indexes “01FF” indicated by the empty stack PTR (1).
The floor PTR (1) is corrected to -1 based on F ". As a result, the index number pointed to by the floor PTR (1) is located at" 01FFF ", and an unused area appears. 65.128. X.
It becomes possible to write "X" in the position of the index number "01FFF" of the expansion destination.

As described above, in this embodiment, the empty stack PTR is moved upward to expand the unused area of the block, and accordingly, the floor PTR is moved upward to expand the storage area of the block. Therefore, the number of program steps is reduced as compared with the conventional example, and the movement of the entry accompanying the entry registration of the IP address can be suppressed to the minimum, whereby the processing performance of the entire device is not deteriorated and the efficiency is improved. It becomes possible to manage the address table on the CAM.

Further, in this embodiment, since the index of the unused entry of the CAM registered in the stack memory is designated by using the pointer of the empty stack PTR, a plurality of unused entries exist in the CAM. Also, it becomes possible to identify them.

The present invention is not limited to these embodiments, and various modifications can be made without departing from the gist of the present invention.

[0053]

As described above, according to the present invention, an address table divided into a plurality of storage areas is provided, and an input upper layer address is registered as an entry in a predetermined storage area of the storage areas of the address table. In addition to deleting, the index number of the unused entry whose upper layer address is not registered is registered in the registration table, and the index number of the unused entry generated by deleting the entry from the address table is registered in the registration table. When registering or deleting an upper layer address, an entry or an entry can be deleted in an unused area of this address table with a small number of steps, and the movement of the entry due to the registration or deletion of the address entry can be minimized. .

Further, according to the present invention, when the upper layer address is input, an unused entry is detected from the registration table, the upper layer address is registered in this unused entry, and the index of this unused entry is registered from the registration table. Since the number is deleted, the unused area of the address table can be easily specified, and the address entry can be registered and deleted quickly.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing a configuration of an embodiment of an address table management device according to the present invention.

FIG. 2 is a table configuration diagram showing an example of a configuration of a management table shown in FIG.

FIG. 3 is a configuration diagram showing a first example of a configuration of the stack memory shown in FIG.

FIG. 4 is a table configuration diagram showing a first example of the configuration of the address table shown in FIG.

5 is a flowchart for explaining an address registration operation of the device management processor shown in FIG.

6 is a flow chart for explaining a block reconfiguration operation of the network processor shown in FIG. 1. FIG.

FIG. 7 is likewise a flowchart for explaining the address registration operation of the network processor.

8 is a configuration diagram showing a second example of the configuration of the stack memory shown in FIG. 1. FIG.

9 is a table configuration diagram showing a second example of the address table shown in FIG.

FIG. 10 is also a table configuration diagram showing a third example of the address table.

FIG. 11 is also a table configuration diagram showing a change of the third example of the address table.

FIG. 12 is also a table configuration diagram showing a fourth example of the address table.

13 is a configuration diagram showing a third example of the configuration of the stack memory shown in FIG.

FIG. 14 is a configuration diagram showing a configuration of a conventional management table.

FIG. 15 is a flowchart for explaining conventional address registration and block reconfiguration operation.

FIG. 16 is a configuration diagram showing a configuration of a conventional address table.

FIG. 17 is also a configuration diagram showing the configuration of an address table.

FIG. 18 is also a configuration diagram showing a configuration of an address table.

FIG. 19 is also a configuration diagram showing a configuration of an address table.

FIG. 20 is a flow chart for explaining a conventional address deleting operation.

FIG. 21 is a block diagram showing the structure of an address table.

FIG. 22 is a block diagram showing the structure of an address table.

[Explanation of symbols]

0-2 blocks 10 Address table management device 11 General-purpose memory 11a management table 11b Stack memory 12 Device management processor 13 CAM 13a address table 14 Network processor 15 Internal bus PTR pointer

Claims (7)

[Claims] 1. An address table management method for managing an address table, comprising an address table divided into a plurality of storage areas, wherein an upper layer address to be input is a predetermined storage area of the storage areas of the address table. An entry step of registering or deleting an entry in, a first setting step of setting first instruction information for instructing the beginning of a storage area in which the upper layer address is registered in each of the storage areas; A registration step of registering an index number of an unused entry whose upper layer address is not registered in a registration table, and a second instruction information for instructing the head of the unused entry in the registration table. An address table management method including a setting step. 2. In the entry step, when the upper layer address is input, an unused entry in a predetermined storage area is detected based on the second instruction information, and the upper layer address is not detected. While registering in the usage entry,
The head of the storage area in which the upper layer address is registered in the first setting step is designated by the first instruction information, and in the registration step, the index number of the unused entry in which the upper layer address is registered is set. 2. The method according to claim 1, wherein the address is deleted from the registration table, and in the second setting step, the address of the next unused entry registered in the registration table is instructed by the second instruction information. Address table management method. 3. When the entry is deleted, in the entry step, the entry of the corresponding upper layer address registered in the predetermined storage area is deleted, and in the registration step,
3. The address table management method according to claim 1, wherein the index number of an unused entry generated by the deletion is registered in the registration table. 4. The address table management method according to claim 1, wherein the upper layer address is an IP address. 5. An address table management device for managing an address table which is divided into a plurality of storage areas and stores an input upper layer address in a predetermined storage area of the storage areas, wherein the upper layer to the address table is stored. Address table control means for registering an entry of an address and deleting an entry, a registration table for registering an index number of an unused entry in the address table where the upper layer address is not registered, and an unused table for the registration table Registration table control means for registering and deleting the index number of the entry, and a management table for storing first instruction information for instructing the head of the storage area and second instruction information for instructing the index number of the unused entry. , The beginning of the storage area is the first instruction information An address table, comprising: a first instructing means for instructing by means of the second instruction information; and a second instructing means for instructing the index number of an unused entry stored in the registration table by means of the second instruction information. Management device. 6. When the upper layer address is input, the table control means detects an unused entry in the predetermined storage area in which the upper layer address is registered, and the upper layer address is used as the unused entry. The first instruction means causes the top of the predetermined area to be instructed by the first instruction information, and the registration table control means registers an upper layer address in the unused entry. And deleting the index number of the unused entry, and causing the second instruction means to instruct the address of the next unused entry stored in the registration table by the second instruction information. Claim 5
Address table management device described in. 7. When the entry is deleted, the table control means deletes the entry of the corresponding upper layer address registered in a predetermined storage area of the address table, and the registration table control means 7. The address table management device according to claim 5, wherein the index number of an unused entry generated by the deletion is registered in the registration table.