JP2009017439A - Packet transfer device and method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To make speed of forwarding processing fast without using a special memory nor dedicated hardware. <P>SOLUTION: A packet transfer device includes a storage unit which has a plurality of information entries, a field extraction unit which extracts a field associated with forwarding of packets, a cache unit which have a plurality of cache blocks, a cache block specification unit which specifies a cache block, a decision unit which decides whether a cache block includes processing information, and a forwarding unit which reads reference information out of the information entry of the storage unit, performs packet transfer processing on the basis of the read reference information, and stores the reference information and processing information together in a cache block, when it is decided that no processing information is present, and reads processing information out of a cache block and performs packet transfer processing on the basis of the read processing information when it is decided that the processing information is present. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a packet transfer apparatus and a packet transfer method for transferring a packet.

Communication devices such as bridges and routers have a plurality of data input / output interfaces (ports) called a packet. For each packet, these devices search and refer to a large number of databases in the device based on the information attached to the port from which the packet was received and the control information attached to the packet. Determine the processing method. The processing includes operations such as changing or processing packet control information, discarding packets based on the inflow or outflow amount of packets, or sending to specific ports based on database search results. . In these processes, it is necessary to search a large number of databases. When the communication interface becomes high speed, the storage device (memory) in the apparatus storing the database becomes a bottleneck, and the processing speed is limited. The transmission speed is not completely used up. Therefore, in the conventional apparatus, in order to increase the search speed, a special memory called a content addressable memory (CAM) or dedicated hardware for searching a database is used (for example, see Patent Document 1). .
JP 06-261078

  However, when a special memory such as a CAM or dedicated hardware is installed, the cost and power consumption of the device increase, which in turn affects the exhaust heat of the entire device and the size of the housing. In addition, a special memory has a strict limit on the mounting capacity due to the above-described reason, and thus a strict limit is imposed on the capacity of the database of the apparatus. In addition, the search function is limited by special hardware and memory, and there is a problem that the flexibility of the forwarding policy and packet processing processing must be sacrificed.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a packet transfer apparatus that can increase the speed of forwarding processing without using a special memory or dedicated hardware. And

  In order to solve the above problems, a packet transfer apparatus according to an aspect of the present invention relates to a storage unit including a plurality of information entries for storing reference information related to packet transfer processing, and to packet forwarding from the packet. A field extraction unit for extracting a field to be processed, a cache unit including a plurality of cache blocks that collectively store the reference information corresponding to the field related to the forwarding, and a field related to the forwarding extracted by the field extraction unit A cache block specifying unit that specifies the cache block based on the cache block, a determination unit that determines whether or not the processing information exists in the cache block specified by the cache block specifying unit, and the processing by the determination unit Information was determined not to exist In this case, the reference information is read from the information entry of the storage unit based on the field related to the forwarding, the packet is transferred based on the read reference information, and the reference information is collected as the processing information. When the determination unit determines that the processing information is present, the processing information is read from the cache block specified by the cache block specification unit and read. And a forwarding unit that performs transfer processing of the packet based on the processing information. As a result, the cache block identifying unit identifies the cache block based on the field related to forwarding, and the forwarding unit identifies the cache block unit identified by the cache block identifying unit as reference information read from the storage unit when performing packet transfer processing. When the packet forwarding process is performed using the same processing information, the forwarding unit reads the reference information stored in the cache block and performs the packet forwarding process.

  The packet transfer apparatus according to an aspect of the present invention further includes a counter information updating unit that updates counter information, the information entry further stores first counter information, and the cache block further stores second counter information. And the forwarding unit further updates the second counter information when reading the processing information from the cache unit, and the counter updating unit updates the first counter based on the second counter information. The information is updated, and the second counter information is further updated. Thus, the cache block stores the second counter information, the counter information update unit reads the second counter information stored by the cache block, and the second counter information is stored based on the first counter information stored by the information entry unit. Update counter information.

  The packet transfer apparatus according to an aspect of the present invention further includes an aging information update unit that updates aging information, the information entry further stores first aging information, and the cache block further stores second aging information. The forwarding unit further updates the second aging information when reading the processing information from the cache block, and the aging information update unit updates the first aging based on the second aging information. The information is updated, and the second aging information is further updated. Thus, the cache block stores the second aging information, the aging information update unit reads the second aging information stored in the cache block, and the second aging information stored in the information entry unit is stored in the second aging information. Update aging information.

  According to another aspect of the present invention, there is provided a packet transfer method comprising: a storage unit including a plurality of information entries for storing reference information related to packet transfer processing; and the reference information corresponding to a field related to forwarding. As a packet transfer method in an apparatus comprising a plurality of cache blocks for storing, a field extraction step for extracting a field related to packet forwarding from the packet, and the forwarding extracted by the field extraction step A cache block specifying step for specifying the cache block based on a field associated with the cache block; a determining step for determining whether or not the processing information exists in the cache block specified in the cache block specifying step; When it is determined in the determination step that the processing information does not exist, the reference information is read from the information entry of the storage unit based on the field related to the forwarding, and the packet is transferred based on the read reference information Perform the processing, store the reference information as the processing information in the cache block specified in the cache block specifying step, and determine that the processing information exists in the determining step, the cache block specifying step A forwarding step of reading the processing information from the identified cache block and performing a transfer process of the packet based on the read processing information.

  The packet transfer method according to an aspect of the present invention further includes a counter information update step for updating counter information, wherein the information entry further stores first counter information, and the cache block further stores second counter information. Storing, and the forwarding step further updates the second counter information when the processing information is read from the cache unit, and the counter updating step is configured to update the first counter based on the second counter information. The information is updated, and the second counter information is further updated.

  The packet transfer method according to an aspect of the present invention further includes an aging information update step for updating aging information, the information entry further stores first aging information, and the cache block further stores second aging information. Storing, and the forwarding step further updates the second aging information when reading the processing information from the cache block, and the aging information updating step is based on the second aging information. The aging information is updated, and the second aging information is updated.

  An object of the present invention is to provide a packet transfer apparatus capable of increasing the speed of packet transfer processing without using a special memory or dedicated hardware.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a switch device 1 (packet transfer device) according to an embodiment of the present invention. The switch device 1 includes a control card device 2, input / output line card devices 3-1 to 3-3, forwarding processing devices 4-1 to 4-3, and a switch unit 6. The control card device 2 controls the entire switch device 1. The forwarding processing device 4-1 includes a packet processing unit 5-1, the forwarding processing device 4-2 includes a packet processing unit 5-2, and the forwarding processing device 4-3 includes a packet processing unit 5-3. The packet processing units 5-1 to 5-3 are connected to the switch unit 6, and packets can be transmitted and received between the packet processing units 5-1 to 5-3 via the switch unit 6. The packet processing unit 5-1 is connected to the input / output line card device 3-1, the packet processing unit 5-2 is connected to the input / output line card device 3-2, and the packet processing unit 5-3 is connected to the input / output line card device 3-1. 3-3. The packet processing units 5-1 to 5-3 perform transfer processing of packets received from the input / output line card device 3. Each of the input / output line card devices 3-1 to 3-3 includes three ports, and transmits and receives packets to and from an external device (not shown) via the ports.

  FIG. 2 is a functional block diagram showing the configuration of the packet transfer apparatus of this embodiment. The packet transfer apparatus 1 includes an input / output port 3, a field extraction unit 11, an index calculation unit 12 (cache block specifying unit), a verification information storage unit 13, a verification unit 14, a forwarding unit 17, and a cache unit 200. And database 1 (521-1) to database n (521-n) (storage unit). The forwarding unit 17 includes a database reference forwarding unit 15 and a cache reference forwarding unit 16. The cache unit 200 includes a cache block 1 (210-1) to a cache block t (210-t).

  In the illustrated example, there are n databases, database 1 (521-1) to database n (521-n). Database 1 (521-1) to database n (521-n) are stored in a semiconductor memory (RAM) that is a main storage device that can be directly read and written by the CPU. Database 1 (521-1) to database n (521-n) store reference information that is information necessary for packet transfer processing. The types of the database 1 (521-1) to the database n (521-n) include a port database for storing information about ports, a forwarding database (Forwarding DataBase, FDB) for storing Ethernet (registered trademark) addresses, a virtual database A virtual local area network table that stores information of a local local area network (VLAN), and a port virtual that stores information searched using ports and virtual local area networks as keys. • Quality of service (Quality of Se) that stores information on the service level of the local area network table and packet transfer vice, QoS) parameters, and the like. Database 1 (521-1) to database n (521-n) have a plurality of entries.

  The field extraction unit 11 extracts a field related to forwarding included in the transfer target packet received via the input / output port 3. A field related to forwarding is included in a part (header) of a packet, and is a part of control information including a source address, a destination address, quality of service (QoS), and the like. The index calculation unit 12 calculates a hash value of a field related to forwarding extracted by the field extraction unit 11, calculates an index based on the calculated hash value, and the cache block 1 (210 that the cache unit 200 includes based on the index -1) to one of the cache blocks t (210-t) is specified. The verification information storage unit 13 uses the field related to forwarding extracted by the field extraction unit 11 as verification information, and the index calculation unit 12 identifies the verification information based on the field as a cache block 1 (210-1). Store in cache block t (210-t). The verification unit 14 (determination unit) relates to the forwarding of the packet to the cache block 1 (210-1) to the cache block t (210-t) specified based on the field related to the forwarding of the packet to be transferred. It is determined whether or not the same verification information as the field to be checked (verification information) is stored. Since packet transfer is performed based on fields related to forwarding, when the verification information is the same, the packet transfer process is also the same.

  In general, router and bridge processing has a feature that only control information included in a part of a packet affects transfer processing. Therefore, if only a portion that affects packet transfer is recorded as a feature of the packet, , Can sort out the same kind of packets. The same type of packet refers to a packet having the same transfer process. When processing the same type of packet for the second time or later, the same processing as the first processing may be performed. Therefore, when processing and outputting the packet and the means for confirming that it has the same kind of characteristics, all the information necessary for the transfer of the packet read from the database is stored in one cache. If the hash function can be used to search at high speed, the transfer process will be much faster.

  The forwarding unit 17 processes the packet and transfers the packet. The forwarding unit 17 includes a database reference forwarding unit 15 and a cache reference forwarding unit 16. The packet processing and the bucket transfer are performed in the same manner, but the reading destination of information necessary for the processing and transfer is different. The database reference forwarding unit 15 reads information necessary for processing and transfer from the database 1 (521-1) to the database n (521-n). Further, the database reference forwarding unit 15 writes the read information into the cache block 1 (210-1) to the cache block t (210-t) specified based on the field of the packet. On the other hand, in the cache reference forwarding unit 16, the database reference forwarding unit 15 reads from the database 1 (521-1) to the database n (521-n) and the cache block 1 (210-1) to the cache block t (210-t). Is read from the cache block 1 (210-1) to the cache block t (210-t) to process the packet and transfer the packet. That is, the data once read by the forwarding unit 17 from the database 1 (521-1) to the database n (521-n) is written in the cache block 1 (210-1) to the cache block t (210-t). When the same transfer process is performed on a packet having the same type of characteristics as a packet that has been previously transferred, data is read from the cache block 1 (210-1) to cache block t (210-t) and the transfer process is performed. Do. The forwarding unit 17 relates to the forwarding of the packet to the cache block 1 (210-1) to the cache block t (210-t) specified by the verification unit 14 based on the field related to forwarding of the packet to be transferred. When it is determined that the same verification information as the field (verification information) to be stored is stored, the cache reference forwarding unit 16 is used. When it is determined that the field is not stored, the database reference forwarding unit 15 is used.

  The cache unit 200 includes a cache block 1 (210-1) to a cache block t (210-t) and is stored on a semiconductor memory (RAM). This semiconductor memory is not a special memory such as CAM, but may be a semiconductor memory similar to the semiconductor memory storing the database 1 (521-1) to the database n (521-n). The cache block 1 (210-1) to the cache block t (210-t) are areas that can store data and can be read continuously by the forwarding unit 17, respectively.

  FIG. 3 is a block diagram illustrating the operation of the database reference forwarding unit in the present embodiment. As illustrated, the packet transfer apparatus 1 includes an input / output port 3, a processing unit 60, a database 1 (521-1) to a database n (521-n), and a cache unit 200. The processing unit 60 includes the field extraction unit 11, the index calculation unit 12, the verification information storage unit 13, the verification unit 14, and the forwarding unit 17 illustrated in FIG. The forwarding unit 17 includes a database reference forwarding unit 15 and a cache reference forwarding unit 16. The reception packet 20 and the transmission packet 21 are packets to be transferred, and are processed and transferred by the packet transfer apparatus 1.

  In the illustrated example, the forwarding unit 17 included in the processing unit 60 performs transfer processing using the database reference forwarding unit 15. When the transfer process is performed using the database reference forwarding unit 15, the verification unit 14 identifies the cache block 1 (210-1) to the cache block t (210 −) identified based on the field related to the forwarding of the packet to be transferred. This is a case where it is determined that the same verification information as the field (verification information) related to forwarding of the packet is not stored in t). That is, since the reference information is not stored in the cache block 1 (210-1) to the cache block t (210-t), the reference information is read from the database 1 (521-1) to the database n (521-n), The packet transfer process is performed, and the read reference information is stored in the cache block 1 (210-1) to the cache block t (210-t) specified based on the field related to the forwarding of the packet to be transferred.

  FIG. 4 is a block diagram illustrating the operation of the cache reference forwarding unit in this embodiment. As illustrated, the packet transfer apparatus 1 includes an input / output port 3, a processing unit 60, a database 1 (521-1) to a database n (521-n), and a cache unit 200. The processing unit 60 includes the field extraction unit 11, the index calculation unit 12, the verification information storage unit 13, the verification unit 14, and the forwarding unit 17 illustrated in FIG. The forwarding unit 17 includes a database reference forwarding unit 15 and a cache reference forwarding unit 16. The reception packet 20 and the transmission packet 21 are packets to be transferred, and are processed and transferred by the packet transfer apparatus 1.

  In the illustrated example, the forwarding unit 17 included in the processing unit 60 performs a transfer process using the cache reference forwarding unit 16. When performing the transfer process using the cache reference forwarding unit 16, the verification unit 14 identifies the cache block 1 (210-1) to the cache block t (210-) specified based on the field related to the forwarding of the packet to be transferred. This is a case where it is determined that the same verification information as the field (verification information) related to the forwarding of the packet is stored in t). That is, since the reference information is stored in the cache block 1 (210-1) to the cache block t (210-t), the reference information is obtained from the cache block 1 (210-1) to the cache block t (210-t). Read and transfer packets.

  FIG. 5 illustrates reference information stored in the database 1 (521-1) to the database n (521-n) according to the embodiment of the present invention, and the cache block 1 (210-1) to the cache block t (210-) on the cache. It is the block diagram which showed the relationship with the process information which t) memorize | stores. The cache block 1 (210-1) to the cache block t / 2 are source address cache lines. Cache block (t / 2) +1 to cache block t (210-t) are destination address cache lines. Note that t is an even number.

  Database 1 (521-1) stores reference information 30-1 and 30-2. Database 2 (521-2) stores reference information 30-3 and 30-4. The database n (521-n) stores reference information 30-5 and 30-6. The reference information 30-1, 30-4, and 30-5 are reference information that is referred to when the source address is processed in the transfer process. The reference information 30-2, 30-3, and 30-6 are reference information that is referred to when the destination address is processed in the transfer process.

  When the reference information 30 stored in the database 1 (521-1) to the database n (521-n) is read once by the database reference forwarding unit 15, one cache block is provided for each reference information used for transferring one packet. 1 (210-1) to cache block t (210-t). In the illustrated example, the reference information 30-1, 30-4, and 30-5 are reference information that is referred to when processing the source address in the transfer processing of one packet, and therefore, t cache blocks 1 ( 210-1) to cache block 4 (210-4) which is one of the cache blocks t (210-t). The reference information 30-2, 30-3, and 30-6 are reference information that is referred to when processing the destination address in the transfer processing of one packet, and therefore, t cache blocks 1 (210- 1) to cache block t-1 (210-t-1), which is one of the cache blocks t (210-t).

  Next, the operation procedure of the packet transfer apparatus will be described with reference to FIG. 6 and FIG. 6 and 7 are flowcharts showing the operation procedure of the packet transfer apparatus. First, the field extraction unit 11 extracts a field related to forwarding from a packet input from the input / output port 3 (step S101). The index calculation unit 12 calculates a hash value (1) from the field values extracted in step S101 using a predetermined hash function (step S102). The index calculation unit 12 calculates an index based on the hash value (1) calculated in step S102, and identifies cache block 1 (210-1) to cache block t (210-t) based on the index. The verification information storage unit 13 searches whether or not verification information exists in the cache block 1 (210-1) to the cache block t (210-t) specified by the index calculation unit 12 (step S103). The verification information storage unit 13 determines whether or not the verification information exists in the cache block 1 (210-1) to the cache block t (210-t) specified in step S103 (step S104), and the verification information (2) is determined. When it exists, it progresses to step S105, and when it does not exist, it progresses to step S108.

  In step S105, the verification unit 14 executes cache block 1 (210-1) to cache block including the verification information searched based on the verification information existing in step S104 and the field (verification information) extracted in step S102. It is confirmed whether or not the information of t (210-t) is valid for the transfer target packet (step S105). If it is determined in step S105 that the information of the cache block 1 (210-1) to the cache block t (210-t) is valid, the process proceeds to step S107, and if it is determined to be invalid, the process proceeds to step S108 (step S106). In step S107, the cache reference forwarding unit 16 performs transfer based on the processing information (3) among the information included in the cache block 1 (210-1) to the cache block t (210-t) specified in step S103. The packet to be transferred is controlled to the output port recorded in the processing information (3) using the parameters recorded in the processing information (3) (step S107), and the processing is terminated.

  On the other hand, in step S108, the verification information storage unit 13 secures cache blocks 1 (210-1) to t (210-t), which are new cache blocks (4) (step S108). The database reference forwarding unit 15 analyzes the header part of the packet to be transferred, reads the reference information from the database 1 (521-1) to the database n (521-n) based on the analyzed information, and based on the reference information The packet is processed, and the processed packet is sent to the output port as a transmission packet 21. Further, the database reference forwarding unit 15 collects a plurality of pieces of reference information read in this process into one and stores them as one piece of processing information in the cache block (4) secured in step S108 (step S109). The database reference forwarding unit 15 registers the cache block (4) in which the processing information is stored in step S109 with the index calculated in step S103 based on the hash value (1) calculated in step S102 (step S110). The process ends.

  As described above, the forwarding unit 17 reads a plurality of reference information necessary for packet transfer from the database 1 (521-1) to the database n (521-n) for the packet to be transferred for the first time, and based on the read information. The packet is transferred to the cache block, and the reference information read at that time is combined into one process and stored in the cache block as a single process information. Transfer processing is performed based on the processing information stored in the cache block.

  The database and the cache block are stored on the RAM and exist in the same address space that can be directly accessed by the CPU at the same access speed. However, each cache block is stored on the RAM so that the addresses are continuous. When reading the same content, consecutive reads from one cache block are faster than reads from multiple databases. This is due to the following factors.

When a CPU having a CPU internal cache reads data used for the first time from the RAM in performing packet transfer processing, the data specified by the address adjacent to the address of the data is read in units of the line size of the CPU internal cache. Collectively store in the CPU internal cache. In this embodiment, when data necessary for packet transfer processing is read from a cache block, the target data is accumulated within a predetermined range on the RAM (for example, within a range corresponding to the line size of the CPU internal cache). Therefore, there is a high probability that the next data to be used is stored in the CPU internal cache together with the first data to be used. Therefore, when the data required for packet transfer processing is not recorded in the area designated by the continuous addresses on the RAM, that is, compared with the case where data is read from a plurality of databases with distributed addresses, one cache is used. Reading data from the block is faster.
If the line size of the CPU internal cache matches the size of the cache block, reading is further accelerated. For example, the CPU internal cache has a line size of 128 bytes, the cache block size is 128 bytes, and the cache block is arranged so that one cache block fits within a predetermined boundary on the address. Since all the data of one cache block is stored in the CPU internal cache, the reading speed is further increased.

  Also, data stored in an area designated by consecutive addresses on the RAM can be transferred at high speed by burst transfer. In burst transfer, the CPU first transmits read address information to the RAM only once. Thereafter, data near the transmitted address is continuously transferred from the RAM to the CPU. Therefore, in comparison with the method in which address information is transmitted once for each data transfer, the time required for transmitting address information can be significantly reduced in burst transfer. Therefore, when the CPU continuously reads data stored at consecutive addresses from the RAM, that is, data stored in one cache block, burst transfer is effective, so it is stored at non-contiguous addresses. The reference information can be read faster than the case where the read data, that is, the data existing in a plurality of databases is read.

  As described above, when packet transfer processing using the present invention is compared with packet transfer processing not using the packet transfer processing using the present invention, reference data can be read at high speed. As a result, the reading of reference information, which has conventionally been a bottleneck of packet transfer processing, is accelerated, and the packet transfer processing is also accelerated.

  Next, a management method of counters included in the entries of the database 1 (521-1) to the database n (521-n) in the packet transfer apparatus described above will be described with reference to the drawings. FIG. 8 is a block diagram illustrating a counter management method in the present embodiment. The packet transfer apparatus described above has a counter information update unit described below as means for managing the counters of the entries in the database 1 (521-1) to the database n (521-n).

In the packet forwarding process, it is necessary not only to refer to the database 1 (521-1) to the database n (521-n) but also to record statistical information regarding the forwarded packet. The statistical information (counter) is any of the database 1 (521-1) to the database n (521-n) referred to when the database 1 (521-1) to the database n (521-n) are referred to in the forwarding process. Is recorded in the entry. There are a plurality of entries in the database 1 (521-1) to the database n (521-n). In the illustrated example, the number of entries in the database 1 (521-1) is m _{1 and the} number of entries in the database 2 (521-2) The number of entries is m ₂ . Each entry has a counter (first statistical information). However, in this embodiment, when the reference information is included in the processing information and stored in the cache block 1 (210-1) to the cache block t (210-t), the forwarding process is performed in the cache block 1 (210 -1) to the cache block t (210-t), the forwarding process is performed without accessing the entries of the database 1 (521-1) to the database n (521-n). Therefore, statistical information cannot be recorded in the entries of the database 1 (521-1) to the database n (521-n) unless the counter management method is taken into consideration.

  The counter management method in the present invention is as follows. Each of the cache block 1 (210-1) to the cache block t (210-t) has a counter (second statistical information). When the packet reference forwarding unit 16 performs the packet forwarding process based on the information of the cache block 1 (210-1) to the cache block t (210-t), the cache reference forwarding unit 16 accesses the cache block 1 (210-1) to the cache The counter of block t (210-t) is counted up. In the illustrated example, when the cache reference forwarding unit 16 performs the forwarding process of the packet A, the processing information of the cache block 1 is read. At that time, the cache reference forwarding unit 16 counts up the counter of the referenced cache block 1 (210-1). The same applies to the forwarding process for packet B.

  On the other hand, the counter information update unit reads the second statistical information of the cache block 1 (210-1) to the cache block t (210-t) by the periodic process, and the cache block 1 (210-1) to the cache block t (210). -T) stores the reference information included in the processing information stored therein, the first statistical information of the entries of the database 1 (521-1) to the database n (521-n) stores the cache block 1 (210-1). ) To the second statistical information of the cache block t (210-t), and then the second statistical information of the cache block 1 (210-1) to the cache block t (210-t) is cleared. The same processing is performed when cache block 1 (210-1) to cache block t (210-t) are deleted, and cache block 1 (210-1) to cache block t (210-t) The second statistical information to be stored is added to the first statistical information of the entry.

  As described above, according to the present embodiment, even when the forwarding process is performed without accessing the entries of the database 1 (521-1) to the database n (521-n), the database 1 (521-1). ~ Statistical information can be recorded in an entry of database n (521-n).

  Next, a method for updating the aging information (first aging information, first valid time) of each entry of the database 1 (521-1) to the database n (521-n) in the packet transfer apparatus described above will be described. The description will be given with reference. FIG. 9 is a block diagram illustrating an aging processing method according to this embodiment. The packet transfer apparatus described above has an aging information update unit described below as means for managing the validity of entries in the database 1 (521-1) to the database n (521-n). Each of the cache block 1 (210-1) to the cache block t (210-t) has second aging information.

  The packet transfer apparatus may manage the validity of entries of database 1 (521-1) to database n (521-n) that are dynamically collected by a process called aging. In this process, when it is confirmed that the entry of the specific database 1 (521-1) to the database n (521-n) is valid by the packet during the packet transfer process, the confirmed time is set to the database 1 (521-1) to database n (521-n) are recorded in the entries, and when it is not confirmed that they are valid within a predetermined time, the database 1 (521-1) to database n (521-n) This process automatically deletes the entry.

  However, in this embodiment, when the reference information is included in the processing information and stored in the cache block 1 (210-1) to the cache block t (210-t), the forwarding process is performed in the cache block 1 (210 -1) to the cache block t (210-t), the forwarding process is performed without accessing the entries of the database 1 (521-1) to the database n (521-n). For this reason, even when it is confirmed to be valid, the confirmed time cannot be recorded in the entries of the database 1 (521-1) to the database n (521-n). -1) to database n (521-n) entries are automatically deleted.

  The aging process in the present invention is as follows. When the cache reference forwarding unit 16 performs the packet forwarding process based on the information of the cache block 1 (210-1) to the cache block t (210-t), the cache reference forwarding unit 16 accesses the cache block 1 (210 -1) to the second valid time (second aging information) of the cache block t (210-t), the time referring to the cache block is recorded. In the illustrated example, when the cache reference forwarding unit 16 performs the forwarding process for the packet A, the cache reference forwarding unit 16 reads the second processing information of the cache block 1 (210-1). At that time, the cache reference forwarding unit 16 records the current time acquired from the internal clock when referring to the cache block 1 at the second valid time of the cache block 1 (210-1). Regarding the forwarding process for packet B, the cache reference forwarding unit 16 performs the same process as for packet A.

  On the other hand, the aging information update unit reads the second valid time of the cache block 1 (210-1) by the periodic process, and the first valid time and the entries related to the cache block 1 (210-1) have the first Compare the effective time of. If the second valid time is newer, the aging information update unit rewrites the first valid time with the value of the second valid time. Thereafter, the aging information update unit clears the second valid time of the cache block 1 (210-1). For the cache block 2 (210-2) to the cache block t (210-t), the aging information update unit performs the same processing as that for the cache block 1.

  As described above, according to the present embodiment, even when the forwarding process is performed without accessing the entries of the database 1 (521-1) to the database n (521-n), the database 1 (521-1). ~ Aging processing of database n (521-n) can be performed.

  Next, a technique for managing and maintaining information on database entries and cache entries in the packet transfer apparatus described above will be described. The packet transfer apparatus described above has an information management apparatus described below as means for managing database entries and cache entries.

  FIG. 10 is a schematic block diagram illustrating a hardware configuration of the information management apparatus according to the present embodiment. As shown in the figure, the information management apparatus 501 includes a CPU (Central Processing Unit) 502, a semiconductor RAM (Read / Write Random Access Memory comprised of a semiconductor) 503, and a bus 504. The The CPU 502 and the semiconductor RAM 503 are respectively connected to the bus 504, and the CPU 502 reads data from the semiconductor RAM 503 via the bus 504 and writes data to the semiconductor RAM 503. Can be done. Although other components are also connected to the bus 504, description thereof is omitted here. The semiconductor RAM 503 includes an area in which execution-type computer program code is stored and an area in which data to be processed is stored. The CPU 502 reads out and executes the program code from a predetermined address of the semiconductor RAM 503 as appropriate based on the value of the program counter included therein. By using such a computer program, the information management function described below is realized.

  FIG. 11 is a schematic functional block diagram showing a functional configuration of the information management apparatus 501. As illustrated, the information management apparatus 501 includes a relevance validation processing unit 511, a relevance invalidation processing unit 512, a garbage collection processing unit 513, and a storage unit 514. The storage unit 514 has a function of storing data, and is realized by the semiconductor RAM 503 described above. The relevance validation processing unit 511, the relevance invalidation processing unit 512, and the garbage collection processing unit 513 are realized by the CPU 502 executing the computer program.

The relevance validation processing unit 511 (relevance validation process), when validating a cache block (related information entry) related to a database entry (information entry), the database entry (information entry) and the cache An object (related object) including a cache block pointer (relevance information) indicating that there is a relationship with a block (related information entry) is generated, and the generation number (522) of the cache block (related information entry) −1, generation information) has a function of performing the process of writing the same generation information as the generation number (527-1, generation information) of the object (related object).
The relevance invalidation processing unit 512 (relevance invalidation processing step), when any of the database entries (information entries) is changed, the cache block (relevance) related to the changed database entry (information entry) The information entry) has a function of invalidating and updating the generation number (522-1, generation information) of the cache block (related information entry).
The garbage collection processing unit 513 (garbage collection process) has a generation number (527-1, generation information) of an object (related object) and a cache block (related information entry) corresponding to the object (related object). It has a function of comparing the generation number (522-1, generation information) and collecting the object (related object) according to the comparison result (that is, collecting (collecting) unnecessary objects). is there.

Next, the configuration and structure of data to be managed by the information management apparatus 501 will be described. FIG. 12 is a schematic diagram conceptually showing an example of a data structure managed by the information management apparatus 501. This figure merely conceptually represents the data structure, and the actual physical data structure in the information management apparatus 501 of this embodiment will be described later. In FIG. 12, reference numerals 521-1, 521-2, ..., 521-n denote n databases (first storage units). Reference numeral 522 denotes a cache block group (second storage unit). Database 1 (521-1) has m ₁ data entries (information entries) from entry 1 to entry m ₁ . The database 2 (521-2) has m ₂ data entries from entry 1 to entry m ₂ . In the same manner, database n (521-n) has _mn data entries from entry 1 to entry _mn . On the other hand, the cache block group 522 has t cache blocks (related information entries) from the cache block 1 to the cache block t. Each arrow line in the figure represents a relation from a database entry to a cache block. In the illustrated example, for example, entry 2 of database 1 (521-1) is associated with cache block 2, cache block 3, and cache block t. Also, entry 2 of database 2 (521-2) is associated with cache block 2. The entry m ₂ in the database 2 (521-2) is related to the cache block 1. In addition, entry 2 of database n (521-n) relates to cache block t. Further, the entry m _n of the database n (521-n) is related to the cache block 3.

As in the example shown in FIG. 12, a database entry may be associated with a plurality of cache blocks. Also, multiple database entries may be associated with one cache block. That is, the relationship between the database entry and the cache block is a many-to-many relationship (in the example shown, (m ₁ + m ₂ +... + M _n ) vs. t).

Incidentally, as described above, in the present embodiment, the database (521-1 to 521-n) holds various data that need to be referred to when the packet transfer apparatus performs packet transfer. In addition, if the information necessary to transfer a packet is scattered and present in each database, it takes time to read the data, so each cache block transfers a packet. This is to keep all the information necessary at the time in a local place.
That is, when the packet transfer apparatus is operated, the database entry may be changed as a result of a setting operation by an operator, as a result of exchange of a routing protocol, or as a result of FDB learning of a bridge.

  When a database entry is changed, the cache block that holds the old value corresponding to the database entry is not referenced, such as deleted or invalidated, in order to avoid inconsistent values. It is necessary to do so. As described above, a certain cache block includes information extracted from a plurality of database entries. As described above, a certain database entry is associated with a plurality of cache blocks. In other words, it depends on a certain cache block and a plurality of database entries. That is, there is a many-to-many dependency between database entries and cache blocks.

  Next, a specific structure of data managed by the information management apparatus 501 will be described with reference to FIGS. 13, 14, and 15. FIG.

FIG. 13 is a schematic diagram showing a data structure representing an association between a database and a cache block. In this figure, database 1 (521-1, first storage unit) has m ₁ entries (information entries), and cache block group 522 (second storage unit) has t entries (related information entries). have. Reference numeral 526 denotes an object hash, and this object hash 526 has x slots from slot 1 to slot x. The entry of database 1 (521-1) is associated with the slot of object hash 526. Various methods can be considered as this association method. For example, based on values specific to the entry of the database 1 (521-1) (such as an address where the entry exists and a key value of data of the entry). There is a method of associating with any slot from slot 1 to slot x by calculating a predetermined function (such as a hash function). In addition, when a hash function is used, hash values corresponding to a plurality of entries in the database 1 (521-1) may be the same. To solve this, for example, a single hash value is used. On the other hand, there is a method of assigning a plurality of slots and using them appropriately.

  Reference numeral 527 denotes an object (related object), and this object 527 is a structure for associating one slot with a plurality of cache blocks. The object 527 is stored in an object storage unit (related object storage unit) on the memory. Each slot in the object hash 526 has a pointer to one object 527. One object 527 has a pointer to one cache block and a pointer to the next one object 527. That is, the pointer of one slot points to the head of a list composed of a plurality of objects 527. In the object 527 at the end of this list, the pointer to the next object is set to “null”. Each object 527 belonging to this list points to one cache block. That is, the association from one slot to a plurality of cache blocks is performed.

  FIG. 14 is a schematic diagram showing an internal data structure of the object 527. As illustrated, the object 527 includes a generation number 527-1 (generation information indicating a generation corresponding to the relevance information), a cache block pointer 527-2 (relevance information), and a next object pointer 527-3. It is comprised including. The generation number 527-1 is for managing the generation of this object 527 and the update of the cache block pointed to by this object 527. The relevance validation processing unit 511 (FIG. 11) or the relevance invalidation process Updated by the unit 512 (FIG. 11). Details of how to use the generation number 527-1 will be described later. The cache block pointer 527-2 is a pointer for pointing to one cache block as described above. That is, the cache block pointer 527-2 represents the association between the database entry and the cache block. As described above, the next object pointer 527-3 is a pointer for pointing to the next object 527 on the link list.

  FIG. 15 is a schematic diagram showing the internal data structure of one cache block. As shown in the figure, the cache block includes a generation number 522-1 (generation information indicating the generation corresponding to the related information entry), valid / invalid 522-2, verification information 522-3, and processing information 522-4. It is comprised including. The generation number 522-1 is for managing the update generation of the cache block, and is used together with the above-mentioned generation number 527-1. Details of how to use the generation number 522-1 will be described later. The valid / invalid 522-2 is a flag indicating whether or not the cache block is an entry that currently has valid information. The value of the flag may be determined as appropriate by design. For example, “1” represents valid and “0” represents invalid. For example, the verification information 522-3 stores a key value (may be a composite key value of a plurality of databases) corresponding to the cache block. The verification information 522-3 is used for verifying the key value when referring to the cache block. The processing information 522-4 is information corresponding to the key value, and is information that is referred to when the packet transfer apparatus performs a process of transferring a packet corresponding to the key value. This processing information 522-4 is for holding information distributed in a plurality of databases (521-1, 521-2,..., 521-n) in one place so that the information can be referred to at high speed. It is an area.

  Next, processing using the data structure described above will be described with reference to FIG. 16, FIG. 17, and FIG.

FIG. 16 is a flowchart showing a procedure of processing in which the association validation processing unit 511 (FIG. 11) of the information management apparatus 501 registers the cache blocks corresponding to the database entries in association with each other. That is, it is a flowchart showing a procedure of processing for registering a dependency relationship. At this time, for the cache block to be associated from the database entry, the information management apparatus 501 stores appropriate data in the verification information 522-3, stores appropriate data in the processing information 522-4, and is enabled / disabled. The process of setting the flag 522-2 to indicate “valid” and storing an appropriate generation number in the generation number 522-1 is appropriately performed. Here, for the generation number, for example, a numerical value that is incremented every time one cache block is validated or invalidated is used.
An example of processing for searching the database and recording the verification information and the processing information in the cache block is as shown in the flowcharts of FIGS. 6 and 7 (particularly, step S109).

According to the flowchart of FIG. 16, the relevance validation processing unit 511 first uses the address value on the memory of the entry as a value unique to the entry of the database to be registered in step S701. A hash function is calculated based on the obtained hash value, and a specific slot to be used is determined (that is, a slot is calculated).
Next, in step S <b> 702, the relevance validation processing unit 511 generates one object 527 that is a structure for retaining the dependency relationship, that is, for retaining the association information between the database entry and the cache block. To do. That is, an area on the memory for one object 527 is secured.

Next, in step S703, the relevancy validation processing unit 511 uses the generation number value stored in the generation number 522-1 of the cache block to be associated as the generation number 527-1 of the object 527 generated above. Store in the area. As a result, these objects 527 and the corresponding cache block hold the same generation number.
Next, in step S704, the relevance validation processing unit 511 inserts the object 527 generated in step S702 into the slot calculated in step S701. That is, the object 527 generated in step S702 is inserted at the beginning or the end of the link list composed of the plurality of objects 527 indicated by the slot calculated in step S701. This is done by updating the object pointer 527-3 next to the object 527 on this link list. If the link list pointed to by the slot is originally null (no object is present), the link list consisting only of the object 527 generated in step S702 may be pointed to by the slot. Then, the relevance validation processing unit stores the address of the corresponding cache block in the cache block pointer 527-2 of the object 527 generated in step S702.
Through the series of processes described above, the association between the database entry and the corresponding cache block is registered.

  The information management apparatus 501 changes the database entry used to generate the cache block verification information 522-3 and the processing information 522-4, that is, when the entry associated with the cache block is changed or deleted. Performs invalidation of the (corresponding) cache block related to the changed or deleted database entry based on the registered dependency (association information).

  FIG. 17 is a flowchart showing a procedure of the above-described processing for invalidating a cache block. Describing along this flowchart, the relevance invalidation processing unit 512 (FIG. 11) determines a value (for example, an address value on the memory of the entry) unique to the changed (or deleted) database entry in step S711. ) Based on the hash function, and a slot is specified based on the obtained hash value (that is, the slot is calculated). The slot specified here should be the same as the slot determined in step S701 in the flowchart (relevance validation processing) in FIG.

  Next, in step S712, the relevancy invalidation processing unit 512 follows the link list of the object 527 pointed to by the slot specified in step S711, and the cache block pointer 527-2 for each of all the linked objects 527. Is invalidated (that is, the valid / invalid 522-2 flag of the cache block is set to a value representing “invalid”). Then, the generation number 522-1 of the cache block is updated (for example, incremented). Then, all objects included in the link list of the object 527 pointed to by the identified slot are collected. Here, collecting the object means that the area of the object is released and the value of the pointer to the linked list associated with the specified slot is set to “null”.

  As a result of the above-described processing by the relevance invalidation processing unit 512 (steps S711 and S712), in response to the change of a specific database entry, it is succeeded by a slot calculated from a value unique to the changed entry. Following all objects 527, the corresponding cache block could be invalidated. However, the database entry and the cache correspond many-to-many, and the cache block invalidated by the above processing may remain in a state where the object 527 corresponding to the other database entry still points.

  If such a state is left unattended, the object 527 that is not collected occupies the memory area, which causes a problem that the memory area is exhausted. If the above state is left unattended, it is not until the other database entry refers to the cache block valid / invalid 522-2 area or the verification information 522-3 area via the object 527. Since it can be seen that the cache block is invalid, there is a problem that the process of tracing the pointer is wasted.

  Therefore, the garbage collection processing unit 513 (FIG. 11) of the information management apparatus 501 checks the cache of all the objects in the object hash 526 at a predetermined timing (for example, periodically), and has already been invalidated. A process of collecting an object 527 (garbage, garbage, dust data) pointing to a block is performed. Whether or not an object 527 is garbage, that is, whether or not the object 527 indicates a cache block that has already been deleted, is compared with the generation number 522-1 in the cache block and the generation number 527-1 in the object 527. You can do that. If the generation numbers of the two are different, the cache block has already been invalidated or has been invalidated and then revalidated for other data. Collect as being garbage. If the two generation numbers are the same, the cache block is in a valid state, so such an object 527 is not a collection target.

  FIG. 18 is a schematic data structure diagram for explaining a processing example in which the garbage collection processing unit 513 collects an object 527 pointing to an invalid cache block. In the example shown, entry 2 of database 1 (521-1) is changed. Accompanying this change processing, the relevance invalidation processing unit 512 (FIG. 11) uses the hash function to determine the index value of the slot based on the information unique to the entry 2 (address of the entry in memory). Calculate Then, the slot indicated by the index value is specified (step S711 in FIG. 17). In the illustrated example, slot 3 in the object hash 526 is a specified slot. Then, the relevance invalidation processing unit 512 follows the list of the objects 527 connected to the slot 3 to delete (collect) the object (B) and invalidate the corresponding cache block 2. (C) is deleted (collected) and the corresponding cache block 1 is invalidated. At this time, the invalidated generation numbers of the cache blocks 2 and 1 are updated (for example, incremented) (step S712 in FIG. 17).

  As described above, since the dependency (association) between the database entry and the cache block is many-to-many, even when the cache blocks 2 and 1 become invalid, in this state, the object (pointing to the cache block 2 ( A) remains uncollected.

Here, the garbage collection unit 513 inspects all the objects 527 connected to the slots from all the slots included in the object hash 526 in a predetermined cycle. As a result of the inspection, all objects whose cache block generation number 522-1 and object generation number 527-1 do not match are collected. In the illustrated example, the garbage collection unit 513 collects the object (A). Before the object (A) is collected, the pointer associated with the slot 1 stores the pointer value to the object (A). However, the garbage collection unit 513 collects the object (A). The value of the pointer to the next object of the object (A) is recorded again in the pointer associated with the slot 1.
As described above, since the generation number is used for management, even if the cache block 1 and the cache block 2 are in a valid state again before the garbage collection unit 513 is run, only correct and unnecessary objects are collected. be able to.

  The garbage collection process may be executed at a predetermined timing as appropriate, for example, at a predetermined cycle. For example, a monitoring unit for monitoring the free memory capacity is provided, and the monitoring result of the free memory capacity is provided. (For example, when the free memory capacity falls below a predetermined threshold), the garbage collection process may be executed. Further, for example, the monitoring unit may monitor the CPU load and execute the garbage collection process in a time zone when the CPU load is low.

  In the above, the case where the relationship between the database entry and the cache block is many-to-many has been described. However, the present embodiment can also be effectively applied to data in which this is many-to-one. In the above description, the number of databases is n. However, n may be an integer of 1 or more. That is, even if the number of databases is 1, this embodiment can be applied effectively. The number of entries in each database is arbitrary, and the number of entries in each database may be variable. Also, the number of entries in the cache block is arbitrary, and this may be variable.

  Note that the entire packet transfer processing function or part of the packet transfer device in the above-described embodiment, the entire counter information update processing function or part of the packet transfer device, and the entire aging processing function or part of the packet transfer device. May be realized by recording a program for realizing these functions on a computer-readable recording medium, reading the program recorded on the recording medium into a computer system, and executing the program. Here, the “computer system” includes an OS and hardware such as peripheral devices.

  The “computer-readable recording medium” refers to a storage device such as a flexible medium, a magneto-optical disk, a portable medium such as a ROM and a CD-ROM, and a hard disk incorporated in a computer system. Further, the “computer-readable recording medium” dynamically holds a program for a short time, like a communication line when transmitting a program via a network such as the Internet or a communication line such as a telephone line. It is also possible to include those that hold a program for a certain time, such as a volatile memory inside a computer system serving as a server or client in that case. The program may be a program for realizing a part of the functions described above, and may be a program capable of realizing the functions described above in combination with a program already recorded in a computer system.

  The embodiment of the present invention has been described in detail with reference to the drawings. However, the specific configuration is not limited to this embodiment, and includes designs and the like that do not depart from the gist of the present invention.

It is a block diagram which shows the structure of the switch provided with the packet transfer apparatus by one Embodiment of this invention. It is a functional block diagram which shows the structure of the packet transfer apparatus by the embodiment. It is the block diagram which showed the operation | movement of the database reference forwarding part by the embodiment. FIG. 6 is a block diagram showing an operation of a cache reference forwarding unit according to the same embodiment. It is the block diagram which showed the relationship between the information which the database by the embodiment memorize | stores, and the information which the cache block on a cache memorize | stores. 5 is a flowchart showing an operation procedure of the packet transfer apparatus according to the embodiment. 5 is a flowchart showing an operation procedure of the packet transfer apparatus according to the embodiment. It is the block diagram shown about the management method of the counter by the same embodiment. It is the block diagram shown about the aging processing method by the embodiment. It is a schematic block diagram which shows the hardware constitutions of the information management apparatus by embodiment of this invention. It is a schematic functional block diagram which shows the function structure of the information management apparatus by the embodiment. It is the schematic showing notionally an example of the data structure which the information management apparatus by the embodiment manages. It is the schematic which showed the data structure showing the association between a database and a cache block by the embodiment. It is the schematic which shows the internal data structure of the object 527 (related object) by the embodiment. It is the schematic which shows the internal data structure of one cache block by the embodiment. It is a flowchart which shows the procedure of the process which the association validation process part by the embodiment associates and registers between the entry of a database, and a cache block. It is a flowchart which shows the procedure of the process in which the relevance invalidation process part by the same embodiment invalidates a cache block. It is a schematic data structure figure for demonstrating the example of a process which the garbage collection process part by the same embodiment collects an unnecessary object (related object).

Explanation of symbols

1: Switch device (packet transfer device)
2: control card device 3: input / output ports 3-1, 3-2, 3-3: input / output line card devices 4-1, 4-2, 4-3: forwarding processing devices 5-1, 5-2 5-3: Packet processing unit 6: Switch unit 11: Field extraction unit 12: Index calculation unit (cache block specifying unit)
13: Verification information storage unit 14: Verification unit 15: Database reference forwarding unit 16: Cache reference forwarding unit 17: Forwarding units 30-1, 30-2,..., 30-6: Reference information 60: Processing unit 200: Cache units 210-1, 210-2, ..., 210-t: Cache blocks 521-1, 521-2, ..., 521-n: Database (storage unit)

Claims (6)

A storage unit including a plurality of information entries for storing reference information related to packet transfer processing;
A field extractor for extracting a field related to packet forwarding from the packet;
A cache unit including a plurality of cache blocks that collectively store the reference information corresponding to the fields related to the forwarding;
A cache block identification unit that identifies the cache block based on a field related to the forwarding extracted by the field extraction unit;
A determination unit that determines whether or not the processing information exists in the cache block specified by the cache block specifying unit;
When the determination unit determines that the processing information does not exist, the reference information is read from the information entry of the storage unit based on the field related to the forwarding, and the packet information is read based on the read reference information. Performing the transfer process, storing the reference information as the processing information in the cache block specified by the cache block specifying unit, and when the determining unit determines that the processing information exists, the cache block specifying unit A forwarding unit that reads out the processing information from the cache block identified in step (a) and performs transfer processing of the packet based on the read processing information;
A packet transfer apparatus comprising: A counter information update unit for updating the counter information,
The information entry further stores first counter information;
The cache block further stores second counter information;
The forwarding unit further updates the second counter information when reading the processing information from the cache unit,
The packet transfer apparatus according to claim 1, wherein the counter update unit updates the first counter information based on the second counter information, and further updates the second counter information. An aging information update unit for updating aging information is provided.
The information entry further stores first aging information;
The cache block further stores second aging information;
The forwarding unit further updates the second aging information when reading the processing information from the cache block,
The aging information update unit updates the first aging information based on the second aging information, and further updates the second aging information. 2. The packet transfer apparatus according to item 1. A storage unit including a plurality of information entries for storing reference information related to packet transfer processing;
A cache unit including a plurality of cache blocks that collectively store the reference information corresponding to fields related to forwarding;
As a packet transfer method in a device equipped with
A field extraction step of extracting a field related to packet forwarding from the packet;
A cache block specifying step for specifying the cache block based on the field related to the forwarding extracted by the field extracting step;
A determination step of determining whether or not the processing information exists in the cache block specified in the cache block specifying step;
If it is determined in the determining step that the processing information does not exist, the reference information is read from the information entry of the storage unit based on the field related to the forwarding, and the packet information is read based on the read reference information. Performing the transfer process, storing the reference information as the processing information in the cache block specified in the cache block specifying step, and determining that the processing information exists in the determining step, the cache block specifying step A forwarding step of reading out the processing information from the cache block identified in step, and performing a transfer process of the packet based on the read out processing information;
A packet transfer method comprising: A counter information update step for updating the counter information,
The information entry further stores first counter information;
The cache block further stores second counter information;
The forwarding step further updates the second counter information when reading the processing information from the cache unit,
The packet transfer method according to claim 4, wherein the counter updating step updates the first counter information based on the second counter information, and further updates the second counter information. An aging information update step for updating aging information is provided.
The information entry further stores first aging information;
The cache block further stores second aging information;
The forwarding step further updates the second aging information when reading the processing information from the cache block,
6. The aging information update step updates the first aging information based on the second aging information, and further updates the second aging information. 2. The packet transfer method according to item 1.

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