CN108134739B

CN108134739B - Route searching method and device based on index trie

Info

Publication number: CN108134739B
Application number: CN201611091474.7A
Authority: CN
Inventors: 程晨; 陶想林; 张炜; 李彧
Original assignee: Sanechips Technology Co Ltd
Current assignee: Sanechips Technology Co Ltd
Priority date: 2016-12-01
Filing date: 2016-12-01
Publication date: 2020-10-02
Anticipated expiration: 2036-12-01
Also published as: CN108134739A

Abstract

The invention discloses a route searching method and a device based on an index trie, wherein the method comprises the following steps: searching an index node corresponding to a target IP in the in-chip index trie, and acquiring the following information from the index node: index base address of the out-of-chip envelope space, storage rule of the out-of-chip envelope space and index prefix; determining a tail prefix corresponding to the target IP address according to the index prefix and the target IP address; calculating the index address of the off-chip sub-envelope space according to the tail prefix and the storage rule of the off-chip envelope space; accessing the corresponding sub-packet network space according to the index address of the off-chip sub-packet network space to obtain a routing entry in the sub-packet network space; and comparing the target IP with the routing entries in the sub-network space, and outputting a result corresponding to the target routing entries when the target IP is successfully matched with the target routing entries in the sub-network space.

Description

Route searching method and device based on index trie

Technical Field

The invention relates to a network switching technology, in particular to a route searching method and device based on an index trie.

Background

With the rapid development of the Internet (Internet), the interface rate of core routers for backbone network interconnection has reached 400 Gbps. The performance of the network processor chip, being the heart of the core router, determines the performance differences of the core router. The routing lookup is one of core services of a network processor, the routing lookup rate needs to reach hundreds of megabits per second, the capacity of a routing table of the network processor further meets the requirement of giga entries, and the capacity and the lookup performance of the routing table become bottlenecks which restrict the network processing performance.

At present, most network processors adopt two main schemes for large-scale routing, one scheme is realized by using an external large-capacity Ternary Content Addressable Memory (TCAM) or a routing lookup chip, and the other scheme is realized by using an internal routing algorithm and an external Double Data Rate (DDR) chip.

For the first method, it is usually applied more in core high-end network processing, because the external chip implementation can ensure very high table entry capacity and search bandwidth, and certainly the corresponding cost is much higher.

Therefore, a second implementation mode of utilizing an internal routing algorithm and an external DDR is commonly adopted in a medium-low end application scene with low performance requirements. This is less costly to implement, but the corresponding routing lookup has a relatively low capacity, and lookup performance is also limited by DDR access bandwidth. As manufacturing technology advances, access rates and bandwidths of DDR chips continue to increase, but the number of off-chip accesses to the routing table is still limited for the query performance requirements of high-end routers.

At present, in a high-end router application scenario, more equipment vendors select a second way to implement a route lookup function in order to save cost. However, even if the latest DDR4 chip is used in the system, it can only support one off-chip routing access under the condition of satisfying the line speed lookup, thereby limiting the capacity of the routing table and the lookup performance, and becoming one of the most important factors that restrict the performance of the network processor.

Disclosure of Invention

In view of this, the embodiment of the present invention provides a routing lookup method and apparatus based on an index trie, which can support super-large scale routing lookup, and the lookup performance meets the requirement of a high-end core router.

The routing search method based on the index trie provided by the embodiment of the invention comprises the following steps:

searching an index node corresponding to a target IP in the in-chip index trie, and acquiring the following information from the index node: index base address of the out-of-chip envelope space, storage rule of the out-of-chip envelope space and index prefix; determining a tail prefix corresponding to the target IP address according to the index prefix and the target IP address;

calculating the index address of the off-chip sub-envelope space according to the tail prefix and the storage rule of the off-chip envelope space;

accessing the corresponding sub-packet network space according to the index address of the off-chip sub-packet network space to obtain a routing entry in the sub-packet network space;

and comparing the target IP with the routing entries in the sub-network space, and outputting a result corresponding to the target routing entries when the target IP is successfully matched with the target routing entries in the sub-network space.

In the embodiment of the present invention, the searching for an index node corresponding to a target IP in an intra-chip index trie includes:

and searching index nodes matched with the target IP in the in-chip index trie according to the longest prefix matching principle.

In this embodiment of the present invention, the determining, according to the index prefix and the target IP address, a tail prefix corresponding to the target IP address includes:

and removing the bit matched with the index prefix from the target IP address to be used as a tail prefix corresponding to the target IP address.

In this embodiment of the present invention, the calculating an index address of the off-chip sub-envelope space according to the tail prefix and the storage rule of the off-chip envelope space includes:

according to the storage rule of the off-chip envelope space, determining the bit according to which each off-chip envelope space stores the routing entry;

calculating an offset address according to the bit and the tail prefix; and generating an index address of the corresponding off-chip sub-envelope space according to the offset address.

In this embodiment of the present invention, the comparing the target IP with the routing entry in the sub-packet space includes:

and comparing the target IP with each routing entry, and searching the target routing entry matched with the target IP from each routing entry according to the longest prefix matching principle.

In the embodiment of the present invention, the method further includes:

constructing the on-chip index trie in a chip, wherein the on-chip index trie is formed by index nodes, and each index node corresponds to an off-chip envelope space;

constructing the off-chip sub-envelope space off-chip, wherein the off-chip envelope space forms a sub-trie, the off-chip envelope space formed by off-chip sub-envelope spaces, each off-chip sub-envelope supporting storage of a preset number of routing entries.

In the embodiment of the invention, when a new routing entry is inserted into the index trie, a target index node is searched in the index trie according to the longest prefix matching principle;

when the index trie is empty, an index node of the index trie is newly established, a sub-trie corresponding to the index node is established, the sub-trie corresponds to an off-chip envelope space, and the off-chip envelope space comprises 2^NThe envelope space of each outer slice is not less than 1;

according to the storage rule of the out-of-chip network space, determining the bit according to which the routing entry is stored;

and selecting the bit according to which the routing entry is inserted from the routing prefix of the routing entry to be inserted, and storing the routing entry into the corresponding off-chip sub-network space according to the selected bit.

accessing a sub-trie corresponding to a target index node, the sub-trie corresponding to an off-chip envelope space, the off-chip envelope space comprising 2^NThe envelope space of each outer slice is not less than 1;

In the embodiment of the present invention, the method further includes:

before storing the routing entry into the corresponding off-chip sub-network space according to the selected bit, determining whether the off-chip sub-network space is full;

when the out-of-chip envelope space is full, transforming the storage rule of the out-of-chip envelope space;

according to the converted storage rule, re-determining the bit according to which the routing entry is stored;

and storing all the stored routing entries of the off-chip envelope space and the routing entries to be inserted into the corresponding off-chip envelope space according to the bits of the new basis.

In the embodiment of the present invention, the method further includes:

when all storage rules of the out-of-chip network space transformation cannot store the route entries to be inserted, reconstructing all route prefixes stored in the out-of-chip network space to form a temporary trie;

finding out an optimal splitting node from the temporary trie as a new index node in the on-chip index trie;

storing the routing entries corresponding to the target index nodes into the out-of-chip envelope spaces corresponding to the target index nodes again according to corresponding storage rules;

and storing the routing entries corresponding to the new index nodes into the off-chip envelope spaces corresponding to the new index nodes again according to the corresponding storage rules.

In the embodiment of the invention, the index node also comprises a default result; the method further comprises the following steps:

when a new routing entry is inserted, traversing child nodes of the index trie and adding a default result;

if the length of the inserted prefix is equal to the index prefix of the envelope, storing a search result corresponding to the prefix as a default result in an internal index trie node, otherwise, storing the prefix and the search result in a sub-envelope, and traversing sub-nodes of the index node to add the default result;

if the default result of the envelope corresponding to the child node is 0, adding the inserted prefix as the default result; if the default result of the envelope is not 0, if the prefix is longer than the default result, replacing the original default result with the result of the newly inserted prefix.

The routing lookup apparatus based on index trie provided by the embodiment of the present invention includes:

the first searching module is used for searching an index node corresponding to the target IP in the in-chip index trie and acquiring the following information from the index node: index base address of the out-of-chip envelope space, storage rule of the out-of-chip envelope space and index prefix; determining a tail prefix corresponding to the target IP address according to the index prefix and the target IP address;

the computing module is used for computing the index address of the off-chip sub-envelope space according to the tail prefix and the storage rule of the off-chip envelope space;

the second searching module is used for accessing the corresponding sub-packet network space according to the index address of the off-chip sub-packet network space to obtain a routing entry in the sub-packet network space;

the comparison module is used for comparing the target IP with the routing entries in the sub-network space, and outputting the result corresponding to the target routing entries when the target IP is successfully matched with the target routing entries in the sub-network space; and outputting a default result when the target IP fails to be matched with the target routing entry in the sub-network space.

In an embodiment of the present invention, the first search module is specifically configured to: and searching index nodes matched with the target IP in the in-chip index trie according to the longest prefix matching principle.

In the embodiment of the invention, the bit matched with the index prefix is removed from the target IP address and is used as the tail prefix corresponding to the target IP address.

In an embodiment of the present invention, the calculation module is specifically configured to: according to the storage rule of the off-chip envelope space, determining the bit according to which each off-chip envelope space stores the routing entry; calculating an offset address according to the bit and the tail prefix; and generating an index address of the corresponding off-chip sub-envelope space according to the offset address.

In an embodiment of the present invention, the comparing module is specifically configured to: and comparing the target IP with each routing entry, and searching the target routing entry matched with the target IP from each routing entry according to the longest prefix matching principle.

In the embodiment of the present invention, the apparatus further includes:

the constructing module is used for constructing the in-chip index trie in a chip, wherein the in-chip index trie is formed by index nodes, and each index node corresponds to one out-of-chip envelope space; constructing the off-chip sub-envelope space off-chip, wherein the off-chip envelope space forms a sub-trie, the off-chip envelope space formed by off-chip sub-envelope spaces, each off-chip sub-envelope supporting storage of a preset number of routing entries.

accessing a sub-trie corresponding to a target index node, the sub-trie corresponding to an off-chip envelope space, the off-chip envelope space comprising 2^NSpace enveloped by outer sub-piecesN is more than or equal to 1;

In the embodiment of the invention, before the routing entries are stored in the corresponding off-chip sub-network spaces according to the selected bits, whether the off-chip sub-network spaces are full is determined;

In the embodiment of the invention, when all storage rules of the out-of-chip packet space transformation cannot store the route entries to be inserted, all route prefixes stored in the out-of-chip packet space are reconstructed to form a temporary trie;

In the embodiment of the invention, the index node also comprises a default result;

In the technical scheme of the embodiment of the invention, index nodes corresponding to a target IP are searched in an on-chip index trie, and the following information is obtained from the index nodes: index base address of the out-of-chip envelope space, storage rule of the out-of-chip envelope space and index prefix; determining a tail prefix corresponding to the target IP address according to the index prefix and the target IP address; calculating the index address of the off-chip sub-envelope space according to the tail prefix and the storage rule of the off-chip envelope space; accessing the corresponding sub-packet network space according to the index address of the off-chip sub-packet network space to obtain a routing entry in the sub-packet network space; and comparing the target IP with the routing entries in the sub-network space, and outputting a result corresponding to the target routing entries when the target IP is successfully matched with the target routing entries in the sub-network space. By adopting the technical scheme of the embodiment of the invention, the ultra-large scale route searching can be supported under the condition of smaller on-chip space requirement. The multi-rule storage mode improves the utilization rate of off-chip space, so that the route searching algorithm of the embodiment of the invention supports super-large scale route searching.

Drawings

The drawings illustrate generally, by way of example, but not by way of limitation, various embodiments discussed herein.

FIG. 1 is a flowchart of a route lookup method based on an index trie according to an embodiment of the present invention;

FIG. 2 is a diagram illustrating an embodiment of an on-chip index trie generation;

FIG. 3 is a schematic diagram of a storage structure of an envelope space according to an embodiment of the present invention;

FIG. 4 is a flow chart of the generation of an indexed trie and a sub-trie of an embodiment of the present invention;

FIG. 5 is a diagram of a route lookup apparatus according to an embodiment of the present invention;

FIG. 6 is a diagram of an example of prefix insertion for an algorithm structure according to an embodiment of the present invention;

FIG. 7 is a diagram illustrating an example of a replacement envelope storage rule of an algorithm structure according to an embodiment of the present invention;

FIG. 8 is a diagram of an example envelope split of an algorithm structure according to an embodiment of the present invention;

FIG. 9 is a diagram illustrating an example IP lookup according to an embodiment of the present invention;

fig. 10 is a block diagram of a routing lookup apparatus based on an index trie according to an embodiment of the present invention.

Detailed Description

So that the manner in which the features and aspects of the embodiments of the present invention can be understood in detail, a more particular description of the embodiments of the invention, briefly summarized above, may be had by reference to the embodiments, some of which are illustrated in the appended drawings.

The basic idea of the embodiment of the invention is as follows: and constructing an on-chip index trie and an off-chip envelope space, wherein the off-chip envelope space supports multi-rule storage. The index trie stores a block of memory space address of an off-chip DDR or memory, and most of routing table item information is stored in the off-chip memory (namely, an off-chip envelope space). And the off-chip space corresponding to the index node is divided into storage modules with equal and continuous sizes. And the target IP carries out longest prefix matching in the index trie, and indexes to the off-chip DDR or a certain storage module in the memory according to the on-chip index node searching information to obtain the next hop information. The invention provides a multi-rule storage mode, which determines a storage module corresponding to a target IP through a certain rule, and selects a plurality of storage modes for a routing prefix needing to be stored by providing a plurality of rule selectable modes, thereby improving the utilization rate of an off-chip memory space.

Fig. 1 is a schematic flowchart of a route lookup method based on an index trie according to an embodiment of the present invention, and as shown in fig. 1, the route lookup method based on the index trie includes:

step 101: searching an index node corresponding to a target IP in the in-chip index trie, and acquiring the following information from the index node: index base address of the out-of-chip envelope space, storage rule of the out-of-chip envelope space and index prefix; and determining a tail prefix corresponding to the target IP address according to the index prefix and the target IP address.

Step 102: and calculating the index address of the off-chip sub-envelope space according to the tail prefix and the storage rule of the off-chip envelope space.

Step 103: and accessing the corresponding sub-packet network space according to the index address of the off-chip sub-packet network space to obtain the routing entry in the sub-packet network space.

Step 104: and comparing the target IP with the routing entries in the sub-network space, and outputting a result corresponding to the target routing entries when the target IP is successfully matched with the target routing entries in the sub-network space.

In the embodiment of the present invention, the method further includes:

accessing a sub-trie corresponding to a target index node, the sub-trie pairAn off-chip envelope space comprising 2^NThe envelope space of each outer slice is not less than 1;

In the embodiment of the present invention, the method further includes:

The routing lookup algorithm based on the index trie provided by the embodiment of the invention totally comprises the following steps: index node generation, routing prefix storage structure, index node splitting, index node merging and multi-rule storage.

The on-chip index trie is a tree structure derived from a standard trie, and has the same basic characteristics as a classic trie, except that the index trie stores not routes but index nodes representing a part of a sub-tree (205). The root node of each subtree can represent an index node, and a trie is established for the index node, namely the index trie.

Referring to fig. 2, the fixed-size envelope space of the off-chip memory corresponding to the node (e.g., the node in fig. 203) of the on-chip index trie is defined as a sub-trie (301); in order to complete the search after one access, the sub-trie is divided into a plurality of sub-envelopes (303) with the same size according to the access bandwidth of the DDR, and the data bit width of the sub-envelopes is the same as the off-chip access bandwidth. For example, in an application scenario, DDR is accessed once per beat, and the bit width is 256b, the size of the sub-envelope may be defined as 256 bits, that is, the sub-envelope can store 256 bits of routing prefix data; the number of sub-envelopes in each envelope is N, and the size of each envelope space is N × 256 bits.

In the above definition, according to the interface bandwidth of the DDR, the envelope space corresponding to the intra-chip index trie node is divided into N sub-envelope spaces. When a routing prefix is inserted, an index node is hit in the in-chip index trie, and bits on a path from a root node of the index trie to the hit node are stored in the hit index node as a prefix, wherein the prefix is called an index prefix; the prefix excluding the index prefix portion of the route prefix is referred to as a tail prefix. And storing the tail prefix in a certain sub-envelope space in the envelope space corresponding to the index node according to a rule.

Referring to fig. 3, the envelope is a child trie (302) arranged in a trie. The child trie is a trie with a fixed height, the height of which is determined by the number of child envelopes. The number N of sub-envelopes in each envelope is taken after the index prefix

The bit is made to have a height of

The number of leaf nodes of the trie is N. Each leaf node of the sub-trie indexes one sub-envelope space, and N sub-envelope space addresses are continuous. Assuming that the address of the first sub-envelope (303) is addr, the address of the second sub-envelope (304) is addr +1, and so on for the other sub-envelopes. If the length of the tail prefix is more than or equal to

Then get the front of the tail prefix

Bits are matched in the regular sub-trie, and tail prefixes are stored in a sub-network space indexed by leaf nodes hit in the sub-trie. If the length of the tail prefix is less than

And matching the tail prefix in the regular sub-trie, wherein the tail prefix needs to copy the sub-network space corresponding to all leaf sub-nodes of the hit node stored in the sub-trie. When N is 4, the envelope inserts routing prefix 01, the tail prefix 01 is 1, and the packet needs to be copied and stored in the sub-packetCollaterals 305 (10) and 306 (11). If the prefixes in the sub-envelopes corresponding to the leaf sub-nodes of the hit node are all the sub-prefixes containing the tail prefix, if 11 exists, the tail prefix does not need to be copied and stored in the current sub-envelope. If there is already 11 prefixes in the sub-packet network 306, or there are prefixes at 110 and 111, or other coincidences, then there is no need to copy 1 in the sub-packet network 306 (11).

The only way to grow the intra-indexed trie is the splitting of the sub-trie. The sizes of the envelope and the sub-envelope corresponding to the on-chip index trie node are fixed, and when the space of any sub-envelope in the envelope is not enough to store a new prefix, the current index node needs to be adjusted. For example, in one scenario, the size of the sub-envelope space is 256b, and when stored in the sub-envelope, each routing prefix needs to store 22-bit search results. When 4 prefixes with the length of 32 bits are stored in the sub-envelope, the sub-envelope space occupies (32+22) × 4, and if a prefix with 32 bits is added to the sub-envelope, the sub-envelope needs to be adjusted.

When a certain sub-envelope is full and a routing prefix is stored, the worst case exists, only one sub-envelope in N sub-envelopes has insufficient space and needs to be split, and other N-1 sub-envelopes are all empty. In this case, the DDR space is less utilized.

The embodiment of the invention also comprises a method for storing the route prefix with multiple rules, which reduces the splitting times of the off-chip sub-envelope and increases the effective storage rate of the off-chip sub-envelope, thereby reducing the occupied space in the chip and reducing the space requirement of the off-chip DDR.

The embodiment of the invention allows a plurality of regular sub-trie structures to be defined, and when the sub-envelopes exist under a certain regular sub-trie structure, the rules are tried to be transformed for storage, which is called multi-rule storage. When the sub-envelope space is insufficient, another one is taken from the tail prefix

Matching in a regular sub-trie, trying to store the tail prefix in it without splittingHis sub-envelope space. It should be noted that when the tail prefix is stored in multiple rules, all the prefixes stored in the envelope before are required to be stored in the corresponding sub-packet according to the new rule. Assuming a prefix at the tail

Arbitrarily fetch in bit

Bits are matched in the sub-trie, present

A combination of species is called as

And (6) planting rules. If at this point

In one rule, there is a tail prefix that is inserted into the routing prefix stored in the envelope without requiring splitting. The current rule needs to be stored in the intra-chip index trie node, and all prefixes in the envelope are stored in the corresponding sub-envelopes again according to the new rule. If the splitting is still needed after traversing the M rules, the splitting is performed according to the splitting operation. The rule change of the invention is not limited to the assumed mode, and can be selected according to the actual situation.

The splitting mode is as follows: splitting index trie nodes needs to be according to the longest prefix matching principle, and prefix average splitting in the corresponding envelope space of the index nodes is performed as much as possible. And establishing a temporary trie for all prefixes in the index node, and finding out the prefixes capable of evenly dividing all the prefixes in the envelope as much as possible. And inserting a new index node into the internal index trie according to the prefix, and splitting the prefix belonging to the new index node in the envelope of the original index node.

When deleting the routing prefix, if the number of the routing prefixes in the envelope space corresponding to the index node is less than a preset minimum value, accessing the parent, the brother and the child node of the current index node in the index trie, and if one node can be found to be merged with the parent, merging operation is required. If merging occurs, the index nodes deleted due to merging need to be deleted on the index trie, and the route prefixes of the corresponding envelope spaces need to be merged together. This operation may delete 2 inodes and create a new inode.

When the hardware is implemented, the rule number needs to be stored in the index trie in the chip as a part of a search result, and after a certain longest matching index node in the index trie is hit, only corresponding bits are taken from the tail prefix of the search key value as an offset address, and the address of the sub-envelope is calculated, so that the corresponding sub-envelope is accessed.

Changing the rule can reduce the splitting times of the nodes and improve the utilization rate of the storage space, and the splitting times are reduced, so that the number of the nodes of the index trie is reduced, and the occupied space in the chip is reduced.

When the routing lookup is implemented on the basis of the index trie, the routing lookup needs to be completed under the condition of one DDR reading, and the returned result is ensured to be the longest prefix matching, so that a default result needs to be added to the internal index trie node. And during route searching, reading one sub-envelope in the DDR, and if no result is searched in the sub-envelope, directly returning a default result of the on-chip index trie node as a searching result. The default result is the result of a lookup of the index node's own or parent node.

The longest prefix of the index prefixes matches the routing prefix. According to whether the envelope is split when the prefix is inserted, the default result added to the index trie node is divided into two cases. One is to add the default result if the envelope does not need to be split, and the other is to add the default result after the current envelope needs to be split.

In the first case, the sub-packet network may store the inserted prefix or may store the prefix after changing the rule, if the length of the inserted prefix is equal to the index prefix of the envelope, the search result corresponding to the prefix is stored as a default result in the internal index trie node, otherwise, the prefix and the search result thereof are stored in the sub-packet network (405), and then the default result is added by traversing the child nodes of the index node.

If the default result of the envelope corresponding to the child node is 0, adding the inserted prefix as the default result;

if the default result for the envelope is not 0, the default result is overridden (406) if the prefix is longer than the default result.

The default result of index node 111 (205) in the intra-chip index trie (201) is 111.

In the second case, the prefix cannot be inserted after the rule is changed, and the index node needs to be split. And (4) newly building an index node in the index trie, performing splitting operation and storing the prefix in the newly built index node (407).

And if the prefix length in the prefix of the newly-built index node is equal to the prefix length of the index prefix of the newly-built node, directly storing the prefix as a default result.

And if the newly-built index node is not the real routing entry and the default result is 0, traversing the father node of the index node and adding the default result.

If the default result of the newly-created index node is not 0, the child node addition result of the current index node is also traversed (408).

The default result of index node 0100 x (203) in on-chip index trie (201) is prefix e:010 x.

The invention provides a route searching device based on an index trie, which comprises: the system comprises a route searching algorithm software module, a route updating interface module and a route searching hardware module. And the route searching algorithm software module (501) is used for responding to the issued route updating instruction and sending the changed node information to the route updating interface module. And the routing update interface module (502) writes the update node data into the hardware module according to a certain sequence according to the update node data sent by the routing algorithm software module. The route searching hardware module (503) is used for pipeline searching and is mainly divided into an on-chip index trie searching module and an off-chip route searching module. The on-chip index trie module sends the result of the longest prefix matching to the off-chip route searching module when a hardware route searching request exists. The off-chip route searching module locates the sub-envelope address according to the index node information sent by the on-chip index trie searching module, performs longest prefix matching and returns a searching result.

In summary, embodiments of the present invention provide a routing lookup method and apparatus based on an index trie, which can support very large scale routing lookup under the condition of smaller on-chip space requirement. The multi-rule storage mode improves the utilization rate of off-chip space, so that the route searching algorithm of the embodiment of the invention supports large-scale route searching.

The technical solution of the embodiments of the present invention is further described in detail below with reference to specific application scenarios.

The first embodiment is as follows:

this embodiment is used to illustrate how to construct the index trie and the sub-trie described in the present invention, as shown in fig. 4:

step 401: and the master control CPU sends a routing key value to the routing algorithm software module, wherein the routing key value comprises information such as a routing prefix, a prefix length, a search result of the prefix or a search result address and the like.

Step 402: the routing algorithm software module firstly uses the routing prefix as a key value to search in the existing index trie. And according to the longest prefix matching principle, finding an index node with the existing prefix length smaller than the key value.

If the original trie is empty, an index node is newly established according to the numerical value of the first 8 bits of the inserted key value, because the routing prefix does not have a prefix entry with the length smaller than 8. An envelope space, namely a sub-trie space, is newly established, and the sub-trie space is initialized by default rules.

The information stored by the index node includes: index prefix, index prefix length, default result of the index prefix, corresponding envelope space base address and storage rule of the sub-trie.

Step 403: and finding corresponding data according to the base address of the sub-trie space of the index node, and inspecting the storage condition of the inserted prefix on the sub-network of the sub-trie according to the storage rule of the sub-trie.

Step 404: considering the storage of the inserted prefix on the sub-network includes:

1. whether the route is a default route (a prefix with the prefix length equal to the index prefix length is inserted), if so, storing the result of inserting the prefix in the index node; otherwise, inserting the sub-envelope;

2. insert into only one sub-envelope: whether the sub-packet can accommodate the prefix;

3. a duplicate insertion into multiple sub-envelopes needs to be done: traversing all the sub-envelopes to determine whether the prefix can be accommodated;

if the prefix can be accommodated as a result of the investigation, jumping to step 5; otherwise, jumping to step 7.

Step 405: the inserted prefixes are stored in the corresponding sub-packet. If the prefix length of the inserted prefix is the same as the index prefix length, taking the prefix of the inserted prefix as a default result of the envelope, otherwise, directly storing the prefix in the corresponding sub-envelope;

the information to be stored in the sub-envelope includes: inserting tail bits of the prefix, inserting prefix length of the prefix, and inserting a search result corresponding to the prefix.

Step 406: returning to the index trie, all child nodes of the index node are traversed.

1. If the default result of the sub-index node is 0, adding the result of inserting the prefix as the default result;

2. if the default result of the sub-inode is not 0, the default result is replaced if the prefix length of the inserted prefix is longer than the prefix length of the default result.

After step 6 is completed, jump to step 10 and complete the insertion.

Step 407: an attempt is made to regularly replace the prefix stored in the envelope.

Sequentially traversing all rules, storing all items including the newly inserted prefix by using the new rule, and jumping to the step 6; otherwise, jumping to step 8.

Step 408: and splitting the index nodes and the corresponding envelope spaces.

1. Constructing temporary sub-tries of all prefixes in the envelope space;

2. finding out the optimal split node and the optimal storage rule of each sub trie;

3. inserting the split node serving as a newly-built index node into the index trie;

4. and taking out all prefix data belonging to the new index node from the original envelope, and adding the prefix data into the envelope corresponding to the new index node according to a storage rule.

Step 409: and adding a default result to the newly-built index node.

2. If the default result of the newly-built node is 0, traversing the father node of the index trie to add a result; finding a nearest parent node, and taking the default result of the parent node as the default result of the parent node;

3. if the default result of the newly-built node is not 0, traversing all child node adding results of the newly-built index node;

Step 410: the insertion is completed.

The generation of indexed tries and envelopes (sub-tries) described in the present invention grows as the routing prefix is inserted. If the prefix entry is deleted, firstly, the prefix entry is searched in the index trie, and after the longest prefix matching hit, the inverse process of the insertion process is executed in the sub trie operation.

Example two:

as shown in fig. 5, the route lookup apparatus based on index trie according to the embodiment of the present invention includes: a routing table entry management software module (501), a routing table entry update interface module (502), a route lookup index module (on-chip) (503), an address index module (504), and a route lookup table entry storage module (off-chip) (505).

And the routing table item management software module (501) is used for responding to the issued routing update instruction and sending the changed node information to the routing table item update interface module.

The route updating instruction can be an instruction for inserting or deleting a route entry or checking a route table;

after receiving the instruction from the main control CPU, the routing table item management software module executes a corresponding algorithm action, records all hardware item information that needs to be changed (including information of index nodes in the chip, information of all sub-envelopes in the envelope space outside the chip, and the like), and transmits the information to the routing table item update interface module at one time.

The routing table item updating interface module (502) writes the updated node data into the routing lookup index module (on-chip) (503), the routing lookup table item storage module (off-chip) (505) and the result comparison module (on-chip) (506) respectively through PCIe and other high-speed interfaces according to the updated node data sent by the routing algorithm software module according to a certain sequence.

The sequence of updating the information by the updating interface module needs to ensure that the information is completely written into the route searching hardware module under the condition that the route searching data flow is not interrupted and the searching error is not generated.

The route search index module (on chip) (503) is the main search module in the hardware module, completes the search of the index trie, and sends the search result to the address resolution module (504). The search result comprises the index base address of the sub-envelope, tail bits in the key value and rule numbers stored outside the chip. And meanwhile, the search key value and the default result are sent to a result comparison module (506) to wait for the data of the off-chip sub-envelope to return.

The address analysis module (504) intercepts the corresponding bit from the search key value as the offset address of the off-chip sub-envelope according to the storage rule number and the hit prefix length, and the actual access address of the off-chip sub-envelope is formed by adding the offset address to the base address in the search result, and a read request is initiated to the off-chip routing search table entry storage module.

After receiving the read request, the route lookup table entry storage module (off-chip) (505) returns the stored sub-packet network information to the result comparison module (on-chip) (506).

Finally, the result comparison module (in-chip) (506) compares the returned data with the search key value, obtains the final search result according to the longest prefix IP principle, and returns the search result.

Example three:

as shown in fig. 6, it is assumed that the initial routing table has no entry, the sub-envelope number of the sub-trie is 4, and the sub-envelope depth of the tail bit is 4.

Inserting a first routing entry A:1 (601), firstly searching in the index trie, and building an index node "+" (602) of the index trie and a sub-trie (603) taking "+" as index prefix if the index trie is found to be empty; the sub-trie has 4 sub-envelopes corresponding to the first two bit values of the prefix respectively: "00", "01", "10" and "11". Because the prefix a:1 is the parent prefix of "10" and "11", so a needs to be stored in duplicate in these two sub-envelopes, and the stored entries are "1: a "(604), where" 1 "indicates that any IP accessing the sub-envelope that can match" 1 "can hit," a "represents that the lookup result for the entry is" a ".

A second route entry B:00 is inserted (605). Searching in the index trie, finding the index node with the longest match as "+", then accessing the "child trie" ("603), and examining the first 2 bits of the entry B; finding the first two bits "00" of entry B, then accessing "sub-envelope 00" (606); the sub-envelope is found (606) to be empty, and entry B is inserted into the sub-envelope. The storage format is '00 x B', which indicates that any IP which can match 00 x can be hit when accessing the sub-packet, and 'B' indicates the search result of the entry.

A third routing entry C is inserted, 100 x. The operation steps are similar to the case of the second route, and an entry C is stored in the "sub-envelope 10" in the format of "100 × C", which means that all the IPs accessing the sub-envelope that can match 100 × can hit, and "C" is the search result.

The process of inserting the remaining entries (607) is similar to that described above, with the final representation of the child trie shown at 608. Where "sub-envelope 00" stores entry B, "sub-envelope 01" stores entry E, "sub-envelope 10" stores entries A and C, and "sub-envelope 11" stores entry A, D, F, G.

The multi-rule storage flow is further described below for illustration and understanding only, and does not limit the selection of rules in the present invention.

Assuming that "index nodes" already exist in the index trie and the rule stored in the index nodes is marked as rule0, as shown in 701 and 702 in fig. 7, the number of sub-envelopes in the envelope nodes is 4, and each sub-envelope can store 4 entries. The predetermined rule is a combination of 2 bits out of the first 3 bits of the tail prefix. Each envelope has 3 regular choices of rule0 (

bit

1, 2 of the tail prefix), rule1 (

bit

2, 3 of the tail prefix), rule2 (

bit

1, 3 of the tail prefix).

The current child trie (702) uses rule0 for storing prefixes, i.e., the first 2 bits of the tail prefix are used as the label for allocating sub-envelopes.

When a further route entry H:11001 needs to be inserted, it first accesses the indexed trie, finds the child trie (702), and knows that the child trie is stored according to rule 0. Since the first two bits of the tail prefix of H are "11," the "sub-envelope 11" is accessed (703). It is found that "sub-envelope 11" already holds 4 prefixes, which cannot be stored any more, and therefore requires a readjustment of the entire sub-trie.

Firstly, regular transformation is carried out on a sub-trie, rule0 is changed into rule1, namely the 2 nd and 3 rd bits of a tail prefix are inspected; all the route entries in the child trie are re-inserted into the tree according to rule1, the end result will be shown as 704 in fig. 7. Under rule of rule1, all current routing entries can be stored without splitting the sub-trie.

Further, if it is not desirable to perform excessive calculations in inserting each entry in view of the route update performance, then the current insertion process may end because H can already be successfully inserted into the routing table at this point.

If a more optimal insertion result is desired, it is necessary to review other rules, compare the final results obtained under each rule, and determine which rule to use for insertion.

For example, the sub trie is examined again by using rule2, that is, the 1 st and 3 rd bits of the tail prefix are examined; all the route entries in the child trie are reinserted into the tree according to rule2, the end result will be shown in fig. 705. It can be seen that when storing according to rule1, the number of actually stored entries reaches 11, because there are relatively many copies, where a makes 3 copies (there are entries a in all 3 sub-envelopes); when the storage is performed according to rule2, the number of copies is relatively small (there are 2 copies of entry a), and thus 10 entries are actually stored. Rule2 may be selected for storage based on the principle that storage capacity is saved optimally.

The envelope split case is described below.

Assuming that there is an index node in the index trie, as shown in 801 in fig. 8, there is only one node "×" in the index trie, the number of sub-envelopes in the envelope node is 4, each sub-envelope can store 4 entries, and the storage rule used is rule2 (1, 3 bits of tail prefix).

When a routing entry J:11100 needs to be inserted again, the index trie is firstly accessed, the index node ". times.of the longest prefix match is found, then the sub trie is accessed, and the sub envelope 11 is accessed according to rule 2; it is found that the sub-packet can no longer store an entry.

As described above for changing the rule, the rule changing attempt also finds that all the rules may not store the routing entry, and thus needs to split the sub-trie.

All prefixes stored in the child trie are first reconstructed to construct a "temporary trie," as shown at 802 in fig. 8. After the construction is finished, the temporary trie is inspected, the nodes on the temporary trie are found, the number of the routing entries actually existing in the child nodes of the nodes is close to half of the total number of the routing entries, and the nodes '11' in the graph meet the condition. So "node 11" is selected as the new index tree node.

The temporary trie is divided into two parts according to the node 11, and the original node 11 and the node 11 serve as index prefixes of the two parts respectively, as shown in 803 and 804 in fig. 8.

By inserting "node 11" as a new index prefix into the index trie, the index trie has two index nodes as shown in fig. 805. Since "node 11" is not a real routing entry and does not have its own lookup result, the lookup result a of its parent node 1 needs to be stored as a default result in the corresponding node of the index trie.

All route entries belonging to the "child trie" are inserted into the "child trie" and stored in accordance with rule0, as indicated at 806 in fig. 8.

All the route entries belonging to the "child trie 11" are inserted into the "child trie 11" and stored in accordance with rule0, as indicated by 807 in fig. 8.

Example four:

it is assumed that the existing routing table is as shown in fig. 9.

1. Searching an IP address 11100100;

firstly, the IP address is searched in a route searching index module (904) to obtain an index node 11 with the longest prefix matching, and the corresponding index base address is b' 100; and knows that its storage rule is rule 0; the tail bit of the IP address is "100100". In the address resolution module (905), the 1 st bit and the 2 nd bit are 10, so the offset address is b ' 010, an off-chip index address b ' 110 is formed, and a sub-packet 10 ' in 903 is accessed;

after reading the sub-packet data, sending the sub-packet data to a result comparison module (906), finding that three routing entries '111 × D', '11101 × F' and '11100 × J' exist, and simultaneously comparing the IP with the three routing entries to obtain '11100 × J' which is the longest prefix matching entry, so that J is returned as the search result of the IP.

2. Lookup IP address 01101100;

firstly, searching in a route searching index module by using the IP address to obtain index nodes with the longest prefix matching as x and the corresponding index base address as b' 000; and its storage rule is rule 0; the tail bit of the IP address is '01101100', the 1 st bit and the 2 nd bit thereof are 01, so the offset address thereof is b '001, the off-chip index address b' 001 is formed, and the sub-packet envelope 01 in the access 902 is accessed;

after reading the sub-envelope data, the sub-envelope data is sent to a result comparison module (906), a routing entry '010 x: E' exists in the sub-envelope, and the IP is compared with the routing entry to find out mismatch. Because the default result is Null, the lookup fails and no hit routing entry is found.

3. Looking up an IP address 11000000;

firstly, searching in a route searching index module by using the IP address to obtain index nodes 11 with the longest prefix matching; the corresponding index base address is b' 100, and the storage rule is rule 0; the tail bit of the IP address is "000000", the 1 st bit and the 2 nd bit thereof are 00, so the offset address thereof is b '000, the off-chip index address b' 100 is formed, so the "sub-packet network 00" in 903 is accessed;

after reading the sub-envelope data, the sub-envelope data is sent to a result comparison module (906), and a routing entry '11001': h ", cannot match the lookup IP, but because of default result a, default result a is returned as the final lookup result.

Fig. 10 is a schematic diagram illustrating a module composition of a route lookup apparatus based on an index trie according to an embodiment of the present invention, and as shown in fig. 10, the apparatus includes:

a first searching module 1001, configured to search an index node corresponding to a target IP in an intra-chip index trie, and obtain the following information from the index node: index base address of the out-of-chip envelope space, storage rule of the out-of-chip envelope space and index prefix; determining a tail prefix corresponding to the target IP address according to the index prefix and the target IP address;

a calculating module 1002, configured to calculate an index address of the off-chip sub-envelope space according to the tail prefix and a storage rule of the off-chip envelope space;

a second searching module 1003, configured to access a corresponding sub-packet network space according to the index address of the off-chip sub-packet network space, to obtain a routing entry in the sub-packet network space;

a comparing module 1004, configured to compare the target IP with the routing entry in the sub-network space, and output a result corresponding to the target routing entry when the target IP is successfully matched with the target routing entry in the sub-network space; and outputting a default result when the target IP fails to be matched with the target routing entry in the sub-network space.

In this embodiment of the present invention, the first searching module 1001 is specifically configured to: and searching index nodes matched with the target IP in the in-chip index trie according to the longest prefix matching principle.

In this embodiment of the present invention, the calculating module 1002 is specifically configured to: according to the storage rule of the off-chip envelope space, determining the bit according to which each off-chip envelope space stores the routing entry; calculating an offset address according to the bit and the tail prefix; and generating an index address of the corresponding off-chip sub-envelope space according to the offset address.

In this embodiment of the present invention, the comparing module 1004 is specifically configured to: and comparing the target IP with each routing entry, and searching the target routing entry matched with the target IP from each routing entry according to the longest prefix matching principle.

In the embodiment of the present invention, the apparatus further includes:

a building module (not shown in the figure) for building the on-chip index trie in a chip, wherein the on-chip index trie is formed by index nodes, and each index node corresponds to an off-chip envelope space; constructing the off-chip sub-envelope space off-chip, wherein the off-chip envelope space forms a sub-trie, the off-chip envelope space formed by off-chip sub-envelope spaces, each off-chip sub-envelope supporting storage of a preset number of routing entries.

In the embodiment of the invention, the index node also comprises a default result; when a new routing entry is inserted, traversing child nodes of the index trie and adding a default result;

Those skilled in the art will understand that the functions implemented by the modules in the routing lookup apparatus based on index trie shown in fig. 10 can be understood by referring to the related description of the routing lookup method based on index trie. The functions of the units in the routing lookup apparatus based on the index trie shown in fig. 10 can be implemented by a program running on a processor, and can also be implemented by specific logic circuits.

As will be appreciated by one skilled in the art, embodiments of the present invention may be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of a hardware embodiment, a software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, optical storage, and the like) having computer-usable program code embodied therein.

The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention.

Claims

1. A routing lookup method based on an index trie is characterized by comprising the following steps:

comparing the target IP with the routing entries in the sub-network space, and outputting a result corresponding to the target routing entries when the target IP is successfully matched with the target routing entries in the sub-network space;

the calculating an index address of the off-chip sub-envelope space according to the tail prefix and the storage rule of the off-chip envelope space includes:

2. The method for routing lookup based on an indexed trie of claim 1, wherein the looking up an inode corresponding to a target IP in the intra-chip indexed trie comprises:

3. The method according to claim 1, wherein the determining a tail prefix corresponding to the target IP address according to the index prefix and the target IP address comprises:

4. The method of claim 1, wherein comparing the target IP with the routing entries in the sub-packet network space comprises:

5. The method for routing lookup based on an indexed trie of claim 1, wherein the method further comprises:

6. The index trie-based route lookup method according to claim 5,

when a new routing entry is inserted into the index trie, searching a target index node in the index trie according to the longest prefix matching principle;

when indexing trieWhen the tree is empty, an index node of the index trie is newly established, a sub trie corresponding to the index node is established, the sub trie corresponds to an off-chip envelope space, and the off-chip envelope space comprises 2^NThe envelope space of each outer slice is not less than 1;

7. The index trie-based route lookup method according to claim 5 or 6,

8. The method of claim 7, wherein the method further comprises:

9. The method of claim 8, wherein the method further comprises:

10. The index trie-based route lookup method according to claim 8, wherein the index node further includes a default result; the method further comprises the following steps:

11. An apparatus for routing lookup based on an indexed trie, the apparatus comprising:

the comparison module is used for comparing the target IP with the routing entries in the sub-network space, and outputting the result corresponding to the target routing entries when the target IP is successfully matched with the target routing entries in the sub-network space; when the matching of the target IP and the target routing entry in the sub-network space fails, outputting a default result;

the calculation module is specifically configured to: according to the storage rule of the off-chip envelope space, determining the bit according to which each off-chip envelope space stores the routing entry; calculating an offset address according to the bit and the tail prefix; and generating an index address of the corresponding off-chip sub-envelope space according to the offset address.

12. The index trie-based route lookup apparatus according to claim 11, wherein the first lookup module is specifically configured to: and searching index nodes matched with the target IP in the in-chip index trie according to the longest prefix matching principle.

13. The apparatus according to claim 11, wherein bits of the target IP address that match the index prefix are removed as a tail prefix corresponding to the target IP address.

14. The index trie-based route lookup apparatus according to claim 11, wherein the comparing module is specifically configured to: and comparing the target IP with each routing entry, and searching the target routing entry matched with the target IP from each routing entry according to the longest prefix matching principle.

15. The indexed trie-based route lookup apparatus according to claim 11, wherein the apparatus further comprises:

16. The indexed trie-based route lookup apparatus according to claim 15,

17. The index trie-based route lookup apparatus according to claim 15 or 16,

18. The indexed trie-based route lookup apparatus according to claim 17,

19. The indexed trie-based route lookup apparatus according to claim 18,

20. The indexed trie-based route lookup apparatus according to claim 18, wherein the index node further includes a default result;