JP2003195834A - Display device and its driving method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress the generation of stripes parallel to signal lines of a display device which uses a time-base expanded video signal. <P>SOLUTION: The display has a signal line driving circuit which outputs display signals corresponding to a plurality of pixels addressed with a scanning signal to a plurality of signal lines and this signal line driving circuit outputs the display signals to all the signal lines by repeatedly performing the operation of sampling (n) video signals obtained by expanding an input video signal on the time base by (n) times and the operation of outputting (n) display signals corresponding to the (n) sampled video signals to a plurality of blocks in order by the blocks and then selectively outputs a correction signal to signal lines adjacent to a block to which display signals are outputted later among the plurality of signal lines belonging to a block to which the display signals are outputted first among mutually adjacent blocks. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix type display device and a driving method thereof, and is particularly preferably applied to an active matrix type driver monolithic display device in which a driving circuit is formed integrally with a display panel. .

[0002]

2. Description of the Related Art A conventional active matrix type driver monolithic liquid crystal display device 100 will be described with reference to FIG.
The structure and operation of will be described.

The liquid crystal display device 100 has a signal line driving circuit (source driver) 101, a scanning line driving circuit (gate driver) 102, and a display section 103. The display unit 103 includes a plurality of scanning lines (gate lines) G1 to Gn arranged in parallel with each other and a plurality of signal lines (source lines) arranged in parallel with each other in a direction intersecting the scanning lines G1 to Gn.
S1 to Sm, a plurality of TFTs (thin film transistors) 104 each connected to one of the scanning lines G1 to Gn and the signal lines S1 to Sm, and one TFT 104.
And a picture element capacitor 105 connected to.

The picture element capacitance 105 is composed of, for example, a liquid crystal capacitance and an auxiliary capacitance provided in parallel with the liquid crystal capacitance. The plurality of picture element capacitors 105 are arranged in a matrix, and each corresponds to a pixel of the display unit 103. The liquid crystal capacitance includes, for example, the scanning lines G1 to Gn and the signal lines S1 to S.
m and the pixel electrode (not shown) formed on the substrate on which the TFT 104 is formed (also referred to as a “TFT substrate”), and a counter electrode formed on a counter substrate arranged so as to face the pixel electrode. (Not shown) and a liquid crystal layer (not shown) between the pixel electrode and the counter electrode.
The auxiliary capacitance may be omitted.

In the signal line drive circuit 101, a start pulse sp, which is a control signal, clock signals ck and ckb, and an input video signal (sometimes referred to as "Videoin") are doubled in the time-axis direction to obtain 2 signals. Two video signals vi
Deo1 and video2 are input. The time-axis expansion (also referred to as "time-axis expansion") of the input video signal will be described later. A start pulse spg, clock signals ckg and ckgb, and the like are input to the scan line driver circuit 102.

As shown in FIG. 2, the signal line driving circuit 101 is a switch (for example, an analog circuit) that controls the timing of sampling the two video signals video1 and video2 input to the sampling pulse generating circuit 201 and the signal line driving circuit 101. Switch) 202. The video signals video1 and video2 are
While the switch 202 is in the ON state, it is held by the capacitances of the corresponding signal lines S1 to Sm (also referred to as “signal line capacitance Csm”).
Here, an example is shown in which the capacitance that each of the signal lines S1 to Sm has is utilized, but a capacitive element (capacitor) may be separately formed for each signal line.

The sampling pulse generating circuit 201 is, for example, as shown in FIG. 3, a shift register composed of a plurality of D flip-flop blocks 301, and
ND circuit 302, and adjacent outputs (for example, Q1 and Q2) of each stage of the shift register are 2 of the AND circuit 302.
Connected to one input.

Next, the operation of the above-mentioned conventional liquid crystal display device 100 will be described.

First, the sampling pulse generation circuit 201
Is based on the input control signal start pulse sp and clock signals ck and ckb as shown in the timing chart of FIG.
1, SAM2, SAM3 ... SAMp are clock signals c
It is sequentially output according to k and ckb.

In the signal line drive circuit 101, the input video signal is doubled on the time axis (2
Video signals video1 and vi that have been expanded on the time axis
deo2 is input and sampling pulse SAM
The ON / OFF of the switch 202 is controlled by 1 to SAMp, and the signal line capacitance Csm which is the capacitance of the signal lines S1 to Sm.
A display signal (a signal corresponding to each pixel in the video signal will be referred to as a display signal) is held in. That is, the switch 202 and the signal line capacitance Csm function as a sample hold circuit.

The display signals (image data) are sequentially output to the signal lines S1 to Sm by the sampling pulses SAM1 to SAMp, and while the display signals (image data) are held by the signal line capacitances Csm, the scanning line driving circuit 102 scans the scanning lines G1. ~ Gn
The TFT 104 connected to the one scanning line selected by the scanning signal output to is activated (ON state), and the display signal written in the signal line capacitance Csm is respectively transmitted via each of the active TFTs 104. It is sequentially stored in the corresponding picture element capacity 105. That is, the image data corresponding to each pixel is written in the pixel.

In this way, the sampling pulse SA
The display signals corresponding to all the signal lines S1 to Sm are sampled at the timing controlled by M1 to SAMp, and the display signals corresponding to all the pixel capacitors 104 connected to one scanning line are written. . After this,
This scanning line is not selected, and the pixel capacitor 104 holds the written display signal until the display signal of the next frame is output (that is, until the horizontal scanning period of the next frame).

By sequentially performing this operation for all the scanning lines G1 to Gn, the display signal corresponding to one frame is held by each of the picture element capacitors 104, and an image for one frame is displayed. . By repeating this operation for each frame, a moving image or the like can be displayed. A driving method in which one frame is divided into a plurality of fields is also known.

Next, the time axis expansion (time axis expansion) of the input video signal will be described.

In the above description, an example in which the input video signal is doubled in the time axis has been described. That is, two display signals (each of which is a part of video signals video1 and video2) are output for each block composed of two signal lines according to each sampling pulse, and p sampling pulses SAM1 to SAMp are sequentially output. , The display signal output operation for each block is sequentially performed p times, and the display signal output operation for all m signal lines S1 to Sm is completed (m = 2p). The display signals output to the signal lines S1 to Sm are held by the signal line capacitors Cs1 to Csm, which are the capacitors of the signal lines S1 to Sm.

A video signal video which has been doubled in time axis.
In o1 and video2, as shown in FIG. 4, the time axis of the input video signal Videoin is doubled. For example, the input video signal videoin is
2 while the sampling pulse SAM1 is in the high state
One display signal (for example, two signals are signal lines S
1 and S2, and these display signals are also referred to as S1 and S2 for simplicity. ) Is included. One video signal vid that has been doubled in time axis
eo1 includes only the display signal S1 while the SAM1 is in the high state, and the other video signal video2 includes only the display signal S2 while the SAM1 is in the high state. In this way, the number of display signals included in each of the video signals video1 and video2 is half the number of display signals in the input video signal videoin, and the period for maintaining the level of each display signal is doubled. .

In this way, by sampling the input video signal from the n video signals which have been time-axis expanded (time-phase expanded to n phases) by n times, the input video signal videooi
The sampling rate (sampling frequency) can be reduced to 1 / n as compared with the case of sampling directly from n. It should be noted that the multiple n of time-axis expansion does not mean that it is the same as the number n of scanning lines.

Generally, when a switch of a signal line driving circuit of a driver monolithic display device is formed by using a polysilicon TFT or the like, the operation speed of the TFT is not sufficient and it is difficult to sample directly from an input video signal. In particular, when the sample hold circuit is configured by using the analog switch and the signal line capacitance, the time constant becomes large, so that the operation speed of the sample hold circuit is limited. As described above, by extending the input video signal on the time axis and reducing the sampling rate, it becomes possible to use the signal line drive circuit whose operation speed is limited.

Next, with reference to FIG. 5, a conventional system configuration and operation for driving a liquid crystal display device using n video signals obtained by time-expanding the input video signal Videoin by n times will be described. In the system shown in FIG. 5, the input video signal Videoin is converted into 12 video signals Video1.
12 to 12 show the case where the time axis expansion is performed (expansion number = 12).

This system includes a timing generator 501 for generating various control signals and an input video signal Vid.
A circuit 502 which receives eoin and performs polarity inversion and contrast / amplitude adjustment, and a timing generator 5.
The polarity inversion video signal output from the circuit 502 is set to 1 based on the sample-hold control signal output from 01.
A sample hold LSI 503 for generating two time-axis-expanded video signals Video 1 to 12, and a driver monolithic liquid crystal display device 504 for receiving and displaying a control signal from the timing generator 501 and a video signal from the sample hold LSI 503. have.

A synchronization signal sync synchronized with the input video signal Videoin is input to the timing generator 501, and the input video signal Videoin is input to the video signal polarity inversion and contrast / amplitude adjusting circuit 502. The timing generator 501 includes various control signals (sp, ck, ckb, spg, ckg, ckg) for driving the signal line driving circuit and the scanning line driving circuit of the liquid crystal display device 504 based on the input synchronization signal sync.
b)) is output to the liquid crystal display device 504. Timing generator 501 outputs to liquid crystal display device 504 1
A control signal for the sample hold LSI for generating the two video signals Video1 to Video12 is generated.

The polarity inversion and contrast / amplitude adjusting circuit 502, as shown in FIG.
idein is converted into a signal whose polarity is inverted every horizontal period, and the amplitude V of the input video signal Videoin is also adjusted (typically amplified) to V1. The purpose of inverting the polarity of the video signal is to prevent deterioration of the liquid crystal material due to application of a DC voltage to the liquid crystal layer.
It may be omitted in an L display device or the like.

The video signal subjected to polarity reversal and amplitude adjustment is input to the sample hold LSI 503, and the sample hold LSI 503 operates as shown in FIG.
Twelve video signals Video1 that have been doubled in time axis
12 is generated and these are output to the liquid crystal display device 504. Since the operation speed for sampling the video signals Video1 to Video12 is 1/12 the operation speed in the case of directly sampling the input video signal Videoin,
The signal line driver circuit of the driver monolithic liquid crystal display device 504 can be sufficiently driven.

[0024]

In the liquid crystal display device using the above-mentioned time-axis-expanded video signal, streaks (generally vertical streaks) along the direction of the signal line may be observed. There are various causes for the generation of the vertical stripes. For example, Japanese Patent Application Laid-Open Nos. 10-83166, 11-271811, 2000-267632, and 5
Japanese Patent Laid-Open No. 35221 proposes a measure for suppressing the generation of vertical stripes that occurs when a signal line drive circuit that performs simultaneous sampling is used.

However, as a result of examination by the present inventor, the vertical streaks seen in the liquid crystal display device using the video signal expanded in the time axis are largely due to the factors described below, and the measures proposed in the above publications are taken. It turns out that can't be suppressed.

The cause of the occurrence of vertical stripes found by the present inventor will be described with reference to FIGS. 8 and 9.

In FIG. 8, the input video signal Videoin is 1
Twelve video signals Video1 to 1 time-doubled
The structure of the conventional liquid crystal display device 200 using 12 (for example, used as the liquid crystal display device 504 of FIG. 5) is shown.

When halftone display is performed on the entire surface of the liquid crystal display device 200, a display area 1 in which a video signal is sampled by the sampling pulse SAM1, a display area 2 in which a video signal is sampled by SAM2, and a video signal is sampled by SAM3. Vertical stripes occur at the boundaries of the respective display areas in the displayed display area 3.

As described above with reference to FIGS. 1 to 4, while the sampling pulse SAM1 is in the high state, the analog switch 202 and the signal line capacitors Cs1 to Cs are used.
The video signals Video1 to Video12 are sampled and held by the sample and hold circuit configured by s12, and a predetermined display signal is written in the pixel capacitance of the display area 1.

After the sample and hold of the video signal by the SAM1 is completed, the sample and hold circuit constituted by the analog switch 202 and the signal line capacitors Cs13 to Cs24 is operated by the sample and hold circuit during the next period when the sampling pulse SAM2 is in the high state. 12 to 12 are sampled and held, and a predetermined display signal is written in the pixel capacitance of the display area 2.

By repeating this operation for one horizontal scanning period, a predetermined display signal is written in all of the picture element capacitors connected to one scanning line (for example, G1) of one frame image. That is, the display signal is sequentially written every 12 signal lines.

Here, the display signal sampled and held on the signal line S12 will be considered.

In response to the sampling pulse SAM1, the display signal of the video signal Video12 (here, a halftone voltage) is sampled and held in the signal line capacitance Cs12 of the signal line S12, and then the display signal is held in a predetermined pixel capacitance. Ideally, it is kept constant without fluctuation (that is, over the one horizontal scanning period).

However, as shown in FIG. 9, there is a parasitic capacitance (due to various conductive layers forming the display unit 103) between adjacent signal lines (for example, Sk and Sk + 1). As a result, the voltage held in the signal line capacitance Csk of the signal line Sk is
It is affected by +1 voltage. That is, the voltage held in the signal line capacitance Csk of the signal line Sk adjacent to the signal line Sk + 1 that samples and holds the display signal changes according to different sampling pulses SAM.

For example, the voltage held in the signal line capacitance Cs12 of the signal line S12 according to the sampling pulse SAM1 is, as shown in FIG.
At the time when the display signal is sample-held in the signal line capacitance Cs13 of the signal line S13 according to AM2, the signal line S12
Fluctuates by ΔV via the coupling by the parasitic capacitance Css12 between S13 and S13. When the display signal output to S13 has a positive polarity, ΔV has a positive value, and when the display signal has a negative polarity, ΔV has a negative value. In addition, the signal lines S1 to 11
Are not adjacent to the signal lines sampled and held according to different sampling pulses SAM, the voltage held in the signal line capacitances of these signal lines 1 to 11 does not change.

The fluctuation amount ΔV of the voltage sampled and held in the signal line capacitance Cs12 of the signal line S12 is equal to the signal line S12.
Signal line capacitance is Cs12, and signal line S12 and signal line S13 are
Let Css12 be the parasitic capacitance between and, and the polarity of the display signal supplied to the signal line S12 be inverted every horizontal scanning period, and the amplitude of this display signal is V1.
It becomes 2 × V1 × Css12 / Cs12. For example, V1
= 4.5V, Css12 = 0.5pf, Cs12 = 9p
If f, then ΔV = 0.5V, and voltage fluctuations that cannot be ignored in terms of display cause signal line S12 (signal line capacitance Cs1
It occurs in 2).

Similarly, when a predetermined display signal is sampled and held on the signal line S24 and then a predetermined display signal is sampled and held on the signal line S25, the voltage sampled and held on the signal line S24 varies by ΔV. That is, the voltage of the signal line (signal line capacitance) from which the display signal is output later to the adjacent signal line changes. In the illustrated configuration, 12
A voltage fluctuation will occur for each signal line of the book, and vertical stripes along the signal lines S12 and S24 will be observed. Here, since a display device in which the total number of signal lines is 36 is illustrated, voltage fluctuation does not occur in the signal line 36 where the sample hold operation is finally performed (see FIG. 10).

In the above description, the sampling pulse SA
M1 to SAM3 are output in this order, and the sample hold is executed for each block in the display areas 1 to 3 from left to right of the display unit 103 in this order.
The order of the output timing of M1 to 3 is reversed (SAM3 → SA
If M2 → SAM1), the longitudinal relationship of the sample and hold operation is reversed, so that vertical stripes along the signal lines S13 and S25 are observed.

The present invention has been made in view of the above points, and its main object is to provide a display device which suppresses the generation of lines parallel to a signal line in a display device which uses a video signal expanded in a time axis, and a drive thereof. To provide a method.

[0040]

In a display device according to the present invention, a plurality of scanning lines, a plurality of signal lines, one for each of the plurality of scanning lines and one of the plurality of signal lines are provided. A display panel including a plurality of connected switching elements, a plurality of pixels each connected to one of the plurality of switching elements, and a scanning line driving circuit that sequentially outputs a scanning signal to the plurality of scanning lines, A signal line driving circuit for outputting a display signal corresponding to a plurality of pixels addressed by the scanning signal to the plurality of signal lines, wherein n video signals obtained by time-expanding an input video signal by n times are sampled. Then, the operation of sequentially outputting, for each block, n display signals corresponding to the sampled n video signals to a plurality of blocks to which n signal lines belong, is repeatedly executed. The display signal is output to all of the plurality of signal lines by, and then the display signal is output after the plurality of signal lines belonging to the block to which the display signal is output first among the adjacent blocks. A signal line drive circuit that selectively outputs a correction signal to a signal line adjacent to a block is provided, thereby achieving the above object.

In a preferred embodiment, each of the display signals is held by a plurality of signal line capacitors, each of which is formed by each of the plurality of signal lines.

It is preferable that a coupling capacitor is provided between the correction signal line for transmitting the correction signal and the signal line for outputting the correction signal.

The signal line drive circuit may have a configuration capable of switching the order of outputting display signals to the plurality of blocks.

Among the plurality of signal lines, among the signal lines belonging to each of the plurality of blocks, a coupling capacitance is provided to each of the signal lines closest to the adjacent block, and the coupling capacitance is provided to the plurality of blocks. It is preferable that the signal line from which the correction signal is output is selected according to the order in which signals are output.

A correction signal switch is provided between each of the coupling capacitors and the correction signal wiring for transmitting the correction signal, and the signal line to which the correction signal is output is selected by the correction signal switch. It is preferable to have a configuration.

The signal line drive circuit has a plurality of switches between n video signal lines for transmitting the n video signals and a plurality of display signal output terminals for outputting the display signals, It is preferable that the time constants determined by the ON resistances of the plurality of switches and the plurality of signal line capacitances are substantially the same for all of the plurality of signal lines.

The capacitance of the coupling capacitance is 1 of the capacitance of the signal line capacitance of the signal line to which the coupling capacitance is connected.
It is preferably 1/0 or less.

The time constant may be adjusted by the ON resistance of the switch and / or the channel width / gate length ratio of the TFT included in the switch.

The correction signal preferably has two voltage levels, and the two voltage levels are variable.

The signal line drive circuit is preferably formed integrally with the display panel.

According to the driving method of the display device of the present invention, a plurality of scanning lines, a plurality of signal lines, and each of them are connected to one of the plurality of scanning lines and one of the plurality of signal lines. A display panel including a plurality of switching elements and a plurality of pixels, each of which is connected to one of the plurality of switching elements; a scanning line driving circuit which sequentially outputs a scanning signal to the plurality of scanning lines; And a signal line driving circuit for outputting display signals corresponding to a plurality of pixels addressed by the plurality of signal lines to the plurality of signal lines, wherein n input image signals are time-expanded n times. Step of sampling the video signal of, and n display signals corresponding to the sampled n video signals are sequentially output for each block to a plurality of blocks to which n signal lines belong. The step of outputting the display signal to all of the plurality of signal lines by repeatedly performing the step of, and then the plurality of signal lines belonging to the block to which the display signal is first output among the blocks adjacent to each other. And a step of selectively outputting a correction signal to a signal line adjacent to a block to which a display signal has been output after that, thereby achieving the above object.

[0052]

BEST MODE FOR CARRYING OUT THE INVENTION A display device and a driving method thereof according to embodiments of the present invention will be described below. Hereinafter, an embodiment in which the present invention is applied to the above-described driver monolithic liquid crystal display device will be described, but the present invention is not limited to this.
It can be applied to other liquid crystal display devices and display devices other than liquid crystal display devices (for example, organic EL display devices). That is, the present invention can be widely applied to display devices having a configuration in which a display signal applied to a pixel is at least temporarily held in a capacitor. Further, each pixel may be connected to the scanning line and / or the signal line via two or more switching elements.

Further, the liquid crystal display device of the embodiment according to the present invention performs display by using a video signal obtained by expanding the input video signal on the time axis, similarly to the above-mentioned liquid crystal display device, and a configuration and a drive therefor. The methods can be common. Therefore, the step of performing the time-axis expansion processing of the input video signal and the sample-hold processing of the time-axis expanded video signal and the configuration therefor are the same as those of the liquid crystal display device described above.
The description is omitted here.

The circuit for generating a video signal obtained by expanding the input video signal on the time axis may be generally provided separately from the display device, but may be incorporated in the display device depending on the application. For example, in the case of a driver monolithic type display device in which a signal line driving circuit (and a scanning signal driving circuit) is integrated with a display panel, the display panel may be mounted using TAB or the like.

The liquid crystal display device according to the embodiment of the present invention is
Similar to the conventional liquid crystal display device described above, the sampling signals SAM1 to SA for the video signal which is time-axis expanded to n times
The operation of sequentially outputting the n display signals corresponding to the n video signals sampled by Mp to a plurality of blocks (sampling blocks) to which n signal lines belong to each block is repeated. By executing this, the display signal is output to all the signal lines. The display voltage output to the signal line is typically held by the signal line capacitance that is the capacitance of the signal line, and the voltage is held in the corresponding pixel capacitance.

The liquid crystal display device of the embodiment has a function of outputting a correction signal in order to suppress the generation of lines appearing parallel to the signal lines in the above-mentioned conventional liquid crystal display device. According to the study by the present inventor, as described above, in the above-described streak, the display signal is output after the plurality of signal lines belonging to the block to which the display signal is first output among the adjacent blocks. This occurs because the voltage of the signal line adjacent to the block fluctuates (ΔV), so that the correction signal is selectively output to the signal line that receives this voltage fluctuation.
The correction signal is typically output all at once to the signal lines that have undergone the voltage fluctuation after the hold operation of the display signal for one horizontal period is completed. With this correction signal, it is possible to cancel the voltage fluctuation of the signal line and suppress the occurrence of streaks.

The correction signal is preferably output to the signal line via the coupling capacitance. By adjusting the capacitance value of the coupling capacitance, the amplitude of the correction signal output to the signal line can be adjusted to a magnitude that cancels the voltage fluctuation. Further, by outputting the correction signal to the signal line via the coupling capacitance, it is possible to suppress the variation in the amount of charge held in the signal line capacitance. Note that the circuit element for suppressing the variation in the amount of charge held in the signal line capacitance is not limited to the coupling capacitance.

When a switch (typically an analog switch) is used to control the timing of the sample hold operation for each block, the time required for each signal line capacitance to reach a predetermined voltage (that is, each switch). And a signal line capacitance connected to the sampling circuit are sometimes referred to as sampling circuit time constants and sampling time constants.) Are switch on-resistance values and respective signal line capacitances (capacitance values). Depends on. When the coupling capacitance is coupled to the signal line, the time required for the coupling capacitance coupled signal line capacitance to reach a predetermined voltage becomes longer than other signal line capacitances, and as a result, the coupling capacitance coupled signal line is connected. There may occur a problem that the voltage (charge rate) held in the capacity becomes low. In order to suppress the occurrence of this problem, it is preferable that the time until the signal line capacitance reaches a predetermined voltage be substantially the same for all the signal line capacitances.

Adjustment of the sampling time constant for each signal line is as follows.
The ON resistance of the switch that controls the timing of sampling and / or the switch having a TFT can be adjusted by the channel width (W) / gate length (L) of the TFT.

If the electrostatic capacitance of the coupling capacitance is set to about 1/10 of the electrostatic capacitance of the signal line capacitance, the sampling time constants will not be extremely different, and at the block boundary which is the unit of the sample hold operation. It is possible to effectively suppress the generation of muscle due to the generated voltage fluctuation.

The order in which the signal line driving circuit outputs the display signal for each block may be switched. When this configuration is adopted, the correction signal is selectively output to the signal line that receives the voltage fluctuation according to the order in which the display signals are output. In addition, the correction signal is preferably output to the signal line via the coupling capacitance as described above. Therefore, in the liquid crystal display device in which the output order of the display signals can be switched, among the plurality of signal lines, among the signal lines belonging to each of the plurality of blocks, the coupling capacitance is respectively provided to the signal line closest to the adjacent block. Is provided, and the signal line to which the correction signal is output is selected according to the order in which the display signals are output to the plurality of blocks. Further, it is preferable that a correction signal switch is provided between each of the correction signal wiring for transmitting the correction signal and the coupling capacitor, and the signal line to which the correction signal is output is selected by the correction signal switch. .

In general, the polarity of the display signal is inverted so that the DC voltage is not applied to the liquid crystal layer of the liquid crystal display device (for example, the polarity is inverted every horizontal period as shown in FIG. 6). Therefore, it is preferable that the correction signal also has two voltage levels and that the two voltage levels are alternately switched in synchronization with the polarity inversion of the display signal. The two voltage levels are typically of different polarities. Also, depending on the characteristics of the liquid crystal material, it is possible to suppress the generation of streaks,
The voltage level is preferably variable.

The liquid crystal display device according to the embodiment of the present invention is
It is preferable that the signal line driver circuit (and the scan line driver circuit) be formed integrally with the display panel. When formed integrally with the display panel, a TFT formed of a semiconductor material having a relatively low mobility, such as polysilicon, is used as a switch of the signal line driving circuit. A driving method using a video signal expanded in the time axis is adopted. The multiple of the time extension is appropriately set according to the operation speed of the switch and the application of the liquid crystal display device. By forming a switch for driving a signal line and a switching element for a pixel of a display panel by using continuous grain boundary crystal silicon, a driver monolithic liquid crystal display device having a high operation speed can be realized (for example, Japanese Patent Laid-Open Publication No. 7-58242). (See Japanese Patent Publication No. 161634).

Hereinafter, the configuration and operation of the liquid crystal display device according to the embodiment of the present invention will be described in more detail with reference to the drawings.

FIG. 11 schematically shows the structure of the liquid crystal display device 600 of the embodiment according to the present invention. Liquid crystal display device 60
0 is a block each including 12 signal lines, like the conventional liquid crystal display device 200 shown in FIG. 8 (each of display area 1 to display area 3 corresponds to one block).
The operation of sampling and holding the video signals Video1 to Video12 is performed every time. The video input signals Video 1 to 12 are signals obtained by expanding the input video signal Videoin 12 times in the time axis. Like the liquid crystal display device 200, the total number of signal lines of the liquid crystal display device 600 is 36.

As described above, when the liquid crystal display device 200 shown in FIG. 8 performs the sample hole operation in the order of SAM1 to SAM3, vertical stripes due to the voltage fluctuation ΔV are generated for every 12 signal lines (for example, S12 and S24). Occur. On the other hand, in the liquid crystal display device 600 shown in FIG. 11, the correction signal Vc selectively supplied to the signal lines (S12 and S24) that receive the voltage fluctuation cancels the voltage fluctuation ΔV and suppresses the generation of vertical stripes. To be done. The coupling capacitance (Cc) 80 is connected to the signal line that receives the voltage fluctuation ΔV by the connection wiring 804.
2 is connected, and the other end of the coupling capacitor 802 is connected to the correction signal line 801.

The operation of the liquid crystal display device 600 will be described with reference to FIG. 12 together with FIG.

After the display signal of the video signal Video12 is sampled and held in the signal line capacitance Cs12 of the signal line S12 according to the sampling pulse SAM1, the display signal of the video signal Video1 is sampled and held in the signal line capacitance Cs13 of the signal line S13 according to the sampling pulse SAM2. Then, the voltage corresponding to the display signal sampled and held in the signal line capacitance Cs12 changes by ΔV as shown in FIG. Similarly, the signal line capacitance Cs2 of the signal line S24
The voltage sampled and held at 4 is also affected by the voltage sampled and held at the signal line capacitance Cs25 of the signal line S25, and changes by ΔV. As described above, when the sample-hold operation of the display signal corresponding to one horizontal scanning period is completed, the signal lines of the signal lines (S12 and S24) adjacent to the signal lines of the adjacent blocks among the signal lines in each block. The voltage held in the capacitors Cs12 and Cs24 is Δ
V changes.

The signal line drive circuit 601 of the liquid crystal display device 600 of the present embodiment supplies the correction signal Vc to the signal lines (S12 and S24) which have been subjected to voltage fluctuation at this point through the coupling capacitance Cc802. Here, by appropriately setting the amplitude of the correction signal Vc and the value of the coupling capacitance Cc802, it is possible to cancel the voltage fluctuation that occurs at the boundary of the blocks (display areas) in which simultaneous sampling is performed.

When the polarity of the correction signal Vc is inverted every horizontal scanning period in synchronization with the polarity inversion of the video signal, and its amplitude (maximum-minimum) is V2, the signal lines S12 and S24.
When the electrostatic capacitance of the coupling capacitance Cc is Cc and the signal line capacitance Csm of the signal lines S12 and S24 is Csm (= Cs12 = Cs24), the correction voltage ΔVc actually supplied to
Vc = (Cc / Csm) × V2.

Here, the electrostatic capacitance Cc of the coupling capacitance Cc is
Relative arrangement (overlapping amount, etc.) of various conductive layers formed on the substrate of a liquid crystal display device (generally, an insulating substrate such as glass or quartz, or a substrate such as a silicon wafer) and the thickness of the conductive layer or insulating layer It is adjusted by controlling the.

The signal line capacitance Csm changes not a little under the conditions such as the liquid crystal material and the cell gap (thickness of the liquid crystal layer). When the signal line capacitance Csm changes, the ratio between the parasitic capacitance Css between the signal lines and the signal line capacitance Csm changes.
The voltage fluctuation ΔV also changes. Therefore, it is preferable to have a configuration in which the amplitude V2 of the correction signal can be changed so as to cope with the change in the voltage change ΔV due to the change in the type of liquid crystal material or the cell gap.

By the way, the correction voltage ΔVc is supplied to the signal line S12.
And S24, the signal lines S12 and S24
Voltage fluctuates, and the voltage of the signal lines on both sides of the voltage fluctuates, but this fluctuation amount is small and does not adversely affect the display.

For example, when the correction voltage of ΔVc is supplied to the signal line S12, the parasitic capacitance Css (= Cs between the signal lines).
s11, Css12) via signal lines S11 and S
The fluctuation ΔV ′ of the voltage generated at 13 is ΔV ′ = ΔVc ×
It becomes Css / Csm. The above value Css = 0.5 pf,
If Csm = 9 pf and ΔVc = 0.5 V, then ΔV ′ =
0.5 × 0.5 / 9 = 0.035V, and ΔVc (Δ
It is sufficiently smaller than V).

Signal lines that receive voltage fluctuations (S12 and S
If the coupling capacitor Cc 802 is connected only to 24), the analog switch 202 forming the signal line driving circuit 601 and the signal line Sm forming the display unit 103 (signal line capacitance Csm).
There is a difference in the time constant of the sample hold circuit composed of and, and as a result, vertical stripes may be visually recognized. This is the signal line (S12 and S12) to which the coupling capacitance Cc is connected.
This is because the capacitance of the sample-hold circuit path including 24) increases by the coupling capacitance Cc, and as a result, the time constant of the sample-hold circuit (the time required to reach a predetermined voltage) increases.

The difference in the time constant of the sample hold circuit can be eliminated by adjusting the ON resistance of the analog switch 202 of the sample hold circuit.
For example, the coupling capacitance Cc802 is connected to connect to the signal line (S1
2 and S24), the W / L ratio of the TFT of the analog switch 202 of the sample and hold circuit is calculated as follows: W / L of the TFT of the analog switch 202 of the sample and hold circuit of the signal line to which the coupling capacitance Cc802 is not connected.
It should be increased with respect to the ratio of.

Further, the electrostatic capacitance of the coupling capacitance Cc is sufficiently smaller than the electrostatic capacitance of the signal line capacitance Csm, for example, 1 /.
By setting it to about 10 or less, the time constants of all the sample and hold circuits can be made substantially the same, so that it is possible to prevent a difference in the charging rate when writing the display signal. In general, the time constant of the sample hold circuit is set sufficiently short for one horizontal scanning period, so charging is performed by setting the capacitance of the coupling capacitance Cc to about 1/10 of the capacitance of the signal line capacitance Csm. The difference in the rates can be set to a level that causes no practical problems.

Next, the structure and operation of the liquid crystal display device 700 according to another embodiment of the present invention will be described with reference to FIG. The same components of the liquid crystal display device 700 as those of the liquid crystal display device 600 are designated by the same reference numerals, and the description thereof will be omitted here.

The signal line drive circuit 601 of the liquid crystal display device 600 (FIG. 11) scans the blocks (display areas 1 to 3) for performing the sample hold operation from left to right, and suppresses the generation of vertical stripes in that case. Therefore, a configuration for outputting a correction signal to the signal lines S12 and S24 is provided. However, in this signal line scanning circuit 601, the two directions are reversed (that is, SAM3 → SAM2 → SAM1).
In this case, it is not possible to suppress the generation of vertical stripes that occur in parallel to the signal lines S25 and S13.

The signal line drive circuit 701 of the liquid crystal display device 700 shown in FIG. 13 has a structure capable of suppressing the generation of vertical stripes in response to bidirectional scanning.

In the signal line drive circuit 701, as shown in FIG. 13, the signal lines S12 and 13 and S24 and S25 are
It is connected to the correction signal line 801 via a coupling capacitor 802, and an analog switch 902 for a correction signal is provided between the correction signal line 801 and the coupling capacitor 802.

The analog switch 902 is ON / OFF controlled by the scanning direction signal SD supplied from the scanning direction signal line 901. The scanning direction signal SD is, for example, in a high state when the scanning direction is from left to right and in a low state when the scanning direction is from right to left.

Swr is connected to the coupling capacitances of the signal lines S12 and S24, and Swl is connected to the coupling capacitances of the signal lines S13 and S25. Swr is in the on state when the scanning direction signal SD is in the high state, and at this time, Swl is in the off state. A signal obtained by inverting the scanning direction signal SD is input to Swl, and is turned on when the scanning direction signal SD is low, and at this time, Swr is in the off state.

Therefore, when the scanning direction is from left to right,
When the correction signal Vc is selectively supplied to the signal lines S12 and S24 and the scanning direction is from right to left, the signal line S25
And the correction signal Vc is selectively supplied to S13. That is, the generation of vertical stripes is suppressed regardless of the scanning direction.

Note that S1 to S11, S at the time of scanning from left to right
The voltage held in each of 13 to S23, S25 to S36, and S1 to S12, S14 to S24, and S26 to S36 during right-to-left scanning should be affected by the voltage of the signal line adjacent to each of them and fluctuate. There is no.

In the above embodiment, the coupling capacitance Cc for inputting the correction signal is provided on the opposite side of the signal line from the signal line drive circuit. However, the coupling capacitance Cc is driven by the signal line. It may be provided on the same side as the circuit. In this case, the coupling capacitance may be connected to the signal line in parallel with the switch of the signal line drive circuit.

[0087]

According to the present invention, there are provided a display device and a driving method capable of suppressing the generation of lines parallel to the signal lines in a display device using a video signal expanded in the time axis.

The present invention is suitably applied to a driver monolithic liquid crystal display device and an organic EL display device, and the display quality can be improved.

[Brief description of drawings]

FIG. 1 is a diagram schematically showing a configuration of a conventional driver monolithic liquid crystal display device.

FIG. 2 is a diagram schematically showing a configuration of a signal line drive circuit included in a conventional driver monolithic liquid crystal display device.

FIG. 3 is a diagram schematically showing a configuration of a sampling pulse generation circuit included in a conventional signal line drive circuit.

FIG. 4 is a diagram for explaining the operation of a signal line drive circuit of a conventional driver monolithic liquid crystal display device.

FIG. 5 is a diagram schematically showing a drive system of a conventional liquid crystal display device.

FIG. 6 is a diagram schematically showing a video signal waveform input to a sample hold LSI of a drive system for a conventional liquid crystal display device.

FIG. 7 is a diagram schematically showing a video signal input to a sample hold LSI of a drive system for a conventional liquid crystal display device and a video signal which is time-axis expanded 12 times by the sample hold LSI.

FIG. 8 is a diagram schematically showing a conventional liquid crystal display device.

FIG. 9 is a schematic diagram for explaining capacitive coupling between signal lines of a liquid crystal display device.

FIG. 10 is a schematic diagram for explaining a voltage fluctuation ΔV that causes vertical stripes in a conventional liquid crystal display device.

FIG. 11 is a diagram schematically showing a liquid crystal display device according to an embodiment of the present invention.

FIG. 12 is a schematic diagram for explaining that the voltage fluctuation ΔV that causes vertical stripes is suppressed in the liquid crystal display device of the present invention.

FIG. 13 is a diagram schematically showing another liquid crystal display device according to an embodiment of the present invention.

[Explanation of symbols]

100, 200, 600, 700 Liquid crystal display device 101 Signal line drive circuit (data driver) 102 Scan line drive circuit (gate driver) 103 Display unit 201 Sampling pulse generation circuit 202 Analog switch 601, 701 Signal line drive circuit 801 Correction signal line 802 (Cc) Coupling capacitance 901 Scanning direction signal line 902 (Swr, Swl) Analog signal correction switches G1 to Gn Scanning lines S1 to Sm Signal lines Cs1 to Cs36 Signal line capacitance Css Parasitic capacitance between signal lines

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) G09G 3/20 G09G 3/20 623M 641 641P 642 642A F term (reference) 2H093 NA13 NA16 NA31 NC02 NC09 NC11 NC23 NC34 NC35 ND31 ND41 5C006 AC22 AF43 AF46 BB14 BB15 BC13 BC16 BC20 BC23 BF11 BF24 BF34 BF37 FA22 5C080 AA10 BB06 DD05 EE28 FF11 JJ02 JJ03 JJ04

Claims (12)

[Claims] 1. A plurality of scanning lines, a plurality of signal lines, and a plurality of switching elements each connected to one of the plurality of scanning lines and one of the plurality of signal lines, respectively. A display panel including a plurality of pixels connected to one of the plurality of switching elements; a scan line driving circuit that sequentially outputs a scan signal to the plurality of scan lines; and a plurality of pixels addressed by the scan signal. A signal line drive circuit for outputting a corresponding display signal to the plurality of signal lines, the input video signal being n times time-axis expanded.
N video signals are sampled and sampled
N display signals corresponding to n video signals
A display signal is output to all of the plurality of signal lines by repeatedly performing an operation of sequentially outputting each block to the plurality of blocks to which the one signal line belongs, and then displaying first among the blocks adjacent to each other. A signal line drive circuit that selectively outputs a correction signal to a signal line adjacent to a block to which a display signal has been output after a plurality of signal lines belonging to the block to which a signal has been output; apparatus. 2. The display device according to claim 1, wherein each of the display signals is held by a plurality of signal line capacitors formed by each of the plurality of signal lines. 3. The display device according to claim 1, wherein a coupling capacitance is provided between a correction signal line for transmitting the correction signal and the signal line for outputting the correction signal. 4. The signal line driving circuit can switch the order of outputting display signals to the plurality of blocks,
The display device according to claim 1. 5. Among the plurality of signal lines, among the signal lines belonging to each of the plurality of blocks, a signal line closest to an adjacent block is provided with a coupling capacitance, and the plurality of blocks are provided. The display device according to claim 4, wherein the signal line to which the correction signal is output is selected according to the order in which the display signal is output to the display device. 6. A correction signal switch is provided between each of the correction signal wiring for transmitting the correction signal and the coupling capacitor, and the signal line to which the correction signal is output is selected by the correction signal switch. The display device according to claim 5, wherein 7. The signal line drive circuit has a plurality of switches between n video signal lines for transmitting the n video signals and a plurality of display signal output terminals for outputting the display signals. The time constants determined by the ON resistances of the plurality of switches and the plurality of signal line capacities are substantially the same for all of the plurality of signal lines.
7. The display device according to any one of 6 and 6. 8. The display device according to claim 7, wherein the time constant is adjusted by an ON resistance of the switch and / or a channel width / gate length ratio of a TFT included in the switch. 9. The electrostatic capacitance of the coupling capacitance is 1/10 or less of the electrostatic capacitance of the signal line capacitance of the signal line to which the coupling capacitance is connected, and any one of claims 3 and 5 to 8 The display device according to claim 1. 10. The display device according to claim 1, wherein the correction signal has two voltage levels, and the two voltage levels are variable. 11. The display device according to claim 1, wherein the signal line drive circuit is formed integrally with the display panel. 12. A plurality of scanning lines, a plurality of signal lines, and a plurality of switching elements each connected to one of the plurality of scanning lines and one of the plurality of signal lines,
A display panel including a plurality of pixels each connected to one of the plurality of switching elements, a scan line driving circuit that sequentially outputs a scan signal to the plurality of scan lines, and a plurality of address lines addressed by the scan signals. A driving method of a display device, comprising: a signal line driving circuit for outputting a display signal corresponding to a pixel to the plurality of signal lines, wherein n video signals obtained by time-expanding an input video signal by n times are sampled. By repeatedly performing the step and the step of sequentially outputting the n display signals corresponding to the sampled n video signals to a plurality of blocks to which the n signal lines belong, for each block, The step of outputting the display signal to all of the plurality of signal lines, and then the plurality of signals belonging to the block to which the display signal is first output among the blocks adjacent to each other. Including the steps of outputting selectively the correction signal to the signal line adjacent to the block to which the display signal is outputted later of the line, the driving method of the display device.