JP2003188151A - Method for manufacturing semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve the performance of a semiconductor integrated circuit by adequately removing a resist film, especially a resist film which is formed as a mask for ion implantation step. <P>SOLUTION: A resist film R6 is formed in a p-channel-type MISFET forming region (pMIS forming region) of a semiconductor substrate 1 and an n<SP>+</SP>-type semiconductor region 14 (source and drain) which is a region of impurities in higher concentration than an n<SP>-</SP>-type semiconductor region 11 is formed by implanting phosphorous (P) ions by using the resist film R6, gate electrodes G and side wall spacers 13 as a mask. After that, the resist film R6 is removed (ashing) by using NH<SB>3</SB>as an ashing gas and at 120°C or lower. In consequence, a degenerated film R6a formed on the surface of the resist film R6 by the ion implantation can be removed and the degradation of characteristics of the semiconductor integrated circuit device due to the generation of foreign materials or the cleaning for removing the foreign materials can be prevented. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for manufacturing a semiconductor integrated circuit device, and more particularly to a technique effectively applied to a technique for removing a photoresist film.

[0002]

2. Description of the Related Art MISFET (Metal Insulator Semico)
A semiconductor integrated circuit having a semiconductor element such as an nductor field effect transistor) is formed by repeating patterning of a conductive film such as a metal film or an insulating film. At the time of patterning these, a photoresist film (hereinafter, simply referred to as “resist film”) formed on a metal film or an insulating film is formed into a desired shape by using a photolithography technique, and the resist film is used as a mask. The underlying film is patterned by etching.

[0003]

The resist film is also used when forming an impurity region (semiconductor region) which constitutes a semiconductor element.

That is, the resist film in the region where the impurities are to be ion-implanted is removed, and the resist film is ion-implanted using the mask as a mask, so that the impurities are ion-implanted only in a desired region.

After that, the resist film is removed by an ashing process. What is this ashing process?
Mainly, in a gas phase, a resist film made of carbon or hydrogen,
This is a process of reacting with a reactive gas (oxygen radical) having a strong oxidizing power such as oxygen or ozone to form a volatile reaction product, and then exhausting and removing it.

However, as described above, ions are implanted in the resist film used as a mask in the ion implantation process, and there is a problem that ashing processing is difficult.

Although the details will be described in the section of the embodiment of the invention, the resist film which is deteriorated by the ion implantation is left by the so-called popping phenomenon.

In order to remove this residue, for example, when the semiconductor substrate is cleaned with a mixed solution of ammonia and hydrogen peroxide (NH ₃ + H ₂ O ₂ ) or a hydrofluoric acid-based cleaning solution, the substrate itself or the The exposed portions such as the insulating film on the substrate surface are etched, and the characteristics of the semiconductor element formed on the substrate surface are deteriorated.

An object of the present invention is to accurately remove a resist film, particularly a resist film used as a mask in an ion implantation process.

Another object of the present invention is to improve the performance of a semiconductor integrated circuit device.

Another object of the present invention is to improve the yield of semiconductor integrated circuit devices.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0013]

Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.

(1) A method of manufacturing a semiconductor integrated circuit device according to the present invention comprises (a) a step of forming a resist film on a semiconductor substrate, and (b) a step of performing ion implantation using the resist film as a mask. c) a step of removing the resist film with a gas containing NH ₃ after the step (b). This step (c) may be performed at a temperature of the semiconductor substrate of 120 ° C. or lower. Further, such temperature control can be performed by fixing the semiconductor substrate on the stage by electrostatic attraction and flowing a gas between the stage and the semiconductor substrate.

The resist film is, for example, a film containing carbon or hydrogen. Further, the ions are composed of P (phosphorus), As (arsenic), B (boron) or a boron compound. Further, the ion implantation location may be in the semiconductor substrate, or in the semiconductor film or the metal film formed on the semiconductor substrate. Further, the gas may be a gas having good thermal conductivity such as He (helium) gas.

(2) In the method of manufacturing a semiconductor integrated circuit device of the present invention, (a) a step of forming a resist film on a semiconductor substrate, (b) a step of performing ion implantation using the resist film as a mask ( c) a step of removing the resist film using a gas containing NH ₃ after the step (b), wherein (c ₁ ) after removing the surface of the resist film at the first temperature, ₂ ) A step of removing the resist film at a second temperature higher than the first temperature.

The steps (c ₁ ) and (c ₂ ) are
It may be performed in different processing chambers. Further, in the step (c ₁ ), the high frequency bias may be applied to the semiconductor substrate, and in the step (c ₂ ), the high frequency bias may not be applied to the semiconductor substrate to perform the treatment.
The applied high frequency bias is 300 kHz to 20
In MHz, the difference between the maximum and minimum applied voltage is
It can be 0.5 kV or less.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted.

(Embodiment 1) FIGS. 1 to 13 are cross-sectional views of a main part of a substrate showing a method for manufacturing a semiconductor integrated circuit device according to the present embodiment.

A method of manufacturing the semiconductor integrated circuit device according to the present embodiment will be described in the order of steps with reference to FIGS.

First, as shown in FIG. 1, after the semiconductor substrate 1 is etched to form a groove, a silicon oxide film 7 is embedded in the groove to form an element isolation 2.

Next, as shown in FIG. 2, a resist film R1 is formed on the substrate 1, and a p-channel type MISFET formation region (p is formed by photolithography (exposure / development)).
The resist film R1 is left only on the MIS formation region). Next, p-type impurities (for example, boron (B)) are ion-implanted using the resist film R1 as a mask.

Next, after removing the resist film R1 by ashing using oxygen or ozone, the resist film is formed on the n-channel type MISFET formation region (nMIS formation region) by photolithography as shown in FIG. Form R2. Then, using the resist film R2 as a mask, an n-type impurity (for example, phosphorus (P)) is ion-implanted.

Next, the resist film R2 is removed by ashing using oxygen or ozone, and then heat treatment is performed to diffuse the impurities, so that as shown in FIG. n-type well 4
To form.

Next, as shown in FIG. 5, after the surface of the substrate 1 (p-type well 3 and n-type well 4) is wet washed, the surface of each of the p-type well 3 and the n-type well 4 is thermally oxidized. Then, a clean gate oxide film 8 is formed.

Next, a low resistance polycrystalline silicon film 9 is formed on the gate oxide film 8 by CVD (Chemical Vapor Deposition).
Of the resist film R on the polycrystalline silicon film 9 after being deposited by the
3 is formed, and as shown in FIG. 6, the resist film R3 is formed only in the region where the gate electrode is formed by photolithography.
To remain.

Then, the polycrystalline silicon film 9 is dry-etched using the resist film R3 as a mask,
The gate electrode G is formed.

Next, after removing the resist film R3 by ashing using oxygen or ozone, as shown in FIG. 7, the resist film is formed on the p-channel type MISFET formation region (pMIS formation region) by photolithography. Form R4. Then, phosphorus (P) ions are ion-implanted using the resist film R4 and the gate electrode G as a mask to form the n ⁻ type semiconductor region 11.

Next, after removing the resist film R4 by ashing using oxygen or ozone, as shown in FIG. 8, the resist film is formed on the n-channel type MISFET formation region (nMIS formation region) by photolithography. Form R5. Then, the p ⁻ type semiconductor region 12 is formed by implanting boron (B) ions with the resist film R5 and the gate electrode G as a mask.

Next, the resist film R5 is removed by ashing using oxygen or ozone, a silicon nitride film is deposited on the substrate 1 by the CVD method, and then anisotropically etched to obtain the structure shown in FIG. As shown, the sidewall spacers 13 are formed on the sidewalls of the gate electrode G.

Next, as shown in FIG. 10, a resist film R6 having a film thickness of about 1 μm is formed on the p-channel type MISFET formation region (pMIS formation region) by photolithography. Then, using the resist film R6, the gate electrode G and the sidewall spacers 13 as a mask, phosphorus (P) ions are applied at an energy of 50 keV.
The n ⁺ type semiconductor region 14 (source, drain) which is an impurity region having a higher concentration than the n ⁻ type semiconductor region 11 is formed by ion implantation at about 5 × 10 ¹⁵ / cm ² .

Next, the resist film R6 is removed by ashing, but it is removed by the following method.

First, the semiconductor substrate 1 shown in FIG. 10 is carried into the ashing device shown in FIG. 23 or 24, for example, and processed.

As the ashing device, there are a downflow type ashing device (single wafer type) shown in FIG. 23 and a barrel type ashing device (batch type) shown in FIG.

As shown in FIG. 23, in the downflow type ashing apparatus, the semiconductor substrate (wafer W) is placed on the stage St in the quartz tube 201. Wafer W
An electrode plate PL1 for generating plasma on the upper part of the
PL2 are provided so as to face each other, and these electrode plates P
Inflow gas G by applying an electric field between L1 and PL2
a is excited and promotes the ashing reaction.

In the barrel type ashing apparatus shown in FIG. 24A, a plurality of wafers W can be stored by the holder 302. Inside and outside the side wall of the quartz tube 301,
Electrode plates PL1 and PL2 for generating plasma are coaxially provided, and these electrode plates PL1 and PL2 are provided.
The inflow gas Ga is excited by applying an electric field therebetween. Radicals enter inside through the holes h opened in the electrode plate PL1 and promote the ashing reaction. Figure 24 (b)
And (c) are diagrams schematically showing the cross section of FIG. 24 (a) and the electrode plate PL1 shown in FIG. 24 (a), respectively.
FIG. 23 and 24, the inflow gas Ga is injected from the inlet IN and exhausted from the outlet OUT.

First, a process using the barrel type ashing device shown in FIG. 24 will be described.

The semiconductor substrate 1 (wafer W) shown in FIG. 10 is placed in the apparatus, and ashing is performed while NH ₃ (ammonia) gas is injected as the inflow gas Ga.

At this time, for example, the conditions shown in FIG. 26A, NH ₃ flow rate 1500 ml / min, pressure 160 P
a, source power 1000 W, initial temperature in the device 70 ° C.
The ashing was performed under the conditions of. Here, the source power indicates high frequency power applied to the electrode plate PL2.
Here, the bias power is not applied to the semiconductor substrate 1. During the removal of the resist film, ashing was performed without changing the above conditions.

As described above, since NH ₃ is used as the ashing gas in the present embodiment, the ashing of the resist film R6 can be appropriately performed by the hydrogen nitride radicals or hydrogen radicals generated in the apparatus.

That is, since the resist film R6 covers the surface of the semiconductor substrate 1 at the time of implanting phosphorus (P) ions, phosphorus (P) ions are implanted on the surface, as shown in FIG. The altered layer R6a is formed. It is considered that this is because the crosslinking reaction occurs mainly when impurities such as phosphorus (P) enter into the resist film made of hydrocarbon (carbon or hydrogen) or the like. When such a reaction occurs, the surface of the resist film and the portion where the phosphorus (P) ions are implanted (R6a portion) are hardened, and it is difficult to remove them by ashing using oxygen or ozone, for example.

Further, if ashing using oxygen or ozone is performed in such a state, as shown in FIG. 29, the resist film R6 inside the altered layer R6a is vaporized and volume-expanded, so that the hard film is hardened. Part of the deteriorated layer R6a is vaporized and burst (FIG. 30), and as shown in FIG. 31, the deteriorated layer R6a
The foreign matter composed of a is scattered on the semiconductor substrate 1 (popping phenomenon).

On the other hand, for example, as shown in FIG. 32, for a resist film R6 having an altered layer R6a formed on its surface,
In order to suppress the occurrence of the popping phenomenon, as shown in FIGS. 33 and 34, it may be possible to perform ashing using oxygen or ozone at a relatively low temperature. However, when oxygen or ozone is used as the ashing gas, the oxygen radicals oxidize the bonds between the molecules forming the resist film and the impurities (in this case, phosphorus (P)), and further, it is difficult to remove the deteriorated layer R6b. Becomes Therefore, the altered layer R6b
Is difficult to remove, and as shown in FIG. 34, the altered layer R6b remains on the semiconductor substrate 1.

In addition, such altered layers (R6a, R6
The foreign matter consisting of b) can be removed by a mixed solution of ammonia and hydrogen peroxide water (NH ₃ + H ₂ O ₂ ) or a hydrofluoric acid-based cleaning solution.
It also etches itself. When the substrate surface recedes in this way, the characteristics of the MISFET are deteriorated, for example, the n ⁺ type semiconductor region 14 (source and drain) becomes shallow and the current flowing between the source and drain becomes small.

Further, the latter cleaning causes the surface of the silicon oxide film 7 constituting the element isolation 2 to recede (so-called recess phenomenon) due to the cleaning, thereby degrading the characteristics of the MISFET. For example, when a gate electrode or the like crosses such a recess portion, it causes a decrease in gate breakdown voltage. In addition, the separation becomes insufficient and the junction leak current increases.

The problem of the scraping of the surface of the semiconductor substrate 1 and the element isolation 2 becomes larger as the element becomes finer, and the cleaning step cannot be performed.

However, according to the present embodiment, since NH ₃ is used as the ashing gas, the resist film mainly composed of hydrocarbon (carbon, hydrogen) is used as the cyanide compound (for example, hydrogen cyanide (CNH)). Not only can it be removed, but P (phosphorus) in the altered layer can be vaporized as phosphorus hydride (for example, PH ₃ ). In this way, the deteriorated layer R6a can be positively vaporized.

Therefore, the cleaning step for removing the deteriorated layer can be omitted or the cleaning time can be reduced, and the above-mentioned problems caused by etching the surface of the semiconductor substrate 1 and the element isolation 2 can be avoided or inconvenienced. It can be reduced.

Further, since the initial temperature in the apparatus is set to 70 ° C. and the processing is performed at a relatively low temperature, the occurrence rate of the popping phenomenon can be suppressed, and the foreign matter composed of the altered layer R6a can be prevented from scattering.

Next, processing using the downflow type ashing apparatus shown in FIG. 23 will be described.

The semiconductor substrate 1 shown in FIG. 10 is installed in the apparatus, and ashing is performed while injecting NH ₃ (ammonia) gas as the inflow gas Ga.

At this time, for example, the conditions shown in FIG. 26 (b), NH ₃ flow rate 3500 ml / min, pressure 200 P
a, source power 1000 W, lower electrode (stage S
t) Ashing was performed at a temperature of 110 ° C.

Here, the semiconductor substrate 1 is fixed on the stage St by electrostatic attraction.

By such electrostatic attraction, the semiconductor substrate 1
By holding the (wafer W) and allowing a gas having good thermal conductivity such as He (helium) gas to flow between the semiconductor substrate 1 (wafer W) and the stage St, the stage St
Can be transmitted to the semiconductor substrate 1 (wafer W) with good controllability.

Here, the lower electrode (stage St) is
It is kept at 110 ℃ by a heater (not shown)
The semiconductor substrate 1 is heated to 120 ° C. through e (helium) gas or the like.
It can be maintained at a temperature of the order. The wafer backside pressure in FIG. 26B: 1.5 kPa means the pressure of a gas having good thermal conductivity such as He (helium) gas.

As described above, when a gas having a good thermal conductivity is introduced between the semiconductor substrate 1 (wafer W) and the stage St, the temperature controllability of the semiconductor substrate 1 (wafer W) is improved. . If the ashing process is performed without controlling the temperature of the semiconductor substrate 1 (wafer W), the substrate temperature rises due to the reaction heat of the ashing, and the popping phenomenon easily occurs.

Here, the bias power is not applied to the semiconductor substrate 1. During the removal of the resist film, ashing was performed without changing the above conditions.

As described above, even when the downflow type ashing apparatus is used, if NH ₃ is used as the ashing gas, the altered layer R6a (see FIG. 10) formed on the surface of the resist film by the ion implantation is removed. You can
As a result, the characteristics of the MISFET can be improved.

Further, when such an etching apparatus is used, a gas having good thermal conductivity such as He (helium) gas can be introduced between the semiconductor substrate 1 (wafer W) and the stage St, It becomes easier to control the temperature of the semiconductor substrate. Therefore, the ashing process can be easily performed at a relatively low temperature, and the occurrence rate of the popping phenomenon can be suppressed. As a result, it is possible to prevent scattering of foreign matter composed of the altered layer.

Next, as shown in FIG. 11, a resist film R7 is formed on the n-channel type MISFET formation region (nMIS formation region) by photolithography. Then, using the resist film R7, the gate electrode G, and the sidewall spacers 13 as a mask, boron (B) ions are ion-implanted at 1 × 10 ¹⁵ / cm ² or more to p ⁺ type semiconductor regions 15 (source and drain).
To form. At this time, boron (B) ions are implanted into the surface of the resist film R7 to form an altered layer R7a.

Next, the resist film R7 is replaced with the resist film R
Similar to 6, NH is used as a reactive gas. ₃Assin using
To remove.

Since NH ₃ is used as the ashing gas also in this step, the resist film mainly composed of hydrocarbon (carbon, hydrogen) can be removed as a cyanide compound (for example, hydrogen cyanide (CNH)). At the same time, B (boron) in the altered layer can be vaporized as borohydride (for example, BH ₃ , B ₂ H _6, etc.).

Therefore, the cleaning step for removing the deteriorated layer R7a can be omitted or the cleaning time can be shortened.
The characteristics of the MISFET can be improved. Also,
By performing the treatment at a relatively low temperature, it is possible to suppress the occurrence rate of the popping phenomenon and prevent the scattering of foreign matter composed of the altered layer.

In the steps up to this point, LDD (Lightly Doped
Drain structure source / drain (n ⁻ type semiconductor region 11
And n ⁺ type semiconductor region 14, p ⁻ type semiconductor region 12 and p ⁺ type semiconductor region 15)
The FET Qn and the p-channel type MISFET Qp are formed.

In the present embodiment, the resist films R6 and R7 used as masks when forming the n ⁺ type semiconductor region 14 and the p ⁺ type semiconductor region 15 are replaced with N
Although removed by ashing using H ₃ , NH ₃ was also used when removing the resist films R4 and R5 used as masks when forming the n ⁻ type semiconductor region 11 and the p ⁻ type semiconductor region 12. An ashing method may be used.

Thereafter, as shown in FIG. 12, the gate electrode
N that constitutes G, source, and drain ⁺Type semiconductor region 14
And p⁺In order to reduce the resistance of the type semiconductor region 15, n
Channel type MISFET Qn and p channel type MIS
A metal film 17 such as a cobalt (Co) film is deposited on the FET Qp.
The gate electrodes G, n⁺Type
Semiconductor region 14 and p⁺-Type semiconductor region 15 and metal film 1
7 causes a silicidation reaction at the contact portion with gold,
The metal silicide layer 19 may be formed. Then unreacted
The metal film 17 is removed by etching (FIG. 13).
A titanium (Ti) film may be used instead of the cobalt film.
Yes.

Further, after this, n-channel type MISFE
An insulating film such as a silicon oxide film is formed on the TQn and p-channel type MISFET Qp by a CVD method, and then, in the insulating film, for example, plugs are formed on the source and drain (14, 15) of the MISFET. To form
Furthermore, by depositing a metal film or the like on the insulating film, the first
Although layer wiring is formed, these are omitted in the drawing. Further, a multilayer wiring may be formed by repeating the formation of the insulating film, the plug and the metal film.

As described above, according to the present embodiment, the resist film used as the mask in the ion implantation step is removed by ashing using NH ₃ as the ashing gas. The resulting altered layer can be removed. as a result,
The characteristics of the MISFET can be improved.

Further, since the ashing process is performed at a relatively low temperature, the occurrence rate of the popping phenomenon can be suppressed, and the scattering of foreign matter composed of the altered layer can be prevented.

[0070] Here, in the present embodiment, for using the NH ₃ gas as the ashing gas, the ashing apparatus shown in FIGS. 23 and 24, need to incorporate leak detection unit and NH ₃ abatement device of the NH ₃ There is. However, there is no major change in the device configuration, and the capital investment can be small.

On the other hand, although an ashing method in which hydrogen or water is added to ashing using oxygen or ozone has been studied, in such a case, reaction with carbon (C) in the resist film is performed. The ashing rate is lower than when NH ₃ is used. Further, since the ashing reaction occurs in a system in which oxygen and hydrogen coexist, in order to ensure safety, the device structure must be complicated and the device cost increases.

Further, although P (phosphorus) is used as the n-type impurity in the present embodiment, in addition to this, As (arsenic) is used.
May be used. If the resist film used as the mask in this As ion implantation step is removed using NH ₃ as an ashing gas, As in the altered layer can be vaporized as hydrogen arsenide (AsH ₃ etc.).

Although B (boron) is used as the p-type impurity in the present embodiment, boron fluoride (BF ₃ ) or the like may be used instead. If the resist film used as a mask in this BF ₂ ion implantation step is removed by using NH ₃ as an ashing gas, boron in the altered layer is, for example, BH ₃ , B ₂ H _6, etc., and fluorine is It becomes possible to vaporize as NF ₃ .

Further, in the present embodiment, the resist film R6 used as a mask when ion-implanting phosphorus (P) ions and the resist film R7 used as a mask when ion-implanting boron (B). To
Although removed by ashing using NH ₃ , resist films R1 to R5 (especially R1, R2, R4 or R5)
An ashing method using NH ₃ may also be used for the removal.

Since the altered layer is easily formed during high-concentration ion implantation or high-energy ion implantation,
It is effective to apply the present invention to the resist film used as a mask when ion implantation with an ion concentration of 1 × 10 ¹⁵ / cm ² or more, or ion implantation with energy of 1 MeV or more. As the ionic species, a strong cleaning liquid such as a mixed liquid of ammonia and hydrogen peroxide (NH ₃ + H ₂ O ₂ ) or a hydrofluoric acid-based cleaning liquid is used to remove the film containing phosphorus (P) ions. However, since phosphorus is very difficult to remove, it is effective to apply the present invention to the resist film used as a mask during the ion implantation of phosphorus (P).

In this embodiment, the semiconductor substrate temperature is 70 ° C. or 120 ° C., but the temperature is not limited to this. However, in order to prevent the occurrence of the popping phenomenon and obtain a practical ashing rate, it is desirable that the temperature of the semiconductor substrate be 120 ° C. to 70 ° C.

Further, in this embodiment, the MISF is
The gate electrode of the ET was composed of polycrystalline silicon and a metal silicide layer to form a so-called salicide gate electrode (see FIG. 1).
3)), the gate electrode may be a so-called polymetal gate electrode composed of a laminated film of a polycrystalline silicon film and a metal film such as a tungsten film. in this case,
Since the tungsten film is scraped, a mixed solution of ammonia and hydrogen peroxide solution (NH ₃ + H ₂ O ₂ ) cannot be used. Therefore, it is suitable to use the resist removing method of the present embodiment.

(Second Embodiment) In the first embodiment, the processing is performed by using the ashing apparatus shown in FIG. 23 or 24, but the processing may be performed by using the UHF wave dry etching apparatus shown in FIG. . The semiconductor integrated circuit device manufacturing method of the present embodiment is the same as that of the first embodiment described with reference to FIGS. 1 to 13 except for the resist film R6 and R7 removing steps. The description thereof will be omitted, and the removal process of the resist films R6 and R7 will be described in detail.

First, as shown in FIG. 14, a resist film R26 is formed on the p-channel type MISFET formation region (pMIS formation region) by photolithography, and then the resist film R26, the gate electrode G and the sidewall spacers. 13 is used as a mask, and phosphorus (P) ions are applied at an energy of 50 keV at 5 × 10 ¹⁵ / cm ^2.
The n ⁺ type semiconductor region 14 (source, drain) which is an impurity region having a higher concentration than the n ⁻ type semiconductor region 11 is formed by ion implantation to some extent. At this time, phosphorus (P) ions are implanted into the surface of the resist film R26 to form an altered layer R26a.

Next, the resist film R26 (altered layer R26
(including a) is removed by etching (ashing), but is removed by the method described below.

The semiconductor substrate 1 is, for example, U shown in FIG.
It is carried into the HF wave dry etching device and processed.

FIG. 25 shows a UHF dry etching apparatus 1
It is a schematic diagram showing 00. The configuration and the like will be described below.

300M generated from high frequency power supply 101
High frequency from Hz to 900MHz is antenna (counter electrode)
It is introduced into the processing chamber 104 through 102. This high frequency is applied to the antenna 102 and the antenna ground 10 in the vicinity thereof.
3 resonates with and is efficiently propagated into the processing chamber 104. This high frequency is generated by an ECR (Electron Cycl
Otron Resonance) or higher axial magnetic field to generate high density (1 × 10 ¹⁷ / m ³ or more) plasma in a low pressure region of about 0.3 Pa.

The semiconductor substrate 1 (wafer W) is adsorbed and fixed onto the upper surface of the stage St installed in the center of the processing chamber 104 by an electrostatic chuck mechanism (not shown). The distance between the semiconductor substrate 1 (wafer W) fixed on the upper surface of the stage St and the antenna 102 is arbitrarily set within the range of 20 mm to 150 mm. On the stage St, 400 kHz to 13.5 generated from the second high frequency power supply 107.
A high frequency of 6 MHz is applied, and the ion incident energy to the semiconductor substrate 1 (wafer W) is controlled independently of plasma generation. After the flow rate of the etching (ashing) gas is optimized by the gas flow rate controller 108, the etching gas is introduced into the processing chamber 104 through the gas introduction port 109 and decomposed by the plasma. Further, the exhaust gas is exhausted to the outside of the processing chamber 104 by the exhaust pump 110.
The pressure inside the processing chamber 104 is adjusted by opening and closing the adjusting valve 111 installed in the exhaust system. Processing chamber 104
The temperature of each part in contact with the plasma, such as the inner wall, the stage St, and the gas introduction port 109, is controlled by a temperature controller (not shown).

In such an apparatus, bias power can be applied to the semiconductor substrate 1 (wafer W), and the etching (ashing) speed can be improved. 25, the semiconductor substrate 1 is also used in the same manner as the downflow type ashing apparatus of the first embodiment.
The (wafer W) is fixed on the stage St by electrostatic attraction. Further, the semiconductor substrate 1 (wafer W) is held by electrostatic attraction, and the semiconductor substrate 1 (wafer W) and the stage S are held.
The substrate temperature is controlled by introducing a gas having good thermal conductivity such as He (helium) gas between t and t.

The semiconductor substrate 1 shown in FIG. 14 is placed in such an apparatus, and the resist film R26 (including the altered layer R26a is included while injecting NH ₃ (ammonia) gas as an inflowing gas (etching gas, ashing gas) Ga). ) Etching (ashing) is performed.

At this time, for example, the condition shown in FIG.
₃ flow 300 ml / min, pressure 2 Pa, a source power 1000W, the bias power 200 W, the lower electrode (stage) Temperature 20 ° C. (° C. substrate temperature 70) under the conditions of the wafer backside pressure 1.5 kPa, were etched (ashed) . Here, the bias power means high frequency power applied to a semiconductor substrate (wafer). Here, during the removal of the resist film, etching (ashing) was performed without changing the above conditions.

As described above, also in this embodiment, the resist film R26 used as a mask in the ion implantation step is used as an etching (ashing) gas with NH.
Since it is removed by etching (ashing) using ₃ , the deteriorated layer R2 formed on the surface of the resist film R26 by the ion implantation as described in detail in the first embodiment.
6a can be removed. As a result, MISFET
The characteristics of can be improved.

Further, since the etching (ashing) process is performed at a relatively low temperature, it is possible to suppress the occurrence rate of the popping phenomenon and prevent scattering of foreign matter composed of the altered layer R26a.

Then, as shown in FIG. 15, a resist film R27 is formed on the n-channel type MISFET formation region (nMIS formation region) by photolithography. Then, using the resist film R27, the gate electrode G, and the sidewall spacers 13 as a mask, boron (B) is used.
The p ⁺ type semiconductor region 15 (source, drain) is formed by implanting ions at 1 × 10 ¹⁵ / cm ² or more. At this time, boron (B) ions are implanted into the surface of the resist film R27, and the altered layer R27a.
Is formed.

Next, the resist film R27 (altered layer R27
Similarly to the resist film R26, it is carried into a UHF wave dry etching apparatus and is removed by etching (ashing) using NH ₃ as a reactive gas (FIG. 1).
6).

In this step as well, the resist film used as the mask in the ion implantation step is removed by etching (ashing) using NH ₃ as an etching (ashing) gas, so that the first embodiment has been described in detail. Thus, the altered layer R27a formed on the surface of the resist film R27 by the ion implantation can be removed. As a result, the characteristics of the MISFET can be improved.

Although the bias power is set to 200 W in the present embodiment, it is not limited to this value. However, the high frequency bias may accelerate the deterioration of the resist film, and therefore the high frequency bias is 3
The frequency is set to 00 kHz to 20 MHz, and the difference (Vpp: peak to peak voltage) between the maximum value and the minimum value of the voltage applied to the semiconductor substrate (wafer) is preferably 0.5 kV or less.

Also, in the apparatus shown in this embodiment, since NH ₃ gas is used as the etching (ashing) gas, the NH ₃ leak detection unit and the NH ₃ leak detecting section are used similarly to the ashing apparatus shown in FIGS. _{3 It} is necessary to install an abatement device, but there is no major change in device configuration for others,
The device cost can be suppressed.

Also in this embodiment, as described in detail in the first embodiment, the ion species used in the ion implantation step is not limited to, for example, P (phosphorus), and The ashing method of this embodiment can be applied to the removal of the resist films R1 to R5 described in the first embodiment. In particular, it is suitable for use in a manufacturing method having high-concentration ion implantation and high-energy ion implantation. Further, the semiconductor substrate temperature prevents the popping phenomenon and obtains a practical ashing rate.
It can be appropriately set in the range of 20 ° C to 70 ° C. Also, M
Although the gate electrode of the ISFET is the salicide gate electrode, it may be a polymetal gate electrode, and the polymetal gate electrode is effective by using the resist removing method of the present embodiment.

Here, in the first and second embodiments,
The suitable temperature range used in the present invention is 120 ° C. to 70 ° C. This is because 1) in order to suppress the popping phenomenon,
It is preferable to treat at a temperature of 120 ° C. or lower,
2) Further, in order to secure a practical ashing rate, it is necessary to process at a temperature of about 70 ° C. or higher,
It is due to.

Within this range, when the downflow type ashing apparatus (single-wafer type, see FIG. 23) described in the first embodiment is used, a practical ashing rate of 1 μm / min or more is required. Therefore, 10
Treatment at 0 ° C or higher is preferred. That is, 100 ℃ ~
It is preferable to perform the treatment in the range of 120 ° C.

Further, when the barrel type ashing apparatus (batch type, see FIG. 24) described in the first embodiment is used, it is possible to process a plurality of wafers at the same time, and therefore, practical ashing is performed. The rate is 50 nm /
It may be min or more, and 70 ° C or more is sufficient. That is,
The treatment is preferably performed within the range of 70 ° C to 120 ° C.

When the UHF wave dry etching apparatus (single-wafer type, see FIG. 25) described in the second embodiment is used, although it is a single-wafer type, bias power is used, so that ashing is performed. The rate can be increased.
Therefore, a temperature of 70 ° C. or higher is sufficient. That is, 70 ° C to 1
The treatment is preferably performed within the range of 20 ° C.

(Embodiment 3) Embodiment 1 or 2
Ashing (resist film R
6 and R7 were removed), but as described below,
The ashing conditions may be changed during the ashing process. The manufacturing method of the semiconductor integrated circuit device according to the present embodiment is the same as in FIG. 1 except for the step of removing the resist films R6 and R7.
Since it is similar to the case of the first embodiment described with reference to FIGS. 13A to 13C, description thereof will be omitted, and the removal process of the resist films R6 and R7 will be described in detail.

First, as shown in FIG. 17, a resist film R36 is formed on the p-channel MISFET formation region (pMIS formation region) by photolithography, and then the resist film R36, the gate electrode G and the sidewall spacers are formed. 13 is used as a mask, and phosphorus (P) ions are applied at an energy of 50 keV at 5 × 10 ¹⁵ / cm ^2.
The n ⁺ type semiconductor region 14 (source, drain) which is an impurity region having a higher concentration than the n ⁻ type semiconductor region 11 is formed by ion implantation to some extent. At this time, phosphorus (P) ions are implanted into the surface of the resist film R36 to form an altered layer R36a.

Next, the resist film R36 (altered layer R36
(including a) is removed by ashing, but it is removed under the following conditions.

First, the semiconductor substrate 1 shown in FIG. 17 is set in, for example, the downflow type ashing apparatus described in detail in the first embodiment with reference to FIG. 23, and NH ₃ (ammonia) gas is used as the inflow gas Ga. The first ashing is performed while injecting.

[0104] At this time, in the initial ashing, for example, conditions shown in (1) of FIG. 28 (a), NH ₃ flow rate 350
0 ml / min, pressure 200 Pa, source power 100
0 W, lower electrode (stage) temperature of 110 ℃,
Perform ashing. In addition, here, the semiconductor substrate 1 is
It is fixed on the stage St by electrostatic attraction. Further, the semiconductor substrate 1 is held by electrostatic attraction, and a gas having good thermal conductivity such as He (helium) gas is caused to flow between the semiconductor substrate 1 (wafer) and the stage St.
The substrate temperature is controlled. This gas pressure (wafer backside pressure) is 1.5 kPa. In addition, in FIG. 28, the first ashing is referred to as JE (just etching),
OE (over etching) the second ashing described later
Is written.

Thus, NH _{3 is used} as the ashing gas.
Is used, a resist film mainly composed of hydrocarbons (carbon, hydrogen) is formed into a cyanide compound (for example, hydrogen cyanide (C
NH)) as well as removing P (phosphorus) in the altered layer R36a from phosphorus hydride (for example, PH).
₃ )) can be vaporized. Therefore, the altered layer R36a can be positively vaporized. As a result, as shown in FIG. 18, the altered layer R36a on the surface of the resist film R36 can be removed. The altered layer R
It is not necessary to remove all 36a, and it may remain thin. Further, not only the altered layer R36a but also the resist film R36 thereunder may be further removed.

Then, the ashing conditions are changed as follows, and the second ashing is performed. For example, in FIG.
As shown in (2), NH ₃ flow rate is 3500 ml / min, pressure is 200 Pa, and source power is 1000 W. This point is the same condition as the first ashing. The different point is that the electrostatic attraction of the semiconductor substrate 1 is stopped, and the semiconductor substrate 1 is mechanically held only by lift pins (not shown in FIG. 23). Further, the inflow of gas having good thermal conductivity between the semiconductor substrate 1 (wafer W) and the stage St is also stopped. as a result,
The substrate temperature goes out of control, the substrate temperature gradually rises, the ashing reaction of the resist film is promoted, and the resist film R36 remaining on the semiconductor substrate is rapidly removed (FIG. 19).

Here, the altered layer R on the surface of the resist film R36.
Since 36a is removed or thinned by the first ashing, there is no fear of causing the popping phenomenon.

As described above, according to the present embodiment, the ashing step is performed to remove the deteriorated layer on the surface of the ashing step, and the resist film (the portion which is not deteriorated or has a small degree of deterioration) under the ashing step. (2) is removed, the resist film can be removed efficiently while preventing the popping phenomenon.

Then, as shown in FIG. 20, a resist film R37 is formed on the n-channel type MISFET formation region (nMIS formation region) by photolithography. Then, using the resist film R37, the gate electrode G, and the sidewall spacers 13 as a mask, boron (B) is used.
The p ⁺ type semiconductor region 15 (source, drain) is formed by implanting ions at 1 × 10 ¹⁵ / cm ² or more. At this time, boron (B) ions are implanted into the surface of the resist film R37, and the altered layer R37a
Is formed.

Next, the resist film R37 (altered layer R37
(including a), like the resist film R36, a step for removing the deteriorated layer on the surface (FIG. 21) and a resist film (a part which is not deteriorated or has a small degree of deterioration) thereunder are removed. It is removed by two steps of ashing including the step of performing (FIG. 22).

As a result, like the case of the resist film R36, the resist film can be removed efficiently while preventing the popping phenomenon.

Next, an example of two-stage ashing using the UHF wave dry etching apparatus (FIG. 25) described in the second embodiment will be described. The method for manufacturing the semiconductor integrated circuit device in this case is the same as that of the first embodiment described with reference to FIGS. 1 to 13 except for the step of removing the resist films R6 and R7. And omit
The step of removing the resist films R6 and R7 will be described in detail. In addition, the cross-sectional views of the main part of the semiconductor substrate during the step of removing the resist films R6 and R7 are the same as the above-described case described with reference to FIGS. 17 to 22, so the description will be given with reference to these drawings. .

First, by photolithography, p
Channel type MISFET formation region (pMIS formation region)
A resist film R36 is formed thereon, and then the resist film R36, the gate electrode G and the sidewall spacer 1 are formed.
By using phosphorus as a mask, phosphorus (P) ions are ion-implanted at an energy of 50 keV at about 5 × 10 ¹⁵ / cm ² to form an n ⁺ type semiconductor region which is an impurity region having a higher concentration than the n ⁻ type semiconductor region 11. 14 (source, drain) are formed (see FIG. 17). At this time, the resist film R
Phosphorus (P) ions are implanted into the surface of 36 to form an altered layer R36a.

Next, the resist film R36 (altered layer R36
Although (a) is removed by etching (ashing), it is removed under the following conditions.

First, the semiconductor substrate 1 (see FIG. 17) is set in, for example, the UHF wave dry etching apparatus described in detail in Embodiment 2 with reference to FIG. 25, and NH ₃ (ammonia) is used as an inflow gas Ga. First etching (ashing) is performed while injecting gas.

At this time, in the initial stage of etching (ashing), for example, the condition shown in (1) of FIG.
The first etching (ashing) is performed under the conditions of NH ₃ flow rate 300 ml / min, pressure 2 Pa, source power 1000 W, bias power 200 W, and lower electrode (stage) temperature 20 ° C. In addition, here, the semiconductor substrate 1
The (wafer W) is fixed on the stage St by electrostatic attraction. Further, the semiconductor substrate 1 (wafer W) is held by electrostatic attraction, and the semiconductor substrate 1 (wafer W) and the stage S are held.
The substrate temperature is controlled by introducing a gas having good thermal conductivity such as He (helium) gas between t and t. This gas pressure (wafer backside pressure) is 1.5k
Pa.

As described above, when NH ₃ is used as the etching (ashing) gas, the resist film mainly composed of hydrocarbon (carbon, hydrogen) can be removed as a cyanide compound (for example, hydrogen cyanide (CNH)). At the same time, P (phosphorus) in the altered layer R36a can be vaporized as phosphorus hydride (eg, PH ₃ ). Therefore, the altered layer can be positively vaporized. As a result, the altered layer R36 on the surface of the resist film R36
a can be removed (see FIG. 18).

Then, the etching (ashing) conditions are changed as follows, and the second etching (ashing) is performed. For example, as shown in (2) of FIG. 28 (b), NH ₃ flow rate 300 ml / min, pressure 2 Pa, source power 10
00W and lower electrode (stage) temperature 20 ° C. This point is the same condition as the first etching (ashing).

The difference is that the pressure of the gas flowing between the semiconductor substrate 1 (wafer) and the stage St is lowered (in this case, 0 Pa) and the thermal conductivity is reduced. As a result, the substrate temperature gradually rises, and the ashing reaction of the resist film is promoted. In addition, the bias power is 200W
To 0W. As a result, deterioration of the resist film can be suppressed by the high frequency bias.

Here, the altered layer R on the surface of the resist film R36.
Since the portion 36a is removed by the first etching (ashing), there is no fear of causing the popping phenomenon.

As described above, according to the present embodiment, the etching (ashing) step is performed to remove the deteriorated layer on the surface thereof, and the resist film as the lower layer (not changed or the degree of change is changed). The removal of the resist film can be performed efficiently while preventing the popping phenomenon (see FIG. 19).

Then, by photolithography,
A resist film R37 is formed on the n-channel type MISFET formation region (nMIS formation region) (see FIG. 20). Then, using the resist film R37, the gate electrode G, and the sidewall spacers 13 as a mask, boron (B) is used.
The p ⁺ type semiconductor region 15 (source, drain) is formed by implanting ions at 1 × 10 ¹⁵ / cm ² or more. At this time, boron (B) ions are implanted into the surface of the resist film R37, and the altered layer R37a
Is formed.

Then, the resist film R37 (altered layer R37
a) in the same manner as the resist film R36, and a step of removing the deteriorated layer on the surface of the resist film R36 and a step of removing the resist film as an underlying layer (a portion which is not deteriorated or has a small degree of deterioration). It is removed by two-step etching (ashing) (see FIGS. 21 and 22).

As a result, like the case of the resist film R36, the resist film R37 can be efficiently removed while preventing the popping phenomenon.

In the present embodiment, the first and second ashing are performed under different conditions, but these ashings may be performed in the same processing chamber (chamber), or the first and second ashing may be performed. The processing chamber (chamber) may be changed between the first ashing and the second ashing.

Also in this embodiment, as described in detail in the first embodiment, the ion species used in the ion implantation step is not limited to, for example, P (phosphorus), and The ashing method of this embodiment can be applied to the removal of the resist films R1 to R5 described in the first embodiment. In particular, it is suitable for use in a manufacturing method having high-concentration ion implantation and high-energy ion implantation. Further, the semiconductor substrate temperature prevents the popping phenomenon and obtains a practical ashing rate.
It can be appropriately set in the range of 20 ° C to 70 ° C. Also, M
Although the gate electrode of the ISFET is the salicide gate electrode, it may be a polymetal gate electrode, and the polymetal gate electrode is suitable for the resist removal of the present embodiment.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say.

In particular, in the first to third embodiments, MI
Although the semiconductor integrated circuit device having the SFET has been described as an example, it can be widely applied to other semiconductor elements, for example, a method for manufacturing a semiconductor integrated circuit device having an ion implantation step such as a bipolar memory, a flash memory, and a ferroelectric memory. is there.

[0129]

The effects obtained by the typical ones of the inventions disclosed in this application will be briefly described as follows.
It is as follows.

(1) The resist film formed on the semiconductor substrate and used as a mask in the ion implantation step is
Since the removal is performed using the gas containing NH ₃ , the deteriorated layer formed on the resist film surface by the ion implantation can be removed, and the generation of foreign matter and the characteristics of the semiconductor integrated circuit device by the cleaning for removing foreign matter can be improved. It is possible to prevent deterioration. In addition, the manufacturing yield of the semiconductor integrated circuit device can be improved. Further, it is possible to cope with miniaturization of the semiconductor integrated circuit device.

Further, by removing the resist film at 120 ° C. or lower, vaporization and rupture of the altered layer (popping phenomenon)
It is possible to prevent the occurrence of foreign matter and to prevent the deterioration of the characteristics of the semiconductor integrated circuit device due to the generation of foreign matter and the cleaning for removing the foreign matter.

(2) The resist film formed on the semiconductor substrate and used as a mask in the ion implantation step is
Since the gas containing NH ₃ is used for the treatment at the first temperature, the temperature is raised to the second temperature higher than the first temperature for the treatment, so that the popping phenomenon can be prevented and the resist film can be removed efficiently. It can be carried out.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of essential parts of a substrate showing a method for manufacturing a semiconductor integrated circuit device which is Embodiment 1 of the present invention.

FIG. 2 is a sectional view of the essential part of the substrate, for showing the method for manufacturing the semiconductor integrated circuit device which is Embodiment 1 of the present invention.

FIG. 3 is a cross-sectional view of the essential part of the substrate, for showing the method for manufacturing the semiconductor integrated circuit device which is Embodiment 1 of the present invention.

FIG. 4 is a sectional view of the essential part of the substrate, for showing the method for manufacturing the semiconductor integrated circuit device which is Embodiment 1 of the present invention.

FIG. 5 is a sectional view of the essential part of the substrate, for showing the method for manufacturing the semiconductor integrated circuit device which is Embodiment 1 of the present invention.

FIG. 6 is a cross-sectional view of the essential part of the substrate, for showing the method for manufacturing the semiconductor integrated circuit device which is Embodiment 1 of the present invention.

FIG. 7 is a main-portion cross-sectional view of the substrate showing the manufacturing method of the semiconductor integrated circuit device which is Embodiment 1 of the present invention;

FIG. 8 is a fragmentary cross-sectional view of the substrate showing the method of manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention.

FIG. 9 is a cross-sectional view of the essential part of the substrate, for showing the method for manufacturing the semiconductor integrated circuit device which is Embodiment 1 of the present invention.

FIG. 10 is a fragmentary cross-sectional view of the substrate showing the method for manufacturing the semiconductor integrated circuit device which is Embodiment 1 of the present invention.

FIG. 11 is a fragmentary cross-sectional view of the substrate showing the method of manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention.

FIG. 12 is a fragmentary cross-sectional view of the substrate showing the method of manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention.

FIG. 13 is a fragmentary cross-sectional view of the substrate showing the method of manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention.

FIG. 14 is a fragmentary cross-sectional view of a substrate showing a method for manufacturing a semiconductor integrated circuit device which is Embodiment 2 of the present invention.

FIG. 15 is a fragmentary cross-sectional view of a substrate showing a method for manufacturing a semiconductor integrated circuit device which is Embodiment 2 of the present invention.

FIG. 16 is a fragmentary cross-sectional view of a substrate showing a method for manufacturing a semiconductor integrated circuit device which is Embodiment 2 of the present invention.

FIG. 17 is a main-portion cross-sectional view of the substrate showing the method of manufacturing the semiconductor integrated circuit device which is Embodiment 3 of the present invention.

FIG. 18 is a fragmentary cross-sectional view of a substrate showing a method of manufacturing a semiconductor integrated circuit device which is Embodiment 3 of the present invention.

FIG. 19 is a fragmentary cross-sectional view of a substrate showing a method for manufacturing a semiconductor integrated circuit device which is Embodiment 3 of the present invention.

FIG. 20 is a fragmentary cross-sectional view of a substrate showing a method for manufacturing a semiconductor integrated circuit device which is Embodiment 3 of the present invention.

FIG. 21 is a fragmentary cross-sectional view of a substrate showing a method for manufacturing a semiconductor integrated circuit device which is Embodiment 3 of the present invention.

FIG. 22 is a fragmentary cross-sectional view of a substrate showing a method for manufacturing a semiconductor integrated circuit device which is Embodiment 3 of the present invention.

FIG. 23 is a diagram schematically showing an ashing device used in the embodiment of the present invention.

24 (a) to (c) are diagrams showing an outline of another ashing device used in the embodiment of the present invention.

FIG. 25 is a diagram showing an outline of an etching apparatus used in the embodiment of the present invention.

26 (a) and (b) are diagrams showing ashing conditions according to the first embodiment of the present invention.

FIG. 27 is a diagram showing etching (ashing) conditions according to the second embodiment of the present invention.

28A and 28B are diagrams showing ashing conditions according to the third embodiment of the present invention.

FIG. 29 is a fragmentary cross-sectional view of the substrate showing the method for manufacturing the semiconductor integrated circuit device, for explaining the effect of the present invention.

FIG. 30 is a fragmentary cross-sectional view of the substrate showing the method for manufacturing the semiconductor integrated circuit device, for explaining the effect of the present invention.

FIG. 31 is a fragmentary cross-sectional view of the substrate showing the method for manufacturing the semiconductor integrated circuit device, for explaining the effect of the present invention.

FIG. 32 is a main-portion cross-sectional view of the substrate showing the method for manufacturing the semiconductor integrated circuit device, for explaining the effect of the present invention.

FIG. 33 is a cross-sectional view of the essential part of the substrate, for showing the method for manufacturing the semiconductor integrated circuit device, for explaining the effect of the present invention.

FIG. 34 is a cross-sectional view of the essential part of the substrate, for showing the method for manufacturing the semiconductor integrated circuit device, for explaining the effect of the present invention.

[Explanation of symbols]

1 semiconductor substrate (substrate) 2 element isolation 3 p-type well 4 n-type well 7 silicon oxide film 8 gate oxide film 9 polycrystalline silicon film 11 n ⁻ type semiconductor region 12 p ⁻ type semiconductor region 13 sidewall spacer 14 n ⁺ type Semiconductor region 15 p ⁺ type semiconductor region 17 Metal film 19 Metal silicide layer 100 UHF dry etching device 101 High frequency power supply 102 Antenna (counter electrode) 103 Antenna ground 104 Processing chamber 105 Solenoid coil 107 Second high frequency power supply 108 Gas flow rate controller 109 Gas Inlet 110 Exhaust pump 111 Adjusting valve 201 Quartz tube 301 Quartz tube 302 Holder G Gate electrode Ga In gas IN Inlet OUT Outlet PL1, PL2 Electrode plate Qn n-channel type MISFET Qp p-channel type MISFET R1 to R5 Resist film R , R7 resist film R6a, R6b, R7a altered layer R26, R27 resist film R26a, R27a altered layer R36, R37 resist film R36A, R37A deteriorated layer St stage W wafer

Claims (5)

[Claims] 1. A process of forming a resist film on a semiconductor substrate; (b) a process of ion implantation using the resist film as a mask; and (c) the process of (b), the resist film. And a step of removing the gas using a gas containing NH ₃ , and a method for manufacturing a semiconductor integrated circuit device. 2. The step (c) is performed at a temperature of the semiconductor substrate of 120 ° C. or lower.
A method for manufacturing the semiconductor integrated circuit device described. 3. In the step (c), the temperature of the semiconductor substrate is set to 120 ° C. or lower by fixing the semiconductor substrate on a stage by electrostatic attraction and flowing a gas between the stage and the semiconductor substrate. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein 4. (a) a step of forming a resist film on a semiconductor substrate; (b) a step of implanting ions using the resist film as a mask; (c) the step of (b); Is removed by using a gas containing NH _3, and after the surface of the resist film is removed at a first temperature, the resist film is removed at a second temperature higher than the first temperature. A method for manufacturing a semiconductor integrated circuit device, comprising: 5. In the step (c), the temperature of the semiconductor substrate is fixed by fixing the semiconductor substrate on a stage by electrostatic attraction and controlling the pressure of gas flowing between the stage and the semiconductor substrate. 5. The method for manufacturing a semiconductor integrated circuit device according to claim 4, wherein the temperature is maintained at the first or second temperature.