JP2003177934A - Digital signal processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a DSP which can add and correct a program with a small- capacity EEPROM. <P>SOLUTION: Comparing circuits 19a to 19n compare the value of a PC (program counter) 15a with addresses registered in registers 18a to 18n and output a coincidence detection signal to a control circuit 15 through a decision circuit 20 when a match is obtained. Consequently, the value of the PC 15a is set in a specified address in the EEPROM 11b and a performance program is switched from a processing program in a mask ROM 11a to a program for addition and correction in the EEPROM 11b. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal processing device (hereinafter referred to as "DSP"), particularly a D having a non-rewritable memory and a rewritable nonvolatile memory.
It is about SP.

[0002]

2. Description of the Related Art FIGS. 2A and 2B are schematic block diagrams of a conventional DSP. FIG. 2A shows a hardware configuration, and FIG. 2B shows a software configuration. Shows. As shown in FIG. 2A, this DSP has a mask R
OM (Read Only Memory) 1a and EEPROM (Electr
It has a memory circuit 1 configured by an erasably programmable programmable ROM) 1b. The mask ROM 1a is
The program and data for the processing performed by this DSP are stored, and the EEPROM 1b is the mask ROM 1
This is a memory for writing changes and additional parts of the program a.

A read circuit 2 for reading data DAT such as an instruction code from the memory circuit 1 is connected to the memory circuit 1, and the read circuit 2 decodes the read instruction code and executes the corresponding execution instruction. A decoding circuit 3 for decoding is connected to. The decoding circuit 3 is connected to an execution circuit 4 and a control circuit 5 that execute processing in accordance with the decoded execution instruction. The control circuit 5 has a program counter (hereinafter referred to as “PC”) 5a for designating an address, and controls the order of addresses read from the memory circuit 1 by the reading circuit 2 and the overall operation. .

The DSP also writes to the interrupt circuit 6 which interrupts the control circuit 5 periodically or at a set timing, the stack 7 for storing the return address of the subroutine, and the EEPROM 1b. It has a writing interface 8 for performing.

FIG. 2B shows a mask ROM 1a and an EEP.
The outline of the software stored in the ROM 1b is shown. In the following description, mnemonic codes of general instructions that do not involve branching, branch instructions, and no-operation instructions are referred to as INS, JMP, and NOP, respectively.

For example, the mask ROM 1a is 0000 to
Address 0999 is assigned, and processing programs are sequentially stored from address 0000. However, mask ROM1
In the middle of the processing program of a, a branch instruction (JMPxxxx) to a predetermined address of the EEPROM 1b is inserted at a required place in preparation for an error (bug) of a program that may be discovered later or addition of processing content. Has been done. This Figure 2
In the example of (b), addresses 0000, 0100 and 02
At address 00, instructions for branching to addresses 1000, 1001 and 1002 of the EEPROM 1b are stored.

On the other hand, the EEPROM 1b has 1000 to 1
Address 299 is assigned, and a program for changing or adding processing to the processing program in the mask ROM 1a is written therein. For example, mask ROM 1a 0000 to
10 if there is no change in the processing program at address 0099
At address 00, a branch instruction to address 0001 (JMP00
01) is stored. In addition, the mask ROM 1a 020
If there is no change in the processing program after address 0, 100
A branch instruction to address 0201 (JMP020
1) is stored.

In the example of FIG. 2B, the mask ROM 1
In order to change the instruction (INS181X) at address 0181 of a to another instruction (INS181A), a branch instruction (JMP1003) to address 1003 is stored at address 1001. In addition, at addresses 1003 to 1082, 01
The program corresponding to addresses 01 to 0180 is stored,
The changed instruction (INS0181A) is stored at address 1083. Then, at 1084, the mask RO
Branch instruction to address 0182 of M1A (JMP0182)
Is stored.

Next, the operation will be described. The DSP is reset and 0000 is set in the PC5a, and then this D
When the operation of the SP is started, the reading circuit 2 reads the data at address 0000 (JMP1000) of the memory circuit 1. The data read by the reading circuit 2 is decoded by the decoding circuit 3, and the command resulting from the decoding is output to the execution circuit 4 and the control circuit 5. As a result, in the control circuit 5, the value of PC5a is rewritten to the branch destination address 1000.

In the reading circuit 2, 1000 of the EEPROM 1b is read based on the address signal given from the PC 5a.
The address data (JMP0001) is read. The data read by the reading circuit 2 is decoded by the decoding circuit 3,
The instruction resulting from the decoding is output to the execution circuit 4 and the control circuit 5. As a result, in the control circuit 5, the value of the PC 5a is rewritten to 0001 which is the branch destination address.

The reading circuit 2 reads the data (command INS0001) at address 0001 of the mask ROM 1a based on the address given from the PC 5a. The data read by the reading circuit 2 is decoded by the decoding circuit 3,
The instruction resulting from the decoding is output to the execution circuit 4 and the control circuit 5. If the instruction output from the decoding circuit 3 is not a branch instruction, the execution circuit 4 performs a predetermined process and the control circuit 5 increases the value of the PC 5a by one. As a result, the value of the PC 5a becomes 0002.

After that, the mask ROM 1a 0002-0
The instructions stored at address 099 are sequentially read and executed. And the instruction at address 0100 (JMP1001)
The value of PC5a is set to 1001 by executing
It branches to the address 1001 of the EEPROM 1b.

At address 1001 of the EEPROM 1b, 1
Since the branch instruction to address 003 is stored, PC5
The value of a is set to 1003, and 1 in EEPROM 1b
Branched to address 003. Then, the instructions stored at address 1003 and thereafter are sequentially executed. After the changed instruction (INS181A) stored in the 1083th address is executed, the branch instruction (JMP0) stored in the next 1084th address is executed.
182) is executed to return to the address 0182 of the mask ROM 1a.

As described above, in the DSP of FIG. 2A, in addition to the mask ROM 1a, a rewritable EEPROM
Since it has 1b, it is possible to flexibly cope with the correction and change of the program.

[0015]

However, the conventional DSP has the following problems. Mask ROM 1
EEPROM1 is stored in the key part of the program stored in a.
Since it is necessary to embed an instruction for branching to b in advance, it is difficult to determine the arrangement. Also, EE
It is necessary to store a program for returning to the mask ROM 1a in the PROM 1b corresponding to the branch instruction embedded in the mask ROM 1a, which increases the usage amount and processing time of the EEPROM 1b.

Further, for example, 100 in FIG.
Like addresses 3 to 1083, processing from the branch point to the EEPROM 1b (for example, address 0100 in FIG. 2B) to the position of the instruction that needs to be changed (for example, address 0180 in FIG. 2B). , EEPROM1b side needs to be executed as a program. Therefore, there is a problem that it is necessary to prepare the EEPROM 1b having a relatively large capacity, assuming that the position of the branch instruction embedded in advance and the position of the instruction that needs to be changed are distant from each other. .

The present invention solves the problems of the prior art and provides a DSP capable of changing or modifying a program with a small capacity EEPROM.

[0018]

In order to solve the above problems, the first invention of the present invention provides a DSP having a non-rewritable first memory and a rewritable non-volatile second memory. Then, a storage circuit in which the processing program is stored, a rewritable nonvolatile register in which a specific address of the first memory is registered, and an address of the processing program to be read and executed from the storage circuit are sequentially stored. PC, a judgment circuit that compares the value of the PC with the value of the register, and detects whether the value of the PC matches the specific address, and the second circuit when the judgment circuit detects a match. The specified address of memory is set to P
A control circuit which sets to C and updates the value of the PC based on the processing program when no match is detected;
A reading circuit that reads the processing program from the storage circuit according to the value of the PC, a decoding circuit that decodes the processing program read by the reading circuit and decodes into a corresponding execution instruction, and a decoding circuit that is decoded by the decoding circuit. And an execution circuit that executes an execution instruction.

According to a second aspect of the invention, the reading circuit, the decoding circuit and the execution circuit of the first aspect of the invention are arranged to perform pipeline processing in parallel at the same time.

According to a third aspect of the invention, the register according to the first or second aspect of the invention is configured so that a plurality of specific addresses of the first memory can be registered.

According to the present invention, since the DSP is constructed as described above, the following operation is performed. The PC value is sequentially set by the control circuit, and the processing program is sequentially read from the storage circuit according to the PC value, decoded, and executed. Here, if the value of the PC matches the specific address of the first memory registered in the register, the determination circuit detects the match, and the control circuit further detects this PC.
Is set to a predetermined address in the second memory. As a result, the execution address is switched to the predetermined address in the second memory.

[0022]

1 is a block diagram of a DSP showing an embodiment of the present invention. This DSP is a memory circuit 1 including a non-rewritable mask ROM 11a and an electrically erasable and writable EEPROM 11b.
1, a reading circuit 12 for reading data such as an instruction code from the memory circuit 11, a decoding circuit 13 for decoding the instruction code read by the reading circuit 12 and decoding it into a corresponding execution instruction, and the decoding circuit 13 The execution circuit 14 is provided for executing processing according to the decoded execution instruction.

Further, the DSP has a PC 15a for designating an address ADR read from the memory circuit 11 by the reading circuit 12, and a control circuit 15 for controlling the order of processing and the overall operation. On the other hand, it is provided with an interrupt circuit 16 that interrupts periodically or at a set timing, and a stack 17 for storing an address to which a subroutine returns.

Further, this DSP has a mask ROM 11a.
An electrically rewritable non-volatile register (REG) 1 for storing a specific address such as a changed portion in
8a, 18b, ..., 18n, these registers 18a ...
18n and a comparison circuit (CMP) 19a, 19b, ..., 19n for comparing the contents of the PC 15a with each other, a determination circuit 20 for determining whether or not there is a change based on the comparison result of these comparison circuits 19a to 19n, and an EEPROM 11b. A write interface 21 for writing the registers 18a to 18n is provided.

The mask ROM 11a stores programs and data for the processing performed by this DSP.
The PROM 11b is a memory for writing changes and additions to the program of the mask ROM 11a. Under the control of the control circuit 15, the reading circuit 12 sends the instruction read and held from the memory circuit 11 in the previous cycle to the decoding circuit 13 and, at the same time, the address ADR designated by the PC 15a of the control circuit 15 is read. The data DAT is read from the memory circuit 11 as an instruction code and newly held.

The decoding circuit 13 decodes the instruction sent from the reading circuit 12 and holds the corresponding execution instruction, and also decodes and holds the execution instruction that was decoded and held in the previous cycle. It is output to the control circuit 15.
The execution circuit 14 is composed of an arithmetic unit, a multiplier, an analog / digital converter, etc., and executes a predetermined process in accordance with an execution instruction given from the decoding circuit 13. The reading circuit 12, the decoding circuit 13, and the execution circuit 14 are each configured to perform pipeline processing that operates in parallel at the same time.

FIG. 3 is an explanatory diagram showing an outline of the software of FIG. This software is mask ROM11
a and the EEPROM 11b. For example, addresses 0000 to 0999 are allocated to the mask ROM 11a, and processing programs are sequentially stored from addresses 0000. During this processing program, the EEPROM
The branch instruction to 11b is not incorporated.

On the other hand, the EEPROM 11b has 1000
Addresses -1019 are assigned, and a program for changing or adding processing to the processing program in the mask ROM 11a is written therein. For example, 0 in the mask ROM 11a
The instruction at address 204 (INS204X) and the instruction at address 0205 (INS205X) are respectively issued as instructions (INS20
4A) and instruction (INS205A),
Branch instruction (JMP) to address 1000 of EEPROM 11b
1010) is stored. Further, at addresses 1010 and 1011, the changed command (INS204A) and the command (IN
S205A) are respectively stored, and a branch instruction (JMP0206) for returning to the address 0206 of the mask ROM 11a is stored in the address 1012.

Further, at the address 0204 of the mask ROM 11a, the value of the register 18a is set to 02 in order to register the branch to the address 1000 of the EEPROM 11b.
It is set to 04. The contents of the EEPROM 11b and the register 18a are changed by changing the write interface 21.
Via a writing device (not shown).

FIG. 4 is an explanatory diagram showing the operation of FIG.
Hereinafter, the operation of FIG. 1 will be described with reference to FIGS. 3 and 4. In the cycle T000, when the DSP is in the reset state, the value of the PC 15a is set to 0000, and the no-operation instruction (NOP) is set to the reading circuit 12 and the decoding circuit 13.

When the operation of the DSP is started in the period T001, the reading circuit 12 reads and holds the data (INS000) at the address 0000 of the memory circuit 11 according to the value set in the PC 15a. At this time, the no-operation instruction (NO
P) is output to and held by the execution circuit 14, and the reading circuit 1
The no-operation instruction (NOP) held in 2 is output to the decoding circuit 13 and held therein. In the latter half of cycle T001,
The value of the PC 15a is increased by 1 and becomes 0001.

In the cycle T002, the reading circuit 12 reads 0001 of the memory circuit 11 according to the value of the PC 15a.
The address data (INS001) is read and held. At this time, the no-operation instruction (NOP) held in the decoding circuit 13 is output and held in the execution circuit 14, and the instruction (INS000) held in the reading circuit 12 is changed to
It is output to the decoding circuit 13, decoded, and then held.
In the latter half of the cycle T002, the value of the PC 15a is increased by 1 and becomes 0002.

In the cycle T003, the reading circuit 12 reads 0002 of the memory circuit 11 according to the value of the PC 15a.
The address data (INS002) is read and held. At this time, the instruction (I
NS000) is output to the execution circuit 14 and executed, and the instruction (INS001) held in the reading circuit 12 is
It is output to the decoding circuit 13, decoded, and then held.
In the latter half of the cycle T003, the value of the PC 15a is increased by 1 and becomes 0003.

By such an operation, the mask ROM 11
According to the processing program stored in a, the pipeline processing by the reading circuit 12, the decoding circuit 13, and the execution circuit 14 is sequentially continued.

In the cycle T204, when the value of the PC 15a becomes 0204, the address signal ADR output from the control circuit 15 becomes 0204, which coincides with the value stored in the register 18a. As a result, the coincidence detection signal is output from the comparator 19a and given to the determination circuit 20. The determination circuit 20 determines which comparator 19 outputs the coincidence detection signal, and the determination result is given to the control circuit 15.

In the control circuit 15, the value of the PC 15a is changed based on the judgment result given from the judgment circuit 20. In this case, the PC 15a has an EEPROM corresponding to the change program at address 0204 of the mask ROM 11a.
The address 11b, 1000, is set. At this time, the command (INS204X) at address 0204 which has already been read by the reading circuit 12 is rewritten to the no-operation command (NOP).

In the cycle T205, the reading circuit 12 sets 1000 of the memory circuit 11 according to the value of the PC 15a.
The address data (JMP1010) is read and held. At this time, the instruction (INS203) held in the decoding circuit 13 is output to the execution circuit 14 and executed, and the instruction (NOP) held in the reading circuit 12 is changed to
It is output to the decoding circuit 13, decoded, and then held.
In the latter half of the cycle T205, the value of the PC 15a is increased by 1 and becomes 1001.

In the cycle T206, the reading circuit 12 causes the memory circuit 111001 to operate in accordance with the value of the PC 15a.
The address data (INS1001 = NOP) is read and held. At this time, the instruction (NOP) held in the decoding circuit 13 is output to the execution circuit 14 and executed, and the instruction (JMP101) held in the reading circuit 12 is executed.
0) is output to the decoding circuit 13 and decoded.

Since the decoded execution instruction is a branch instruction, the result is given to the control circuit 15, and the value of the PC 15a is changed to the branch destination address 1010. In addition, the command (IN
S1001) is rewritten as a no-operation command (NOP). By such processing, the EEPROM 11b 10
The processing of addresses 10 to 1012 is executed, and the mask ROM 1
Return to address 0206 of 1a.

As described above, the DSP of this embodiment has the registers 19a to 19n for setting the address branching from the mask ROM 11a to the EEPROM 11b,
The comparison circuits 19a to 19n for branching to a predetermined address of the EEPROM 11b when the value of the PC 15a and the values of these registers 19a to 19n are compared and coincident with each other.
And a determination circuit 20. Thereby, the mask R
The EEPROM 11 is previously set in the processing program of the OM 11a.
It is not necessary to embed a branch instruction to b, and the troublesomeness in programming can be avoided. In addition, unnecessary branch instructions are not executed, and the processing speed can be improved.

Furthermore, only the necessary parts are stored in the EEPROM 11
Since it can be processed by branching to b,
There is an advantage that it is not necessary to prepare the EPROM 11b.

The present invention is not limited to the above embodiment, and various modifications can be made. Examples of this modification include the following. (A) The capacity of the memory circuit 11 is not limited to the illustrated capacity, and the capacity necessary for processing can be used.

(B) The overall structure of the DSP is not limited to the illustrated one. For example, in the present embodiment, the reading circuit 1
2, the decoding circuit 13 and the execution circuit 14 are configured to perform pipeline processing, but the present invention can be similarly applied to a DSP having a configuration that does not perform pipeline processing.

(C) Mask ROM 11a to EEPR
Although a plurality of registers 19a to 19n are provided to set an address for branching to the OM 11b, if a change or the like is rarely considered, the single register 19 alone can be similarly applied. The advantages of

[0045]

As described in detail above, according to the first invention, a register for registering a specific address of the first memory, a judgment circuit for comparing the value of the register with the value of PC, and the judgment circuit are provided. It has a control circuit for setting a predetermined address of the second memory in this PC when a match is detected in the circuit. As a result, it is not necessary to embed a branch instruction to the second memory in the processing program of the first memory in advance, which facilitates the creation of the program. Further, the processing time is not increased due to unnecessary branch instructions. Further, since it is possible to branch from the arbitrary specific address to the second memory, the processing amount of the second memory, that is, the memory capacity can be reduced.

According to the second aspect of the invention, the reading circuit, the decoding circuit and the execution circuit are configured to perform pipeline processing. Thereby, the processing speed can be improved.

According to the third invention, the register is constructed so that a plurality of specific addresses of the first memory can be registered. As a result, it is possible to perform addition and change processing on a plurality of locations in the processing program of the first memory.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a DSP showing an embodiment of the present invention.

FIG. 2 is a schematic configuration diagram of a conventional DSP.

3 is an explanatory diagram showing an outline of software of FIG. 1. FIG.

FIG. 4 is an explanatory diagram showing the operation of FIG. 1.

[Explanation of symbols]

11 Memory circuit 11a Mask ROM 11b EEPROM 12 reading circuit 13 Decoding circuit 14 Execution circuit 15 Control circuit 15a PC (program counter) 18 registers 19 Comparison circuit 20 Judgment circuit 21 Writing Interface

Claims (3)

[Claims] 1. A memory circuit having a non-rewritable first memory and a rewritable non-volatile second memory, in which a processing program is stored, and a rewritable memory in which a specific address of the first memory is registered. A non-volatile register, a program counter in which the addresses of the processing programs read out from the storage circuit and executed are sequentially stored, a value of the program counter and a value of the register are compared, and a value of the program counter Determines whether or not the specified address matches the specific address, and sets a predetermined address of the second memory in the program counter when a match is detected by the determination circuit, and sets a predetermined address in the program counter when a match is not detected. A control circuit for updating the value of the program counter based on a processing program; A reading circuit that reads the processing program from the storage circuit according to a counter value, a decoding circuit that decodes the processing program read by the reading circuit and decodes into a corresponding execution instruction, and an execution that is decoded by the decoding circuit. A digital signal processing device comprising: an execution circuit that executes instructions. 2. The digital signal processing apparatus according to claim 1, wherein the reading circuit, the decoding circuit, and the execution circuit are configured to perform pipeline processing in parallel at the same time. 3. The digital signal processing apparatus according to claim 1, wherein the register is configured to be able to register a plurality of specific addresses of the first memory.