JP2003177828A - Constant current circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a constant current circuit having a current detecting circuit whose temperature dependency is small, whose output current detecting precision is satisfactory, and which can prevent the decrease of an output voltage or the occurrence of a thermal loss, keep the current ratio of output currents Io to currents Is for detecting output currents constant regardless of the output voltage and optimize the ratio of constant currents Ia to peak currents Ip according to requested specifications by inserting a resistance for detecting output current. <P>SOLUTION: Series circuits to which resistances R1-R4 and PMOS transistors Q1-Q4 are serially connected are connected in parallel between a power supply voltage VDD and an output terminal OUT, and an arithmetic amplifier 2 controls the operations of PMOS transistors Q1-Q4 in order to set a voltage Vs of the connecting part of the resistance R1 and the PMOS transistor Q1 as a reference voltage Vref, and prescribed constant currents Ia are outputted from an output terminal OUT. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a constant current circuit having a current detecting function, and more particularly to a constant current circuit which supplies a predetermined constant current even when an output is short-circuited.

[0002]

2. Description of the Related Art FIG. 7 is a circuit diagram showing an example of a conventional constant current circuit. In the constant current circuit 100 of FIG. 7, most of the output current Io supplied to the load circuit 110 is supplied from the driver transistor 101 which is a PMOS transistor, and the current detection circuit is connected in parallel with the driver transistor 101. The current detection circuit is a series circuit of an output current detection resistor 105 connected in parallel with the driver transistor 101 and an output current detection transistor 106 which is a PMOS transistor, and a predetermined reference voltage Vre.
It is composed of a reference voltage generating circuit 107 for generating and outputting f, and an operational amplifier 108.

The operational amplifier 108 includes a driver transistor 101 and an output current detecting transistor 10 so that the voltage Vs at the connection between the output current detecting resistor 105 and the output current detecting transistor 106 becomes the reference voltage Vref.
6 is controlled so that an output current Io having a predetermined current value Ia is output from the output terminal OUT. At this time, the same signal is input to each gate of the driver transistor 101 and the output current detection transistor 106. Thus, in the constant current circuit 100, the current value of the output current Io is detected by the voltage drop of the output current detection resistor 105. Such a constant current circuit 100 is
It is disclosed in US Pat. No. 4,553,084.

[0004]

Here, the constant current circuit 1 is used.
00 is the result of comparing the voltage Vs obtained from the connection between the output current detection resistor 105 and the output current detection transistor 106 with the reference voltage Vref.
The output signal of 8 is fed back to the gate of the driver transistor 101. In such a constant current circuit 100, the change of the output current Io when the resistance value of the load circuit 110 is changed from infinity to zero, that is, when the output voltage Vo from the output terminal OUT is changed from the power supply voltage VDD to 0V. think about.

The drain of the driver transistor 101
The value obtained by subtracting the voltage drop of the output current detection resistor 105 from the source voltage becomes the drain-source voltage of the output current detection transistor 106. When the output voltage Vo is not much lower than the power supply voltage VDD, that is, when the source-drain voltage of the driver transistor 101 is small, the difference between the drain-source voltage between the driver transistor 101 and the output current detection transistor 106 is calculated. Cannot be ignored. On the other hand, the output voltage V
When o is 0 V, it is considered that the drain-source voltages of the driver transistor 101 and the output current detection transistor 106 are substantially equal to the power supply voltage VDD, and therefore the current I flowing through the output current detection resistor 105 is the same.
There is a problem that the ratio of s and the output current Io changes according to the output voltage Vo.

FIG. 8 shows an example of the relationship between the output voltage Vo and the output current Io in the constant current circuit 100 of FIG. 8A shows an example of the relationship between the voltage Vs and the output voltage Vo, and FIG. 8B shows a characteristic example of the current Is and the output current Io with respect to the output voltage Vo. In FIG. 8, Vo = V
When DD, Io = 0, and the output current Io increases as the output voltage Vo decreases. Output current Io
The voltage Vs at the connecting portion between the output current detecting resistor 105 and the output current detecting transistor 106 also increases with the increase of the.

When Vs = Vref, the operational amplifier 10
8 controls the driver transistor 101 and the output current detection transistor 106 so as to reduce the drain current. Since the drain current of the output current detection transistor 106 decreases, the voltage Vs becomes constant, that is, the current Is becomes constant, and the output current Io is determined from the ratio of the gate sizes of the driver transistor 101 and the output current detection transistor 106. .

However, as shown in FIG. 8, the output voltage Vo
When the voltage drops to the voltage Va, the output current Io becomes a large value of the peak current Ip. Output current detection resistor 10
5, reference voltage Vref, and driver transistor 10
However, there is a problem that the degree of freedom is small such that the constant current Ia and the peak current Ip are determined by determining the gate width ratio between 1 and the output current detection transistor 106. For example, in order to make specifications such that Ia = 0.7 A and Ip = 0.9 A, in the constant current circuit 100 of FIG. 7, the output current detection resistor 105, the reference voltage Vref, and the driver transistor 101 and the output current are used. Detection transistor 1
It was very difficult to determine the ratio between the constant current Ia and the peak current Ip only by adjusting the gate width ratio with 06.

Further, in order to reduce the chip area of the output current detecting resistor 105, it is necessary to use a semiconductor material such as diffusion or polysilicon. When such a material is used, the output current detecting resistor 105 has a resistance value. There is a problem that the temperature dependence of the output current becomes large, and as a result, the voltage Vs for detecting the output current also becomes highly temperature dependent.

On the other hand, as shown in FIG. 9, a constant current circuit 120 having an output current detecting resistor 122 provided between the power supply voltage VDD and the source of the driver transistor 121.
There is. In the constant current circuit 120, the operational amplifier 123
Controls the operation of the driver transistor 121 so that the voltage at the connection between the driver transistor 121 and the output current detection resistor 122 becomes the reference voltage Vref from the reference voltage generation circuit 124. However, in such a configuration, there is a problem that the resistance 122 inserted for detecting the output current causes a decrease in the output voltage Vo and a heat loss.

The present invention has been made in order to solve the above-mentioned problems, and by inserting a resistor for detecting an output current, there is no reduction in the output voltage or heat loss, and there is no relation to the output voltage. The current ratio between the output current Io and the output current detection current Is can be kept constant, and the ratio between the constant current Ia and the peak current Ip can be optimized according to the required specifications, and the temperature dependence It is an object of the present invention to obtain a constant current circuit having a small current detection circuit with a small output current detection accuracy.

[0012]

A constant current circuit according to the present invention is a constant current circuit for supplying a predetermined constant current to a load, wherein a resistor and a transistor for supplying a current to the load are connected in series. An output circuit section in which a plurality of series circuits are connected in parallel, a reference voltage generating circuit section for generating and outputting a predetermined reference voltage, and a predetermined one of the output circuit sections.
And a control circuit unit for controlling the operation of each transistor in each series circuit of the output circuit unit so that the voltage at the connection between the resistor and the transistor in one series circuit becomes the reference voltage from the reference voltage generation circuit unit. It is equipped with.

Specifically, the same transistor is used for each transistor of each series circuit in the output circuit section.

Further, the respective resistances of the series circuits in the output circuit section are made to have the same resistance value.

The resistance of the predetermined one series circuit of the output circuit section is larger than the resistance of the other series circuits, and the resistance of each of the other series circuits is the same. Good.

On the other hand, each resistance of each series circuit in the output circuit section is formed by a wiring resistance made of a metal material.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described in detail based on the embodiments shown in the drawings. FIG. 1 is a diagram showing an example of a constant current circuit according to the first embodiment of the present invention. In FIG. 1, the constant current circuit 1 includes PMOS transistors Q1 to Q4 and resistors R1 to R1 having the same transistor size.
An R4, an operational amplifier 2, and a reference voltage generation circuit 3 for generating and outputting a predetermined reference voltage Vref are provided. In addition,
The PMOS transistors Q1 to Q4 and the resistors R1 to R4 form an output circuit section, and the operational amplifier 2 forms a control circuit section.

Resistors R1 to R4 and PMOS transistor Q
1 to Q4 are correspondingly connected in series, and each series circuit is connected in parallel between the power supply voltage VDD and the output terminal OUT. The operational amplifier 2 has a non-inverting input terminal to which the reference voltage Vref is input, an inverting input terminal to which the output current detection voltage Vs is input from a connecting portion of the resistor R1 and the PMOS transistor Q1, and an output terminal to the PMOS.
The gates of the transistors Q1 to Q4 are respectively connected. A load circuit 1 is provided between the output terminal OUT and the ground voltage.
0 is connected, and the constant current circuit 1 outputs the output current Io as a load current to the load circuit 10.

In such a structure, the resistor R1 serves as a resistor for detecting the output current Io, and the PMOS transistor Q1 serves as a transistor for detecting the output current Io. The operational amplifier 2 includes an output current detection resistor R1.
And the voltage V at the connection between the output current detection transistor Q1 and
The operation control of the PMOS transistors Q1 to Q4 is performed so that s becomes the reference voltage Vref, and the predetermined constant current Ia is output from the output terminal OUT.

Here, a case where the resistors R1 to R4 have the same resistance value will be described. Since the resistance values of the resistors R1 to R4 are equal, a current obtained by dividing the output current Io into four equals P
Each PM flows to the MOS transistors Q1 to Q4.
The source voltages of the OS transistors Q1 to Q4 are equal to each other. The source voltage of the PMOS transistor Q1 becomes the output current detection voltage Vs, and the operational amplifier 2 performs the PMO so that the output current detection voltage Vs becomes the reference voltage Vref.
The operation control of each of the S transistors Q1 to Q4 is performed,
A predetermined constant current Ia is output from the output terminal OUT. At this time, the same signal is input to each gate of the PMOS transistors Q1 to Q4. Thus, in the constant current circuit 1, the current value of the output current Io is detected by the voltage drop of the resistor R1.

Output current Io in the constant current circuit 1 of FIG.
FIG. 2 shows a characteristic example of the output current detection current Is. Figure 2
When Vo = VDD, Io = 0, and the load current Io increases as the output voltage Vo decreases. The output current detection current I increases as the load current Io increases.
s also increases, and the output current detection voltage Vs also increases. Vs
= Vref, the operational amplifier 2 controls the PMOS transistors Q1 to Q4 to reduce the drain current. Since the drain currents of the PMOS transistors Q1 to Q4 decrease, the output current detection voltage Vs becomes constant, that is, the output current detection current Is becomes constant, and the (4 × Is) constant current Ia becomes the output current Io. Is output as. In this way, the constant current circuit 1 is configured as shown in FIG.
As indicated by, the characteristic of the output current Io that becomes the constant current Ia with respect to the output voltage Vo can be obtained.

Here, the layout for integrating the constant current circuit 1 shown in FIG. 1 will be described. Resistance R1
.. to R4 are formed of wiring resistances, and the resistance values can be made the same by making the layout shapes of the wiring resistances the same. For example, PMOS transistors Q1 to Q
4, it is possible to arrange the minimum unit transistors as cells in an array. The wiring used includes polysilicon, diffusion, aluminum wiring, etc., but aluminum wiring can be used for connecting the source / drain portions of the transistor. By arranging the PMOS transistors Q1 to Q4 having a cell structure in an array, the resistors R1 to R4 can be matched while using aluminum wiring. The output current detection voltage Vs is PMOS
The drain may be taken out from the drain of the transistor Q1 closest to the output terminal OUT.

Next, the resistance value of the resistor R1 is equal to that of the resistors R2 to R4.
The case where the resistance value is larger than the resistance value will be described. The resistance values of the resistors R2 to R4 are the same. FIG. 4 is a diagram showing a characteristic example of the output voltage Vo and the drain currents of the PMOS transistors Q1 and Q2 in the constant current circuit 1 in such a case. In FIG. 4, Id1 is P
Indicates the drain current of the MOS transistor Q1, Id2
Indicates the drain current of the PMOS transistor Q2. Since the drain currents of the PMOS transistors Q3 and Q4 are the same as those of the PMOS transistor Q2, the PMOS transistor Q2 will be described as an example.

When Vo = Va, the output current detection voltage Vs reaches the reference voltage Vref, and when Vo <Va, Vs = Id1 ×
The output voltage of the operational amplifier 2 changes so that R1 (the resistance value of the resistor R1) becomes constant, that is, the drain current Id1 becomes a constant current. Next, in the region of Vo> Va, the PMO
The gate Vg of each of the S transistors Q1 and Q2 becomes 0V. Output voltage Vo is from power supply voltage VDD to voltage V
drain currents Id1 and Id as the current decreases to a.
Each 2 increases linearly. Each drain current Id such as the drain currents Id1 and Id2 at this time is expressed by the formula of the MOS transistor in the linear region shown by the following formula (1).

Id = (β / 2) × {2 × (Vgs−Vth) × Vds−Vds ² } ... (1) However, in the equation (1), Vgs is the gate-source voltage, and Vds is Indicates a drain-source voltage, Vth indicates a threshold voltage, and β is a constant represented by the following equation (2). β = μp × Cox × W / L (2) In equation (2), μp is the mobility in the PMOS transistor, Cox is the capacitance per unit area of the gate insulating film, and W is the MOS transistor. Gate width of L, M
The gate lengths of the OS transistors are shown.

From the equation (1), the source-drain resistance Rd in the linear region of the MOS transistor is calculated as shown in the following equation (3). Rd = 1 / (Id / Vds) = 1 / {β × (Vgs−Vth−Vds)} ………………… (3)

Here, for example, VDD = 5V and Rd = 0.
When 1Ω and Ia = 0.5A, Vo-Va = 0.1
When V and Vref = 0.05V, Vds is about 0.05V at maximum in the formula (3). Vo> Va
, The source-drain resistance Rd1 of the PMOS transistor Q1 and the source-drain resistance of the PMOS transistor Q2
Comparing with the drain-to-drain resistance Rd2, if Vgs = 5V and Vth is, for example, 1V in the equation (3), (Vgs-Vth-Vds) in the equation (3) is 5−
Since 1-0.05 = 3.95 and the influence of the drain-source voltage Vds is small, it is possible to set Rd1≈Rd2.

Next, referring to FIG. 4, the PMOS transistor Q2
The drain current Id2 of 1 exhibits a peak value Ip at Vo = Va. FIG. 5 is a diagram showing the drain Id1 of the PMOS transistor Q1 near Vo = Va. In FIG. 5, the solid line indicates the drain current Id1.
The broken line indicates the gate voltage Vg of the PMOS transistor Q1.
Shows an example of the relationship between the output voltage Vo and the drain current Id1 when the current is always 0 V and current limitation is not performed.

In FIG. 5, assuming that the resistance value of the resistor R1 is R1, Vo <Va and Id1 = I1 = (VDD-Vs) /
Since R1 = (VDD-Vref) / R1
The gate voltage Vg of the S-transistor Q1 decreases, which is indicated by four broken lines. The broken line in FIG. 5 shows the drain current Id1, but the drain-source voltage Vds of the PMOS transistor Q1 such as that shown in FIG.
The drain current Id2 can be read at the point E where the difference ΔVd between the drain-source voltages of the PMOS transistors Q1 and Q2 is added to the point A.

Gate voltage V of PMOS transistor Q1
As g decreases, the drain current Id1 becomes A point, B
The gate voltage Vg of the PMOS transistor Q2 also decreases in response to the movement to the points C, D, and the drain current Id2 moves to the points E, F, G, and H. P
The drain-source voltage Vd of the MOS transistor Q1
Even if s becomes large, the maximum value of ΔVd becomes the reference voltage Vref.
This is because. In the drain current Id2, when the value at the point E is reached, the drain current Id1 is the output voltage Vo indicating the value at the point A. Similarly, when the value at the points F to H is reached, the drain current Id1 is reached. Corresponds to B ~
This is when the output voltage Vo indicates the value at point D.

Although the value of the drain current Id2 is made to drop from the E point to the H point, it shows the change from the peak current Ip to the current I2 in FIG. The difference between the peak current Ip and the constant current value I1 is the current difference between points A and E in FIG. 5, which is proportional to ΔVd. FIG. 6 shows resistors R1 and R2.
7 is a diagram showing an equivalent circuit of the PMOS transistors Q1 and Q2, and ΔVd will be described with reference to FIG.

In FIG. 6, Rd1 represents the equivalent resistance of the PMOS transistor Q1, Rd2 represents the equivalent resistance of the PMOS transistor Q2, VR1 represents the voltage across the resistor R1, and VR2 represents the voltage across the resistor R2. The voltage across the equivalent resistance Rd1 is V1, and the equivalent resistance Rd
When the voltage across d2 is V2, the voltages V1 and V2 are expressed by the following equations (4) and (5). V1 = VSW × {Rd / (Rd + R1)} ………… (4) V2 = VSW × {Rd / (Rd + R2)} ………… (5) However, R2 is the resistance value of the resistor R2. Shown, VSW = VR1
+ V1 = VR2 + V2. In the equations (4) and (5), the PMOS transistors Q1 and Q2 are
Since the respective equivalent resistances Rd1 and Rd2 are the same, the respective equivalent resistances are referred to as Rd.

From the expressions (4) and (5), V2-V1
= ΔVd is expressed by the following equation (6). ΔVd = VSW × (R1-R2) / (Rd + R1 + R2 + R1 × R2 / Rd) (6) Since R1> R2, 0 <ΔVd <Vre
f. As described above, the difference between the peak current Ip and the current I1 is proportional to ΔVd, and ΔVd is calculated from the equation (6) by the resistance R
It can be set by the resistance values of 1 and R2.

Next, the difference between the currents I1 and I2 will be described. The drain currents Id1 and Id2 in the saturation region of the MOS transistor are expressed by the following equations (7) and (8). ^{Id1 = β (Vg-VR1-} Vth) 2/2 .................. (7) Id2 = β (Vg-VR2-Vth) 2/2 .................. (8) In addition, the (7) In equations (8) and (8), since the gate voltages of the PMOS transistors Q1 and Q2 are equal, each gate voltage is Vg.

Since the gate voltage Vg is determined by the condition that the drain current Id1 is constant, when the gate voltage Vg is obtained from the equation (7) and substituted into the equation (8),
The drain current Id2 is expressed by the following equation (9). Id2 = {Id1 ^1/2 + (β / 2) ^1/2 × (VR1-Id2 × R2)} ² …………………… (9)

From the above equation (9), the following equation (10) is established. Id2-Id1 = ΔVR × (2 × β × Id1) 1/2 + β × (ΔVR) 2/2 ...... ............ (10) However, it is ΔVR = VR1-VR2. Since the voltage VR1 is constant at (VDD-Vs) = (VDD-Vref) and VR2 = R2 * Id2, (Id2-Id)
1) is determined by R2 from the equation (10).

Thus, the peak current Ip and the constant current I1
And the difference between the constant current I1 and the constant current I2 are
Since it can be determined by each resistance value of 1 and R2, the output current Io can be expressed by the constant current I1 and the constant current I2,
The difference between the peak current Ip and the constant current I1 is determined by the resistors R1 and R2.
It can be determined by each resistance value. In an actual constant current circuit, the number of transistors corresponding to the PMOS transistors Q2 to Q4 can be increased as necessary. Even in this case, the difference between the peak current Ip and the drain current Id1 can be obtained by the resistance values of the resistors R1 and R2. I can decide.

On the other hand, the peak current Ip is the current value at the point E in FIG. 5 and is proportional to the current value at the point A, so that it is expressed by the following equation (11). Ip = (I1 / VSW) × (VSW + ΔVd) = I1 × (1 + ΔVd / VSW) ……………… (11)

By substituting ΔVd in the equation (6) into the equation (11), the following equation (12) is obtained. Ip = I1 × {1+ (R1-R2) / (Rd + R1 + R2 + R1 × R2 / Rd)} …………… (12)

Here, in the conventional case, for example, in the case of the constant current circuit 100 shown in FIG. 7, the peak current Ip is equal to (1)
It suffices if R2 = 0 in the expression (2), which can be expressed as the following expression (13). Ip = I1 × {1 + R1 / (Rd + R1)} ……………… (13)

Since R1> R2, R1> 0 and R2> 0, the second term in the parentheses in the right side of the equations (12) and (13) is compared, and (R1-R2 of the equation (12) is compared. ) Is
It is smaller than R1 in equation (13), and (Rd + in equation (12)
R1 + R2 + R1 × R2 / Rd) is (Rd of the equation (13).
+ R1). Therefore, it can be seen that the peak current Ip of FIG. 4 is smaller than that of the conventional constant current circuit 100 shown in FIG.

As described above, in the constant current circuit according to the first embodiment, each series circuit in which the resistors R1 to R4 and the PMOS transistors Q1 to Q4 are connected in series corresponding to each other outputs the power supply voltage VDD and the output. The operational amplifier 2 is connected in parallel between the terminal OUT and the resistor R1 and PM.
The PMOS transistors Q1 to Q4 are arranged so that the voltage Vs at the connection with the OS transistor Q1 becomes the reference voltage Vref.
Is controlled so that a predetermined constant current Ia is output from the output terminal OUT. Therefore, by inserting the output current detecting resistor, the output voltage Vo does not drop and heat loss does not occur, and the current ratio between the output current Io and the output current detecting current Is is constant regardless of the output voltage Vo. Since the peak current Ip can be reduced, the temperature dependence can be further reduced, and the detection accuracy of the output current can be improved, a predetermined constant current can be accurately supplied. it can.

[0043]

As is apparent from the above description, according to the constant current circuit of the present invention, in the control circuit unit, the voltage of the connection portion between the resistor and the transistor in one predetermined series circuit of the output circuit unit is The operation control of the transistors in each series circuit is performed so that the reference voltage from the reference voltage generating circuit unit is obtained, and a predetermined constant current is output to the load. Therefore, by inserting a resistor for detecting the output current, the current ratio between the output current and the current flowing through the resistor for detecting the output current can be calculated without a decrease in output voltage or heat loss. Since it can be kept constant regardless of the output voltage, the peak value of the output current can be reduced, the temperature dependence can be reduced, and the output current detection accuracy can be improved.
A predetermined constant current can be accurately supplied.

Further, the resistance of the predetermined one series circuit of the output circuit unit is larger than the resistance of the other series circuits, and the resistance of each of the other series circuits has the same resistance value. Therefore, by setting the two types of resistance values, the ratio between the constant current value and the peak current value in the output current can be optimized according to the required specifications.

Specifically, each resistance of each series circuit in the output circuit section is formed by a wiring resistance made of a metal material. From this, the temperature coefficient of the resistance value can be made constant in each resistance of each series circuit in the output circuit unit, so that the temperature characteristic of the output current detection value can be reduced.

[Brief description of drawings]

FIG. 1 is a diagram showing an example of a constant current circuit according to a first embodiment of the present invention.

FIG. 2 is a diagram showing respective characteristic examples of an output current Io and an output current detection current Is with respect to an output voltage Vo in the constant current circuit 1 of FIG.

3 is a diagram showing an example of a relationship between an output current Io and an output voltage Vo in the constant current circuit 1 of FIG.

FIG. 4 is a diagram showing respective characteristic examples of drain currents Id1 and Id2 with respect to the output voltage Vo in the constant current circuit 1 of FIG.

FIG. 5 is a diagram showing a characteristic example of a drain Id1 near Vo = Va.

FIG. 6 shows resistors R1 and R2 and a PMOS transistor Q.
It is the figure which showed the equivalent circuit of 1 and Q2.

FIG. 7 is a circuit diagram showing an example of a conventional constant current circuit.

8 is a diagram showing each characteristic example of a voltage Vs, an output current Io, and a current Is with respect to an output voltage Vo of the constant current circuit 100 of FIG.

FIG. 9 is a circuit diagram showing another example of a conventional constant current circuit.

[Explanation of symbols]

1 constant current circuit 2 Operational amplifier 3 Reference voltage generation circuit 10 load circuit R1 to R4 resistance Q1 to Q4 PMOS transistors OUT output terminal

Claims (5)

[Claims] 1. A constant current circuit for supplying a predetermined constant current to a load, the output comprising a plurality of series circuits in which a resistor and a transistor are connected in series, the current being supplied to the load. A circuit part, a reference voltage generating circuit part for generating and outputting a predetermined reference voltage, and a voltage at a connecting part of a resistor and a transistor in a predetermined one series circuit of the output circuit part from the reference voltage generating circuit part. A control circuit section for controlling the operation of each transistor in each series circuit of the output circuit section so that the reference voltage becomes the reference voltage. 2. The constant current circuit according to claim 1, wherein the respective transistors of the series circuits in the output circuit section are the same transistor. 3. The constant current circuit according to claim 2, wherein the resistances of the series circuits in the output circuit section have the same resistance value. 4. The resistance of the predetermined one series circuit of the output circuit unit has a resistance value larger than that of each of the other series circuits, and the resistance of each of the other series circuits has the same resistance value. The constant current circuit according to claim 2, wherein 5. The constant current circuit according to claim 1, 2, 3 or 4, wherein each resistance of each series circuit in the output circuit section is formed of a wiring resistance made of a metal material.